<s>
Static	B-Application
timing	I-Application
analysis	I-Application
(	O
STA	O
)	O
is	O
a	O
simulation	O
method	O
of	O
computing	O
the	O
expected	O
timing	O
of	O
a	O
synchronous	B-Application
digital	I-Application
circuit	I-Application
without	O
requiring	O
a	O
simulation	O
of	O
the	O
full	O
circuit	O
.	O
</s>
<s>
Moreover	O
,	O
delay	O
calculation	O
must	O
be	O
incorporated	O
into	O
the	O
inner	O
loop	O
of	O
timing	O
optimizers	O
at	O
various	O
phases	O
of	O
design	O
,	O
such	O
as	O
logic	O
synthesis	O
,	O
layout	O
(	O
placement	O
and	O
routing	B-Algorithm
)	O
,	O
and	O
in	O
in-place	O
optimizations	O
performed	O
late	O
in	O
the	O
design	O
cycle	O
.	O
</s>
<s>
While	O
such	O
timing	O
measurements	O
can	O
theoretically	O
be	O
performed	O
using	O
a	O
rigorous	O
circuit	B-Protocol
simulation	I-Protocol
,	O
such	O
an	O
approach	O
is	O
liable	O
to	O
be	O
too	O
slow	O
to	O
be	O
practical	O
.	O
</s>
<s>
Static	B-Application
timing	I-Application
analysis	I-Application
plays	O
a	O
vital	O
role	O
in	O
facilitating	O
the	O
fast	O
and	O
reasonably	O
accurate	O
measurement	O
of	O
circuit	O
timing	O
.	O
</s>
<s>
In	O
a	O
synchronous	B-Application
digital	I-Application
system	I-Application
,	O
data	O
is	O
supposed	O
to	O
move	O
in	O
lockstep	B-General_Concept
,	O
advancing	O
one	O
stage	O
on	O
each	O
tick	O
of	O
the	O
clock	O
signal	O
.	O
</s>
<s>
This	O
is	O
enforced	O
by	O
synchronizing	O
elements	O
such	O
as	O
flip-flops	B-General_Concept
or	O
latches	B-General_Concept
,	O
which	O
copy	O
their	O
input	O
to	O
their	O
output	O
when	O
instructed	O
to	O
do	O
so	O
by	O
the	O
clock	O
.	O
</s>
<s>
The	O
main	O
goal	O
of	O
static	B-Application
timing	I-Application
analysis	I-Application
is	O
to	O
verify	O
that	O
despite	O
these	O
possible	O
variations	O
,	O
all	O
signals	O
will	O
arrive	O
neither	O
too	O
early	O
nor	O
too	O
late	O
,	O
and	O
hence	O
proper	O
circuit	O
operation	O
can	O
be	O
assured	O
.	O
</s>
<s>
Since	O
STA	O
is	O
capable	O
of	O
verifying	O
every	O
path	O
,	O
it	O
can	O
detect	O
other	O
problems	O
like	O
glitches	B-Error_Name
,	O
slow	O
paths	O
and	O
clock	O
skew	O
.	O
</s>
<s>
Arrival	O
times	O
,	O
and	O
indeed	O
almost	O
all	O
times	O
in	O
timing	B-Application
analysis	I-Application
,	O
are	O
normally	O
kept	O
as	O
a	O
pair	O
of	O
values	O
-	O
the	O
earliest	O
possible	O
time	O
at	O
which	O
a	O
signal	O
can	O
change	O
,	O
and	O
the	O
latest	O
.	O
</s>
<s>
The	O
use	O
of	O
corners	O
in	O
static	B-Application
timing	I-Application
analysis	I-Application
has	O
several	O
limitations	O
.	O
</s>
<s>
In	O
static	B-Application
timing	I-Application
analysis	I-Application
,	O
the	O
word	O
static	O
alludes	O
to	O
the	O
fact	O
that	O
this	O
timing	B-Application
analysis	I-Application
is	O
carried	O
out	O
in	O
an	O
input-independent	O
manner	O
,	O
and	O
purports	O
to	O
find	O
the	O
worst-case	O
delay	O
of	O
the	O
circuit	O
over	O
all	O
possible	O
input	O
combinations	O
.	O
</s>
<s>
However	O
,	O
PERT	O
is	O
a	O
misnomer	O
,	O
and	O
the	O
so-called	O
PERT	O
method	O
discussed	O
in	O
most	O
of	O
the	O
literature	O
on	O
timing	B-Application
analysis	I-Application
refers	O
to	O
the	O
critical	O
path	O
method	O
(	O
CPM	O
)	O
that	O
is	O
widely	O
used	O
in	O
project	O
management	O
.	O
</s>
<s>
While	O
the	O
CPM-based	O
methods	O
are	O
the	O
dominant	O
ones	O
in	O
use	O
today	O
,	O
other	O
methods	O
for	O
traversing	O
circuit	O
graphs	O
,	O
such	O
as	O
depth-first	B-Algorithm
search	I-Algorithm
,	O
have	O
been	O
used	O
by	O
various	O
timing	O
analyzers	O
.	O
</s>
<s>
There	O
are	O
specialized	O
CAD	O
tools	O
designed	O
explicitly	O
to	O
analyze	O
interface	O
timing	O
,	O
just	O
as	O
there	O
are	O
specific	O
CAD	O
tools	O
to	O
verify	O
that	O
an	O
implementation	O
of	O
an	O
interface	O
conforms	O
to	O
the	O
functional	O
specification	O
(	O
using	O
techniques	O
such	O
as	O
model	B-Application
checking	I-Application
)	O
.	O
</s>
<s>
Statistical	B-Application
static	I-Application
timing	I-Application
analysis	I-Application
(	O
SSTA	O
)	O
is	O
a	O
procedure	O
that	O
is	O
becoming	O
increasingly	O
necessary	O
to	O
handle	O
the	O
complexities	O
of	O
process	O
and	O
environmental	O
variations	O
in	O
integrated	O
circuits	O
.	O
</s>
