<s>
Static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
static	B-Architecture
RAM	I-Architecture
or	O
SRAM	O
)	O
is	O
a	O
type	O
of	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
that	O
uses	O
latching	O
circuitry	O
(	O
flip-flop	B-General_Concept
)	O
to	O
store	O
each	O
bit	O
.	O
</s>
<s>
SRAM	O
is	O
volatile	B-General_Concept
memory	I-General_Concept
;	O
data	O
is	O
lost	O
when	O
power	O
is	O
removed	O
.	O
</s>
<s>
The	O
term	O
static	O
differentiates	O
SRAM	O
from	O
DRAM	O
(	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
)	O
—	O
SRAM	O
will	O
hold	O
its	O
data	O
permanently	O
in	O
the	O
presence	O
of	O
power	O
,	O
while	O
data	O
in	O
DRAM	O
decays	O
in	O
seconds	O
and	O
thus	O
must	O
be	O
periodically	O
refreshed	B-General_Concept
.	O
</s>
<s>
SRAM	O
is	O
faster	O
than	O
DRAM	O
but	O
it	O
is	O
more	O
expensive	O
in	O
terms	O
of	O
silicon	O
area	O
and	O
cost	O
;	O
it	O
is	O
typically	O
used	O
for	O
the	O
cache	B-General_Concept
and	O
internal	O
registers	B-General_Concept
of	O
a	O
CPU	B-Device
while	O
DRAM	O
is	O
used	O
for	O
a	O
computer	O
's	O
main	O
memory	O
.	O
</s>
<s>
The	O
SRAM	O
was	O
the	O
main	O
driver	O
behind	O
any	O
new	O
CMOS-based	O
technology	O
fabrication	B-Architecture
process	I-Architecture
since	O
1959	O
when	O
CMOS	B-Device
was	O
invented	O
.	O
</s>
<s>
In	O
1965	O
,	O
Arnold	O
Farber	O
and	O
Eugene	O
Schlig	O
,	O
working	O
for	O
IBM	O
,	O
created	O
a	O
hard-wired	O
memory	B-Algorithm
cell	I-Algorithm
,	O
using	O
a	O
transistor	B-Application
gate	O
and	O
tunnel	O
diode	O
latch	B-General_Concept
.	O
</s>
<s>
They	O
replaced	O
the	O
latch	B-General_Concept
with	O
two	O
transistors	B-Application
and	O
two	O
resistors	O
,	O
a	O
configuration	O
that	O
became	O
known	O
as	O
the	O
Farber-Schlig	O
cell	O
.	O
</s>
<s>
In	O
1965	O
,	O
Benjamin	O
Agusta	O
and	O
his	O
team	O
at	O
IBM	O
created	O
a	O
16-bit	O
silicon	O
memory	O
chip	O
based	O
on	O
the	O
Farber-Schlig	O
cell	O
,	O
with	O
80	O
transistors	B-Application
,	O
64	O
resistors	O
,	O
and	O
4	O
diodes	O
.	O
</s>
<s>
In	O
April	O
1969	O
Intel	O
inc	O
.	O
introduced	O
its	O
first	O
product	O
,	O
Intel	O
3101	O
,	O
a	O
SRAM	O
memory	O
chip	O
intended	O
to	O
replace	O
bulky	O
magnetic	O
core	O
memory	O
modules	O
;	O
Its	O
capacity	O
was	O
64	O
bits	O
(	O
only	O
63	O
bits	O
were	O
usable	O
due	O
to	O
a	O
bug	O
)	O
and	O
was	O
based	O
on	O
bipolar	O
junction	O
transistors	B-Application
it	O
was	O
designed	O
by	O
using	O
rubylith	O
.	O
</s>
<s>
Though	O
it	O
can	O
be	O
characterized	O
as	O
volatile	B-General_Concept
memory	I-General_Concept
,	O
SRAM	O
exhibits	O
data	O
remanence	O
.	O
</s>
<s>
Since	O
SRAM	O
requires	O
more	O
transistors	B-Application
per	O
bit	O
to	O
implement	O
,	O
it	O
is	O
less	O
dense	O
and	O
more	O
expensive	O
than	O
DRAM	O
and	O
also	O
has	O
a	O
higher	O
power	O
consumption	O
during	O
read	O
or	O
write	O
access	O
.	O
</s>
<s>
Many	O
categories	O
of	O
industrial	O
and	O
scientific	O
subsystems	O
,	O
automotive	O
electronics	O
,	O
and	O
similar	O
embedded	B-Architecture
systems	I-Architecture
,	O
contain	O
SRAM	O
which	O
,	O
in	O
this	O
context	O
,	O
may	O
be	O
referred	O
to	O
as	O
ESRAM	O
.	O
</s>
<s>
SRAM	O
in	O
its	O
dual-ported	B-General_Concept
form	O
is	O
sometimes	O
used	O
for	O
real-time	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
circuits	O
.	O
</s>
<s>
SRAM	O
is	O
also	O
used	O
in	O
personal	O
computers	O
,	O
workstations	O
,	O
routers	B-Protocol
and	O
peripheral	O
equipment	O
:	O
CPU	B-General_Concept
register	I-General_Concept
files	O
,	O
internal	O
CPU	B-General_Concept
caches	I-General_Concept
,	O
internal	O
GPU	O
caches	O
and	O
external	O
burst	B-Architecture
mode	I-Architecture
SRAM	O
caches	O
,	O
hard	B-Device
disk	I-Device
buffers	O
,	O
router	B-Protocol
buffers	O
,	O
etc	O
.	O
</s>
<s>
LCD	B-Device
screens	I-Device
and	O
printers	O
also	O
normally	O
employ	O
SRAM	O
to	O
hold	O
the	O
image	O
displayed	O
(	O
or	O
to	O
be	O
printed	O
)	O
.	O
</s>
<s>
SRAM	O
was	O
used	O
for	O
the	O
main	O
memory	O
of	O
many	O
early	O
personal	O
computers	O
such	O
as	O
the	O
ZX80	B-Operating_System
,	O
TRS-80	B-Operating_System
Model	I-Operating_System
100	I-Operating_System
,	O
and	O
VIC-20	B-Device
.	O
</s>
<s>
Non-volatile	B-Architecture
SRAM	I-Architecture
(	O
nvSRAM	B-Architecture
)	O
has	O
standard	O
SRAM	O
functionality	O
,	O
but	O
they	O
save	O
the	O
data	O
when	O
the	O
power	O
supply	O
is	O
lost	O
,	O
ensuring	O
preservation	O
of	O
critical	O
information	O
.	O
</s>
<s>
nvSRAMs	B-Architecture
are	O
used	O
in	O
a	O
wide	O
range	O
of	O
situationsnetworking	O
,	O
aerospace	O
,	O
and	O
medical	O
,	O
among	O
many	O
otherswhere	O
the	O
preservation	O
of	O
data	O
is	O
critical	O
and	O
where	O
batteries	O
are	O
impractical	O
.	O
</s>
<s>
Pseudostatic	O
RAM	B-Architecture
(	O
PSRAM	O
)	O
is	O
DRAM	O
combined	O
with	O
a	O
self-refresh	O
circuit	O
.	O
</s>
<s>
Asynchronous	B-Application
independent	O
of	O
clock	O
frequency	O
;	O
data	O
in	O
and	O
data	O
out	O
are	O
controlled	O
by	O
address	O
transition	O
.	O
</s>
<s>
Examples	O
include	O
the	O
ubiquitous	O
28-pin	O
8K×8	O
and	O
32K×8	O
chips	O
(	O
often	O
but	O
not	O
always	O
named	O
something	O
along	O
the	O
lines	O
of	O
6264	B-General_Concept
and	O
62C256	O
respectively	O
)	O
,	O
as	O
well	O
as	O
similar	O
products	O
up	O
to	O
16Mbit	O
per	O
chip	O
.	O
</s>
<s>
In	O
the	O
1990s	O
,	O
asynchronous	B-Application
SRAM	O
used	O
to	O
be	O
employed	O
for	O
fast	O
access	O
time	O
.	O
</s>
<s>
Asynchronous	B-Application
SRAM	O
was	O
used	O
as	O
main	O
memory	O
for	O
small	O
cache-less	O
embedded	B-Architecture
processors	I-Architecture
used	O
in	O
everything	O
from	O
industrial	O
electronics	O
and	O
measurement	O
systems	O
to	O
hard	B-Device
disks	I-Device
and	O
networking	O
equipment	O
,	O
among	O
many	O
other	O
applications	O
.	O
</s>
<s>
DDR	O
SRAM	O
)	O
is	O
rather	O
employed	O
similarly	O
to	O
synchronous	O
DRAMDDR	O
SDRAM	O
memory	O
is	O
rather	O
used	O
than	O
asynchronous	B-Application
DRAM	O
.	O
</s>
<s>
Synchronous	O
memory	O
interface	O
is	O
much	O
faster	O
as	O
access	O
time	O
can	O
be	O
significantly	O
reduced	O
by	O
employing	O
pipeline	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
SRAM	O
memory	O
is	O
mainly	O
used	O
for	O
CPU	B-General_Concept
cache	I-General_Concept
,	O
small	O
on-chip	O
memory	O
,	O
FIFOs	O
or	O
other	O
small	O
buffers	O
.	O
</s>
<s>
Quad	B-General_Concept
Data	I-General_Concept
Rate	I-General_Concept
SRAM	I-General_Concept
synchronous	O
,	O
separate	O
read	O
and	O
write	O
ports	O
,	O
quadruple	O
data	O
rate	O
I/O	O
.	O
</s>
<s>
SRAM	O
may	O
be	O
integrated	O
as	O
RAM	B-Architecture
or	O
cache	B-General_Concept
memory	O
in	O
micro-controllers	B-Architecture
(	O
usually	O
from	O
around	O
32bytes	O
up	O
to	O
128kilobytes	O
)	O
,	O
as	O
the	O
primary	O
caches	O
in	O
powerful	O
microprocessors	O
,	O
such	O
as	O
the	O
x86	B-Operating_System
family	O
,	O
and	O
many	O
others	O
(	O
from	O
8KB	O
,	O
up	O
to	O
many	O
megabytes	O
)	O
,	O
to	O
store	O
the	O
registers	B-General_Concept
and	O
parts	O
of	O
the	O
state-machines	O
used	O
in	O
some	O
microprocessors	O
(	O
see	O
register	B-General_Concept
file	I-General_Concept
)	O
,	O
on	O
application-specific	O
integrated	O
circuits	O
(	O
ASICs	O
)	O
(	O
usually	O
in	O
the	O
order	O
of	O
kilobytes	O
)	O
and	O
in	O
field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGAs	B-Architecture
)	O
and	O
complex	B-General_Concept
programmable	I-General_Concept
logic	I-General_Concept
devices	I-General_Concept
(	O
CPLDs	B-General_Concept
)	O
.	O
</s>
<s>
A	O
typical	O
SRAM	B-Algorithm
cell	I-Algorithm
is	O
made	O
up	O
of	O
six	O
MOSFETs	B-Architecture
,	O
and	O
is	O
often	O
called	O
a	O
SRAM	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
Each	O
bit	O
in	O
the	O
cell	O
is	O
stored	O
on	O
four	O
transistors	B-Application
(	O
M1	O
,	O
M2	O
,	O
M3	O
,	O
M4	O
)	O
that	O
form	O
two	O
cross-coupled	O
inverters	O
.	O
</s>
<s>
Two	O
additional	O
access	O
transistors	B-Application
serve	O
to	O
control	O
the	O
access	O
to	O
a	O
storage	O
cell	O
during	O
read	O
and	O
write	O
operations	O
.	O
</s>
<s>
In	O
addition	O
to	O
6T	O
SRAM	O
,	O
other	O
kinds	O
of	O
SRAM	O
chips	O
use	O
4	O
,	O
8	O
,	O
10	O
(	O
4T	O
,	O
8T	O
,	O
10T	O
SRAM	O
)	O
,	O
or	O
more	O
transistors	B-Application
per	O
bit	O
.	O
</s>
<s>
Four-transistor	O
SRAM	O
is	O
quite	O
common	O
in	O
stand-alone	O
SRAM	O
devices	O
(	O
as	O
opposed	O
to	O
SRAM	O
used	O
for	O
CPU	B-General_Concept
caches	I-General_Concept
)	O
,	O
implemented	O
in	O
special	O
processes	O
with	O
an	O
extra	O
layer	O
of	O
polysilicon	O
,	O
allowing	O
for	O
very	O
high-resistance	O
pull-up	O
resistors	O
.	O
</s>
<s>
The	O
principal	O
drawback	O
of	O
using	O
4T	O
SRAM	O
is	O
increased	O
static	O
power	O
due	O
to	O
the	O
constant	O
current	O
flow	O
through	O
one	O
of	O
the	O
pull-down	O
transistors	B-Application
(	O
M1	O
or	O
M2	O
)	O
.	O
</s>
<s>
This	O
is	O
sometimes	O
used	O
to	O
implement	O
more	O
than	O
one	O
(	O
read	O
and/or	O
write	O
)	O
port	O
,	O
which	O
may	O
be	O
useful	O
in	O
certain	O
types	O
of	O
video	O
memory	O
and	O
register	B-General_Concept
files	I-General_Concept
implemented	O
with	O
multi-ported	O
SRAM	O
circuitry	O
.	O
</s>
<s>
Generally	O
,	O
the	O
fewer	O
transistors	B-Application
needed	O
per	O
cell	O
,	O
the	O
smaller	O
each	O
cell	O
can	O
be	O
.	O
</s>
<s>
Memory	B-Algorithm
cells	I-Algorithm
that	O
use	O
fewer	O
than	O
four	O
transistors	B-Application
are	O
possible	O
;	O
however	O
,	O
such	O
3T	O
or	O
1T	O
cells	O
are	O
DRAM	O
,	O
not	O
SRAM	O
(	O
even	O
the	O
so-called	O
1T-SRAM	O
)	O
.	O
</s>
<s>
Access	O
to	O
the	O
cell	O
is	O
enabled	O
by	O
the	O
word	O
line	O
(	O
WL	O
in	O
figure	O
)	O
which	O
controls	O
the	O
two	O
access	O
transistors	B-Application
M5	O
and	O
M6	O
which	O
,	O
in	O
turn	O
,	O
control	O
whether	O
the	O
cell	O
should	O
be	O
connected	O
to	O
the	O
bit	O
lines	O
:	O
BL	O
and	O
BL	O
.	O
</s>
<s>
During	O
read	O
accesses	O
,	O
the	O
bit	O
lines	O
are	O
actively	O
driven	O
high	O
and	O
low	O
by	O
the	O
inverters	O
in	O
the	O
SRAM	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
The	O
dimensions	O
of	O
an	O
SRAM	B-Algorithm
cell	I-Algorithm
on	O
an	O
IC	O
is	O
determined	O
by	O
the	O
minimum	O
feature	O
size	O
of	O
the	O
process	O
used	O
to	O
make	O
the	O
IC	O
.	O
</s>
<s>
An	O
SRAM	B-Algorithm
cell	I-Algorithm
has	O
three	O
different	O
states	O
:	O
standby	O
(	O
the	O
circuit	O
is	O
idle	O
)	O
,	O
reading	O
(	O
the	O
data	O
has	O
been	O
requested	O
)	O
or	O
writing	O
(	O
updating	O
the	O
contents	O
)	O
.	O
</s>
<s>
If	O
the	O
word	O
line	O
is	O
not	O
asserted	O
,	O
the	O
access	O
transistors	B-Application
M5	O
and	O
M6	O
disconnect	O
the	O
cell	O
from	O
the	O
bit	O
lines	O
.	O
</s>
<s>
In	O
theory	O
,	O
reading	O
only	O
requires	O
asserting	O
the	O
word	O
line	O
WL	O
and	O
reading	O
the	O
SRAM	B-Algorithm
cell	I-Algorithm
state	O
by	O
a	O
single	O
access	O
transistor	B-Application
and	O
bit	O
line	O
,	O
e.g.	O
</s>
<s>
Then	O
asserting	O
the	O
word	O
line	O
WL	O
enables	O
both	O
the	O
access	O
transistors	B-Application
M5	O
and	O
M6	O
,	O
which	O
causes	O
one	O
bit	O
line	O
BL	O
voltage	O
to	O
slightly	O
drop	O
.	O
</s>
<s>
This	O
is	O
similar	O
to	O
applying	O
a	O
reset	O
pulse	O
to	O
an	O
SR-latch	B-General_Concept
,	O
which	O
causes	O
the	O
flip	B-General_Concept
flop	I-General_Concept
to	O
change	O
state	O
.	O
</s>
<s>
This	O
works	O
because	O
the	O
bit	O
line	O
input-drivers	O
are	O
designed	O
to	O
be	O
much	O
stronger	O
than	O
the	O
relatively	O
weak	O
transistors	B-Application
in	O
the	O
cell	O
itself	O
so	O
they	O
can	O
easily	O
override	O
the	O
previous	O
state	O
of	O
the	O
cross-coupled	O
inverters	O
.	O
</s>
<s>
In	O
practice	O
,	O
access	O
NMOS	B-Architecture
transistors	I-Architecture
M5	O
and	O
M6	O
have	O
to	O
be	O
stronger	O
than	O
either	O
bottom	O
NMOS	O
(	O
M1	O
,	O
M3	O
)	O
or	O
top	O
PMOS	O
(	O
M2	O
,	O
M4	O
)	O
transistors	B-Application
.	O
</s>
<s>
This	O
is	O
easily	O
obtained	O
as	O
PMOS	B-Architecture
transistors	I-Architecture
are	O
much	O
weaker	O
than	O
NMOS	O
when	O
same	O
sized	O
.	O
</s>
<s>
Consequently	O
,	O
when	O
one	O
transistor	B-Application
pair	O
(	O
e.g.	O
</s>
<s>
M3	O
and	O
M4	O
)	O
is	O
only	O
slightly	O
overridden	O
by	O
the	O
write	O
process	O
,	O
the	O
opposite	O
transistors	B-Application
pair	O
(	O
M1	O
and	O
M2	O
)	O
gate	O
voltage	O
is	O
also	O
changed	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
M1	O
and	O
M2	O
transistors	B-Application
can	O
be	O
easier	O
overridden	O
,	O
and	O
so	O
on	O
.	O
</s>
<s>
RAM	B-Architecture
with	O
an	O
access	O
time	O
of	O
70ns	O
will	O
output	O
valid	O
data	O
within	O
70ns	O
from	O
the	O
time	O
that	O
the	O
address	O
lines	O
are	O
valid	O
.	O
</s>
<s>
Some	O
SRAM	B-Algorithm
cells	I-Algorithm
have	O
a	O
"	O
page	O
mode	O
"	O
,	O
where	O
words	O
of	O
a	O
page	O
(	O
256	O
,	O
512	O
,	O
or	O
1024	O
words	O
)	O
can	O
be	O
read	O
sequentially	O
with	O
a	O
significantly	O
shorter	O
access	O
time	O
(	O
typically	O
approximately	O
30ns	O
)	O
.	O
</s>
<s>
With	O
the	O
introduction	O
of	O
the	O
FinFET	O
transistor	B-Application
implementation	O
of	O
SRAM	B-Algorithm
cells	I-Algorithm
,	O
they	O
started	O
to	O
suffer	O
from	O
increasing	O
inefficiencies	O
in	O
cell	O
sizes	O
.	O
</s>
<s>
Over	O
the	O
last	O
30	O
years	O
(	O
from	O
1987	O
to	O
2017	O
)	O
with	O
a	O
steadily	O
decreasing	O
transistor	B-Architecture
size	I-Architecture
(	O
node	O
size	O
)	O
the	O
footprint-shrinking	O
of	O
the	O
SRAM	B-Algorithm
cell	I-Algorithm
topology	O
itself	O
slowed	O
down	O
,	O
making	O
it	O
harder	O
to	O
pack	O
the	O
cells	O
more	O
densely	O
.	O
</s>
<s>
Besides	O
issues	O
with	O
size	O
a	O
significant	O
challenge	O
of	O
modern	O
SRAM	B-Algorithm
cells	I-Algorithm
is	O
a	O
static	O
current	O
leakage	O
.	O
</s>
<s>
With	O
these	O
two	O
issues	O
it	O
became	O
more	O
challenging	O
to	O
develop	O
energy-efficient	O
and	O
dense	O
SRAM	O
memories	O
,	O
prompting	O
semiconductor	O
industry	O
to	O
look	O
for	O
alternatives	O
such	O
as	O
STT-MRAM	O
and	O
F-RAM	O
.	O
</s>
<s>
In	O
2019	O
a	O
French	O
institute	O
reported	O
on	O
a	O
research	O
of	O
an	O
IoT-purposed	O
28nm	B-Architecture
fabricated	O
IC	O
.	O
</s>
<s>
It	O
was	O
based	O
on	O
fully	O
depleted	O
silicon	O
on	O
insulator-transistors	O
(	O
FD-SOI	B-Algorithm
)	O
,	O
had	O
two-ported	O
SRAM	O
memory	O
rail	O
for	O
synchronous/asynchronous	O
accesses	O
,	O
and	O
selective	O
virtual	O
ground	O
(	O
SVGND	O
)	O
.	O
</s>
