<s>
In	O
integrated	O
circuit	O
design	O
,	O
dynamic	O
logic	O
(	O
or	O
sometimes	O
clocked	O
logic	O
)	O
is	O
a	O
design	O
methodology	O
in	O
combinational	O
logic	O
circuits	O
,	O
particularly	O
those	O
implemented	O
in	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
technology	O
.	O
</s>
<s>
It	O
is	O
distinguished	O
from	O
the	O
so-called	O
static	B-General_Concept
logic	I-General_Concept
by	O
exploiting	O
temporary	O
storage	O
of	O
information	O
in	O
stray	O
and	O
gate	O
capacitances	O
.	O
</s>
<s>
It	O
was	O
popular	O
in	O
the	O
1970s	O
and	O
has	O
seen	O
a	O
recent	O
resurgence	O
in	O
the	O
design	O
of	O
high-speed	O
digital	O
electronics	O
,	O
particularly	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	O
)	O
.	O
</s>
<s>
Dynamic	O
logic	O
has	O
a	O
higher	O
average	O
rate	O
of	O
voltage	O
transitions	O
than	O
static	B-General_Concept
logic	I-General_Concept
,	O
but	O
the	O
capacitive	O
loads	O
being	O
transitioned	O
are	O
smaller	O
so	O
the	O
overall	O
power	O
consumption	O
of	O
dynamic	O
logic	O
may	O
be	O
higher	O
or	O
lower	O
depending	O
on	O
various	O
tradeoffs	O
.	O
</s>
<s>
When	O
referring	O
to	O
a	O
particular	O
logic	B-General_Concept
family	I-General_Concept
,	O
the	O
dynamic	O
adjective	O
usually	O
suffices	O
to	O
distinguish	O
the	O
design	O
methodology	O
,	O
e.g.	O
</s>
<s>
dynamic	O
CMOS	B-Device
or	O
dynamic	O
SOI	B-Algorithm
design	O
.	O
</s>
<s>
Besides	O
its	O
use	O
of	O
dynamic	O
state	O
storage	O
via	O
voltages	O
on	O
capacitances	O
,	O
dynamic	O
logic	O
is	O
distinguished	O
from	O
so-called	O
static	B-General_Concept
logic	I-General_Concept
in	O
that	O
dynamic	O
logic	O
uses	O
a	O
clock	O
signal	O
in	O
its	O
implementation	O
of	O
combinational	O
logic	O
.	O
</s>
<s>
static	B-Architecture
RAM	I-Architecture
from	O
dynamic	O
RAM	O
,	O
in	O
that	O
dynamic	O
RAM	O
stores	O
state	O
dynamically	O
as	O
voltages	O
on	O
capacitances	O
,	O
which	O
must	O
be	O
periodically	O
refreshed	O
.	O
</s>
<s>
But	O
there	O
are	O
also	O
differences	O
in	O
usage	O
;	O
the	O
clock	O
can	O
be	O
stopped	O
in	O
the	O
appropriate	O
phase	O
in	O
a	O
system	O
with	O
dynamic	O
logic	O
and	O
static	B-Architecture
storage	I-Architecture
.	O
</s>
<s>
In	O
most	O
types	O
of	O
logic	O
design	O
,	O
termed	O
static	B-General_Concept
logic	I-General_Concept
,	O
there	O
is	O
always	O
some	O
mechanism	O
to	O
drive	O
the	O
output	O
either	O
high	O
or	O
low	O
.	O
</s>
<s>
In	O
many	O
of	O
the	O
popular	O
logic	O
styles	O
,	O
such	O
as	O
TTL	B-General_Concept
and	O
traditional	O
CMOS	B-Device
,	O
this	O
principle	O
can	O
be	O
rephrased	O
as	O
a	O
statement	O
that	O
there	O
is	O
always	O
a	O
low-impedance	O
DC	O
path	O
between	O
the	O
output	O
and	O
either	O
the	O
supply	O
voltage	O
or	O
the	O
ground	O
.	O
</s>
<s>
As	O
a	O
side	O
note	O
,	O
there	O
is	O
,	O
of	O
course	O
,	O
an	O
exception	O
in	O
this	O
definition	O
in	O
the	O
case	O
of	O
high	O
impedance	O
outputs	O
,	O
such	O
as	O
a	O
tri-state	O
buffer	O
;	O
however	O
,	O
even	O
in	O
these	O
cases	O
,	O
the	O
circuit	O
is	O
intended	O
to	O
be	O
used	O
within	O
a	O
larger	O
system	O
where	O
some	O
mechanism	O
will	O
drive	O
the	O
output	O
,	O
and	O
they	O
do	O
not	O
qualify	O
as	O
distinct	O
from	O
static	B-General_Concept
logic	I-General_Concept
.	O
</s>
<s>
Static	B-General_Concept
logic	I-General_Concept
has	O
no	O
minimum	O
clock	O
rate	O
—	O
the	O
clock	O
can	O
be	O
paused	O
indefinitely	O
.	O
</s>
<s>
being	O
able	O
to	O
pause	O
a	O
system	O
at	O
any	O
time	O
makes	O
debugging	O
and	O
testing	O
much	O
easier	O
,	O
enabling	O
techniques	O
such	O
as	O
single	B-General_Concept
stepping	I-General_Concept
.	O
</s>
<s>
While	O
there	O
are	O
other	O
mechanisms	O
to	O
do	O
this	O
,	O
such	O
as	O
interrupts	O
,	O
polling	O
loops	O
,	O
processor	O
idling	O
input	O
pins	O
(	O
for	O
example	O
,	O
RDY	O
on	O
the	O
6502	B-General_Concept
)	O
,	O
or	O
processor	O
bus	O
cycle	O
extension	O
mechanisms	O
such	O
as	O
WAIT	O
inputs	O
,	O
using	O
hardware	O
to	O
gate	O
the	O
clock	O
to	O
a	O
static-core	O
CPU	O
is	O
simpler	O
,	O
is	O
more	O
temporally	O
precise	O
,	O
uses	O
no	O
program	O
code	O
memory	O
,	O
and	O
uses	O
almost	O
no	O
power	O
in	O
the	O
CPU	O
while	O
it	O
is	O
waiting	O
.	O
</s>
<s>
In	O
particular	O
,	O
although	O
many	O
popular	O
CPUs	O
use	O
dynamic	O
logic	O
,	O
only	O
static	B-General_Concept
cores	I-General_Concept
—	O
CPUs	O
designed	O
with	O
fully	O
static	O
technology	O
—	O
are	O
usable	O
in	O
space	O
satellites	O
owing	O
to	O
their	O
higher	O
radiation	O
hardness	O
.	O
</s>
<s>
When	O
properly	O
designed	O
,	O
dynamic	O
logic	O
can	O
be	O
over	O
twice	O
as	O
fast	O
as	O
static	B-General_Concept
logic	I-General_Concept
.	O
</s>
<s>
Static	B-General_Concept
logic	I-General_Concept
is	O
slower	O
because	O
it	O
has	O
twice	O
the	O
capacitive	O
loading	O
,	O
higher	O
thresholds	O
,	O
and	O
uses	O
slow	O
P	O
transistors	O
for	O
logic	O
.	O
</s>
<s>
Most	O
electronics	O
running	O
at	O
over	O
2GHz	O
these	O
days	O
require	O
dynamic	O
logic	O
,	O
although	O
some	O
manufacturers	O
such	O
as	O
Intel	O
have	O
designed	O
chips	O
using	O
completely	O
static	B-General_Concept
logic	I-General_Concept
to	O
reduce	O
power	O
consumption	O
.	O
</s>
<s>
In	O
general	O
,	O
dynamic	O
logic	O
greatly	O
increases	O
the	O
number	O
of	O
transistors	O
that	O
are	O
switching	O
at	O
any	O
given	O
time	O
,	O
which	O
increases	O
power	O
consumption	O
over	O
static	O
CMOS	B-Device
.	O
</s>
<s>
As	O
an	O
example	O
,	O
consider	O
the	O
static	B-General_Concept
logic	I-General_Concept
implementation	O
of	O
a	O
CMOS	B-Device
NAND	O
gate	O
:	O
</s>
<s>
Dynamic	O
logic	O
has	O
a	O
few	O
potential	O
problems	O
that	O
static	B-General_Concept
logic	I-General_Concept
does	O
not	O
.	O
</s>
<s>
A	O
popular	O
implementation	O
is	O
domino	B-General_Concept
logic	I-General_Concept
.	O
</s>
