<s>
MIPS	B-Device
,	O
an	O
acronym	O
for	O
Microprocessor	B-General_Concept
without	I-General_Concept
Interlocked	I-General_Concept
Pipeline	I-General_Concept
Stages	I-General_Concept
,	O
was	O
a	O
research	O
project	O
conducted	O
by	O
John	O
L	O
.	O
Hennessy	O
at	O
Stanford	O
University	O
between	O
1981	O
and	O
1984	O
.	O
</s>
<s>
MIPS	B-Device
investigated	O
a	O
type	O
of	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
now	O
called	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-General_Concept
)	O
,	O
its	O
implementation	O
as	O
a	O
microprocessor	B-Architecture
with	O
very	O
large	O
scale	O
integration	O
(	O
VLSI	O
)	O
semiconductor	O
technology	O
,	O
and	O
the	O
effective	O
exploitation	O
of	O
RISC	B-Architecture
architectures	I-Architecture
with	O
optimizing	B-Application
compilers	I-Application
.	O
</s>
<s>
MIPS	B-Device
,	O
together	O
with	O
the	O
IBM	B-Device
801	I-Device
and	O
Berkeley	B-General_Concept
RISC	I-General_Concept
,	O
were	O
the	O
three	O
research	O
projects	O
that	O
pioneered	O
and	O
popularized	O
RISC	B-General_Concept
technology	O
in	O
the	O
mid-1980s	O
.	O
</s>
<s>
In	O
recognition	O
of	O
the	O
impact	O
MIPS	B-Device
made	O
on	O
computing	O
,	O
Hennessey	O
was	O
awarded	O
the	O
IEEE	O
John	O
von	O
Neumann	O
Medal	O
in	O
2000	O
by	O
the	O
Institute	O
of	O
Electrical	O
and	O
Electronics	O
Engineers	O
(	O
IEEE	O
)	O
(	O
shared	O
with	O
David	O
A	O
.	O
Patterson	O
)	O
,	O
the	O
Eckert	O
–	O
Mauchly	O
Award	O
in	O
2001	O
by	O
the	O
Association	O
for	O
Computing	O
Machinery	O
,	O
the	B-Device
Seymour	I-Device
Cray	I-Device
Computer	I-Device
Engineering	I-Device
Award	I-Device
in	O
2001	O
by	O
the	O
IEEE	O
Computer	O
Society	O
,	O
and	O
,	O
again	O
with	O
David	O
Patterson	O
,	O
the	O
Turing	O
Award	O
in	O
2017	O
by	O
the	O
ACM	O
.	O
</s>
<s>
The	O
project	O
was	O
initiated	O
in	O
1981	O
in	O
response	O
to	O
reports	O
of	O
similar	O
projects	O
at	O
IBM	O
(	O
the	O
801	B-Device
)	O
and	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
(	O
the	O
RISC	B-General_Concept
)	O
.	O
</s>
<s>
MIPS	B-Device
was	O
conducted	O
by	O
Hennessy	O
and	O
his	O
graduate	O
students	O
until	O
its	O
conclusion	O
in	O
1984	O
.	O
</s>
<s>
Hennessey	O
founded	O
MIPS	B-Device
Computer	O
Systems	O
in	O
the	O
same	O
year	O
to	O
commercialize	O
the	O
technology	O
developed	O
by	O
the	O
project	O
.	O
</s>
<s>
In	O
1985	O
,	O
MIPS	B-Device
Computer	O
Systems	O
announced	O
a	O
new	O
ISA	O
,	O
also	O
called	O
MIPS	B-Device
,	O
and	O
its	O
first	O
implementation	O
,	O
the	O
R2000	B-Device
microprocessor	I-Device
.	O
</s>
<s>
The	O
commercial	O
MIPS	B-Device
ISA	I-Device
,	O
and	O
its	O
implementations	O
went	O
on	O
to	O
be	O
widely	O
used	O
,	O
appearing	O
in	O
embedded	O
computers	O
,	O
personal	O
computers	O
,	O
workstations	O
,	O
servers	O
,	O
and	O
supercomputers	O
.	O
</s>
<s>
As	O
of	O
May	O
2017	O
,	O
the	O
commercial	O
MIPS	B-Device
ISA	I-Device
is	O
owned	O
by	O
Imagination	O
Technologies	O
,	O
and	O
is	O
used	O
mainly	O
in	O
embedded	O
computers	O
.	O
</s>
<s>
In	O
the	O
late	O
1980s	O
,	O
a	O
follow-up	O
project	O
called	O
MIPS-X	B-General_Concept
was	O
conducted	O
by	O
Hennessy	O
at	O
Stanford	O
.	O
</s>
<s>
The	O
MIPS	B-Device
ISA	I-Device
was	O
based	O
on	O
a	O
32-bit	O
word	O
.	O
</s>
<s>
It	O
was	O
a	O
load/store	O
architectureall	O
references	O
to	O
memory	O
used	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
that	O
copied	O
data	O
between	O
the	O
main	O
memory	O
and	O
32	O
general-purpose	O
registers	O
(	O
GPRs	O
)	O
.	O
</s>
<s>
It	O
possessed	O
a	O
basic	O
instruction	B-General_Concept
set	I-General_Concept
consisting	O
of	O
instructions	O
for	O
control	O
flow	O
,	O
integer	O
arithmetic	O
,	O
and	O
logical	O
operations	O
.	O
</s>
<s>
There	O
were	O
no	O
instructions	O
for	O
integer	O
multiplication	O
or	O
division	O
,	O
or	O
operations	O
for	O
floating-point	B-Algorithm
numbers	I-Algorithm
.	O
</s>
<s>
The	O
architecture	O
exposed	O
all	O
hazards	B-General_Concept
caused	O
by	O
the	O
five-stage	O
pipeline	O
with	O
delay	B-General_Concept
slots	I-General_Concept
.	O
</s>
<s>
The	O
compiler	O
scheduled	O
instructions	O
to	O
avoid	O
hazards	B-General_Concept
resulting	O
in	O
incorrect	O
computation	O
whilst	O
simultaneously	O
ensuring	O
that	O
the	O
generated	O
code	O
minimized	O
execution	O
time	O
.	O
</s>
<s>
MIPS	B-Device
instructions	O
are	O
16	O
or	O
32	O
bit	O
long	O
.	O
</s>
<s>
The	O
decision	O
to	O
expose	O
all	O
hazards	B-General_Concept
was	O
motivated	O
by	O
the	O
desire	O
to	O
maximize	O
performance	O
by	O
minimizing	O
critical	O
paths	O
,	O
which	O
interlock	O
circuits	O
lengthened	O
.	O
</s>
<s>
Instructions	O
were	O
packed	O
into	O
32-bit	O
instruction	O
words	O
(	O
as	O
MIPS	B-Device
is	O
word-addressed	O
)	O
.	O
</s>
<s>
The	O
MIPS	B-Device
microprocessor	B-Architecture
was	O
implemented	O
in	O
NMOS	B-Algorithm
logic	I-Algorithm
.	O
</s>
