<s>
SpursEngine	B-General_Concept
is	O
a	O
microprocessor	B-Architecture
from	O
Toshiba	O
built	O
as	O
a	O
media	O
oriented	O
coprocessor	B-General_Concept
,	O
designed	O
for	O
3D	O
-	O
and	O
video	O
processing	O
in	O
consumer	O
electronics	O
such	O
as	O
set-top	O
boxes	O
and	O
computers	O
.	O
</s>
<s>
The	O
SpursEngine	B-General_Concept
processor	O
is	O
also	O
known	O
as	O
the	O
Quad	O
Core	O
HD	O
processor	O
.	O
</s>
<s>
The	O
SpursEngine	B-General_Concept
is	O
a	O
stream	B-Application
processor	I-Application
powered	O
by	O
four	O
Synergistic	O
Processing	O
Elements	O
(	O
SPE	O
)	O
,	O
also	O
used	O
in	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
featured	O
in	O
Sony	B-Operating_System
PlayStation	I-Operating_System
3	I-Operating_System
.	O
</s>
<s>
These	O
processing	O
elements	O
are	O
fed	O
by	O
on	O
chip	O
H.264	B-Application
and	O
MPEG-2	B-Algorithm
codecs	B-General_Concept
and	O
controlled	O
by	O
an	O
off	O
die	O
host	O
CPU	B-Device
,	O
connected	O
by	O
an	O
on	O
chip	O
PCIe	O
controller	O
(	O
in	O
contrast	O
to	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
which	O
has	O
an	O
on	O
chip	O
CPU	B-Device
(	O
the	O
PPE	O
)	O
doing	O
similar	O
work	O
)	O
.	O
</s>
<s>
To	O
enable	O
smoother	O
interaction	O
between	O
the	O
host	O
and	O
the	O
SpursEngine	B-General_Concept
Toshiba	O
also	O
integrated	O
a	O
simple	O
proprietary	O
32-bit	O
control	O
core	O
.	O
</s>
<s>
The	O
SpursEngine	B-General_Concept
employs	O
dedicated	O
XDR	O
DRAM	O
as	O
its	O
working	O
memory	O
.	O
</s>
<s>
The	O
SpursEngine	B-General_Concept
is	O
designed	O
to	O
work	O
at	O
much	O
lower	O
frequencies	O
than	O
the	O
Cell	O
and	O
Toshiba	O
has	O
also	O
optimized	O
the	O
circuit	O
layout	O
of	O
the	O
SPEs	O
to	O
reduce	O
the	O
size	O
by	O
30%	O
.	O
</s>
<s>
The	O
SpursEngine	B-General_Concept
is	O
accessible	O
to	O
the	O
developer	O
from	O
a	O
device	B-Application
driver	I-Application
developed	O
for	O
Windows	B-Application
and	O
Linux	B-Application
systems	O
.	O
</s>
<s>
Software	O
supporting	O
the	O
SpursEngine	B-General_Concept
is	O
limited	O
and	O
is	O
primarily	O
in	O
the	O
realm	O
of	O
video	O
editing	O
and	O
encoding	O
.	O
</s>
<s>
The	O
first	O
generation	O
of	O
SpursEngine	B-General_Concept
processors	O
are	O
specified	O
as	O
follows	O
:	O
</s>
<s>
In	O
April	O
2008	O
Toshiba	O
shipped	O
samples	O
of	O
the	O
SpursEngine	B-General_Concept
SE1000	O
device	O
,	O
a	O
PCIe-based	O
reference	O
board	O
.	O
</s>
<s>
Toshiba	O
included	O
the	O
SpursEngine	B-General_Concept
processors	O
in	O
their	O
Qosmio	B-Device
laptops	O
,	O
models	O
F50	O
,	O
G50	O
and	O
G55	O
,	O
in	O
the	O
third	O
quarter	O
of	O
2008	O
.	O
</s>
