<s>
Spacer	B-Algorithm
patterning	I-Algorithm
is	O
a	O
technique	O
employed	O
for	O
patterning	O
features	O
with	O
linewidths	O
smaller	O
than	O
can	O
be	O
achieved	O
by	O
conventional	O
lithography	O
.	O
</s>
<s>
Hence	O
this	O
is	O
a	O
readily	O
practiced	O
form	O
of	O
multiple	B-Algorithm
patterning	I-Algorithm
.	O
</s>
<s>
Whereas	O
immersion	B-Algorithm
lithography	I-Algorithm
has	O
a	O
resolution	O
of	O
~	O
40nm	O
lines	O
and	O
spaces	O
,	O
spacer	B-Algorithm
patterning	I-Algorithm
may	O
be	O
applied	O
to	O
attain	O
20nm	O
.	O
</s>
<s>
This	O
resolution	O
improvement	O
technique	O
is	O
also	O
known	O
as	O
Self-Aligned	O
Double	B-Algorithm
Patterning	I-Algorithm
(	O
SADP	O
)	O
.	O
</s>
<s>
SADP	O
may	O
be	O
re-applied	O
for	O
even	O
higher	O
resolution	O
,	O
and	O
has	O
already	O
been	O
demonstrated	O
for	O
15nm	O
NAND	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Spacer	B-Algorithm
patterning	I-Algorithm
has	O
also	O
been	O
adopted	O
for	O
sub-20nm	O
logic	O
nodes	O
,	O
e.g.	O
,	O
14	B-Algorithm
nm	I-Algorithm
and	O
10	B-Algorithm
nm	I-Algorithm
.	O
</s>
<s>
The	O
mandrel	O
is	O
not	O
removed	O
after	O
the	O
spacer	O
is	O
etched	O
to	O
leave	O
only	O
the	O
sidewall	O
portion	O
,	O
in	O
the	O
case	O
where	O
the	O
mandrel	O
is	O
the	O
MOSFET	B-Architecture
gate	O
stack	O
.	O
</s>
<s>
The	O
silicon	O
nitride	O
sidewall	O
spacer	O
is	O
retained	O
to	O
protect	O
the	O
gate	O
stack	O
and	O
underlying	O
gate	B-Algorithm
oxide	I-Algorithm
during	O
subsequent	O
processing	O
.	O
</s>
<s>
An	O
approach	O
related	O
derived	O
from	O
self-aligned	O
spacer	O
double	B-Algorithm
patterning	I-Algorithm
is	O
so-called	O
"	O
anti-spacer	O
"	O
double	B-Algorithm
patterning	I-Algorithm
.	O
</s>
<s>
The	O
anti-spacer	O
double	B-Algorithm
patterning	I-Algorithm
approach	O
described	O
above	O
naturally	O
fits	O
the	O
SID	O
approach	O
since	O
an	O
additional	O
layer	O
is	O
deposited	O
after	O
the	O
spacer	O
before	O
its	O
removal	O
.	O
</s>
