<s>
The	O
southbridge	B-Device
is	O
one	O
of	O
the	O
two	O
chips	O
in	O
the	O
core	O
logic	O
chipset	B-Device
on	O
a	O
personal	B-Device
computer	I-Device
(	O
PC	O
)	O
motherboard	B-Device
,	O
the	O
other	O
being	O
the	O
northbridge	B-Device
.	O
</s>
<s>
The	O
southbridge	B-Device
typically	O
implements	O
the	O
slower	O
capabilities	O
of	O
the	O
motherboard	B-Device
in	O
a	O
northbridge/southbridge	O
chipset	B-Device
computer	O
architecture	O
.	O
</s>
<s>
In	O
systems	O
with	O
Intel	O
chipsets	B-Device
,	O
the	O
southbridge	B-Device
is	O
named	O
I/O	B-Device
Controller	I-Device
Hub	I-Device
(	O
ICH	O
)	O
,	O
while	O
AMD	O
has	O
named	O
its	O
southbridge	B-Device
Fusion	B-Architecture
Controller	O
Hub	O
(	O
FCH	O
)	O
since	O
the	O
introduction	O
of	O
its	O
Fusion	B-Architecture
Accelerated	B-Architecture
Processing	I-Architecture
Unit	I-Architecture
(	O
APU	O
)	O
while	O
moving	O
the	O
functions	O
of	O
the	O
Northbridge	B-Device
onto	O
the	O
CPU	B-General_Concept
die	O
,	O
hence	O
making	O
it	O
similar	O
in	O
function	O
to	O
the	O
Platform	O
hub	O
controller	O
.	O
</s>
<s>
The	O
southbridge	B-Device
can	O
usually	O
be	O
distinguished	O
from	O
the	O
northbridge	B-Device
by	O
not	O
being	O
directly	O
connected	O
to	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Rather	O
,	O
the	O
northbridge	B-Device
ties	O
the	O
southbridge	B-Device
to	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Through	O
the	O
use	O
of	O
controller	O
integrated	O
channel	O
circuitry	O
,	O
the	O
northbridge	B-Device
can	O
directly	O
link	O
signals	O
from	O
the	O
I/O	O
units	O
to	O
the	O
CPU	B-General_Concept
for	O
data	O
control	O
and	O
access	O
.	O
</s>
<s>
Due	O
to	O
the	O
push	O
for	O
system-on-chip	B-Architecture
(	O
SoC	O
)	O
processors	O
,	O
modern	O
devices	O
increasingly	O
have	O
the	O
northbridge	B-Device
integrated	O
into	O
the	O
CPU	B-General_Concept
die	O
itself	O
;	O
examples	O
are	O
Intel	O
's	O
Sandy	B-Device
Bridge	I-Device
and	O
AMD	O
's	O
Fusion	B-Architecture
processors	O
,	O
both	O
released	O
in	O
2011	O
.	O
</s>
<s>
The	O
southbridge	B-Device
became	O
redundant	O
and	O
it	O
was	O
replaced	O
by	O
the	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
architecture	O
introduced	O
with	O
the	O
Intel	B-Device
5	I-Device
Series	I-Device
chipset	B-Device
in	O
2008	O
while	O
AMD	O
did	O
the	O
same	O
with	O
the	O
release	O
of	O
their	O
first	O
APUs	O
in	O
2011	O
,	O
naming	O
the	O
PCH	O
the	O
Fusion	B-Architecture
controller	O
hub	O
(	O
FCH	O
)	O
,	O
which	O
was	O
only	O
used	O
on	O
AMD	O
's	O
APUs	O
until	O
2017	O
when	O
it	O
began	O
to	O
be	O
used	O
on	O
AMD	O
's	O
Zen	O
architecture	O
while	O
dropping	O
the	O
FCH	O
name	O
.	O
</s>
<s>
On	O
Intel	O
platforms	O
,	O
all	O
southbridge	B-Device
features	O
and	O
remaining	O
I/O	O
functions	O
are	O
managed	O
by	O
the	O
PCH	O
which	O
is	O
directly	O
connected	O
to	O
the	O
CPU	B-General_Concept
via	O
the	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	O
)	O
.	O
</s>
<s>
Based	O
on	O
its	O
Chiplet	O
design	O
,	O
AMD	O
Ryzen	O
processors	O
also	O
integrated	O
some	O
southbridge	B-Device
functions	O
,	O
such	O
as	O
some	O
USB	B-Protocol
interface	O
and	O
some	O
SATA/NVMe	O
interface	O
.	O
</s>
<s>
A	O
southbridge	B-Device
chipset	B-Device
handled	O
many	O
of	O
a	O
computer	O
's	O
I/O	O
functions	O
,	O
such	O
as	O
USB	B-Protocol
,	O
audio	O
,	O
the	O
system	B-Operating_System
BIOS	I-Operating_System
,	O
the	O
ISA	B-Architecture
bus	I-Architecture
or	O
the	O
LPC	O
bus	O
,	O
the	O
low	O
speed	O
PCI/PCIe	O
bus	O
,	O
the	O
IOAPIC	B-Device
interrupt	B-Architecture
controller	I-Architecture
,	O
the	O
SATA	O
storage	O
,	O
the	O
historical	O
PATA	B-Protocol
storage	O
,	O
and	O
the	O
NVMe	B-Application
storage	O
.	O
</s>
<s>
Different	O
combinations	O
of	O
Southbridge	B-Device
and	O
Northbridge	B-Device
chips	I-Device
are	O
possible	O
,	O
but	O
these	O
two	O
kinds	O
of	O
chips	O
must	O
be	O
designed	O
to	O
work	O
together	O
;	O
there	O
is	O
no	O
industry-wide	O
standard	O
for	O
interoperability	O
between	O
different	O
core	O
logic	O
chipset	B-Device
designs	O
.	O
</s>
<s>
In	O
the	O
1990s	O
and	O
early	O
2000s	O
,	O
the	O
interface	O
between	O
a	O
northbridge	B-Device
and	O
southbridge	B-Device
was	O
the	O
PCI	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
As	O
of	O
2023	O
,	O
the	O
main	O
bridging	O
interfaces	O
used	O
are	O
Ultra	B-Architecture
Path	I-Architecture
Interconnect	I-Architecture
(	O
Intel	O
)	O
and	O
PCI	B-Protocol
Express	O
(	O
AMD	O
)	O
.	O
</s>
<s>
The	O
name	O
is	O
derived	O
from	O
representing	O
the	O
architecture	O
in	O
the	O
fashion	O
of	O
a	O
map	O
and	O
was	O
first	O
described	O
as	O
such	O
with	O
the	O
introduction	O
of	O
the	O
PCI	B-Protocol
Local	I-Protocol
Bus	I-Protocol
Architecture	O
in	O
1991	O
.	O
</s>
<s>
At	O
Intel	O
,	O
the	O
authors	O
of	O
the	O
PCI	B-Protocol
specification	O
viewed	O
the	O
PCI	B-Protocol
local	I-Protocol
bus	I-Protocol
as	O
being	O
at	O
the	O
very	O
centre	O
of	O
the	O
PC	O
platform	O
architecture	O
(	O
i.e.	O
,	O
at	O
the	O
Equator	O
)	O
.	O
</s>
<s>
The	O
northbridge	B-Device
extends	O
to	O
the	O
north	O
of	O
the	O
PCI	B-Architecture
bus	I-Architecture
backbone	O
in	O
support	O
of	O
CPU	B-General_Concept
,	O
memory/cache	O
,	O
and	O
other	O
performance-critical	O
capabilities	O
.	O
</s>
<s>
Likewise	O
the	O
southbridge	B-Device
extends	O
to	O
the	O
south	O
of	O
the	O
PCI	B-Architecture
bus	I-Architecture
backbone	O
and	O
bridges	O
to	O
less	O
performance-critical	O
I/O	O
capabilities	O
such	O
as	O
the	O
disk	O
interface	O
,	O
audio	O
,	O
etc	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
is	O
located	O
at	O
the	O
top	O
of	O
the	O
map	O
at	O
due	O
north	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
is	O
connected	O
to	O
the	O
chipset	B-Device
via	O
a	O
fast	O
bridge	O
(	O
the	O
northbridge	B-Device
)	O
located	O
north	O
of	O
other	O
system	O
devices	O
as	O
drawn	O
.	O
</s>
<s>
The	O
northbridge	B-Device
is	O
connected	O
to	O
the	O
rest	O
of	O
the	O
chipset	B-Device
via	O
a	O
slow	O
bridge	O
(	O
the	O
southbridge	B-Device
)	O
located	O
south	O
of	O
other	O
system	O
devices	O
as	O
drawn	O
.	O
</s>
<s>
Although	O
the	O
current	O
PC	O
platform	O
architecture	O
has	O
replaced	O
the	O
PCI	B-Architecture
bus	I-Architecture
backbone	O
with	O
faster	O
I/O	O
backbones	O
,	O
the	O
bridge	O
naming	O
convention	O
remains	O
.	O
</s>
<s>
The	O
functionality	O
found	O
in	O
a	O
contemporary	O
southbridge	B-Device
includes	O
:	O
</s>
<s>
PCI	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
A	O
south	O
bridge	O
may	O
also	O
include	O
support	O
for	O
PCI-X	O
.	O
</s>
<s>
Low	O
speed	O
PCI	B-Protocol
Express	O
(	O
PCIe	O
)	O
interfaces	O
usually	O
for	O
Ethernet	O
and	O
NVMe	B-Application
.	O
</s>
<s>
ISA	B-Architecture
bus	I-Architecture
or	O
LPC	O
bridge	O
.	O
</s>
<s>
ISA	B-Architecture
slots	I-Architecture
are	O
no	O
longer	O
provided	O
on	O
more	O
recent	O
motherboards	B-Device
.	O
</s>
<s>
The	O
LPC	O
bridge	O
provides	O
a	O
data	O
and	O
control	O
path	O
to	O
the	O
super	B-Device
I/O	I-Device
(	O
the	O
normal	O
attachment	O
for	O
the	O
PS/2	B-Protocol
keyboard	I-Protocol
and	O
mouse	O
,	O
parallel	O
port	O
,	O
serial	O
port	O
,	O
IR	O
port	O
,	O
and	O
floppy	O
controller	O
)	O
.	O
</s>
<s>
SPI	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
SPI	B-Architecture
bus	I-Architecture
is	O
a	O
simple	O
serial	O
bus	O
mostly	O
used	O
for	O
firmware	B-Application
(	O
e.g.	O
,	O
BIOS/UEFI	O
)	O
flash	B-Device
storage	I-Device
access	O
.	O
</s>
<s>
SMBus	B-Algorithm
controller	O
.	O
</s>
<s>
DMA	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
The	O
8237	B-Device
DMA	B-General_Concept
controller	I-General_Concept
allows	O
ISA	O
or	O
LPC	O
devices	O
direct	O
access	O
to	O
main	O
memory	O
without	O
needing	O
help	O
from	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
PIC	B-Architecture
and	O
I/O	B-Device
APIC	I-Device
.	O
</s>
<s>
Mass	B-Device
storage	I-Device
interfaces	O
such	O
as	O
SATA	O
,	O
M.2	B-Protocol
,	O
and	O
historical	O
PATA	B-Protocol
.	O
</s>
<s>
This	O
typically	O
allows	O
attachment	O
of	O
hard	B-Device
drives	I-Device
or	O
SSDs	B-Device
.	O
</s>
<s>
Programmable	B-Device
interval	I-Device
timer	I-Device
.	O
</s>
<s>
ACPI	B-Device
controller	O
or	O
APM	B-Device
controller	O
.	O
</s>
<s>
Nonvolatile	B-Device
BIOS	I-Device
memory	I-Device
.	O
</s>
<s>
The	O
system	O
CMOS	B-Device
(	O
BIOS	B-Operating_System
configuration	O
memory	O
)	O
,	O
assisted	O
by	O
battery	O
supplemental	O
power	O
,	O
creates	O
a	O
limited	O
non-volatile	B-General_Concept
storage	I-General_Concept
area	O
for	O
BIOS	B-Operating_System
configuration	O
data	O
.	O
</s>
<s>
USB	B-Protocol
interfaces	O
.	O
</s>
<s>
Optionally	O
,	O
a	O
southbridge	B-Device
also	O
includes	O
support	O
(	O
onboard	O
discrete	O
chip	O
or	O
southbridge-integrated	O
)	O
for	O
Ethernet	O
,	O
Wi-Fi	O
,	O
RAID	B-Architecture
,	O
Thunderbolt	B-Protocol
,	O
and	O
Out-of-band	B-Application
management	I-Application
.	O
</s>
