<s>
A	O
soft	B-Device
microprocessor	I-Device
(	O
also	O
called	O
softcore	B-Device
microprocessor	I-Device
or	O
a	O
soft	B-Device
processor	I-Device
)	O
is	O
a	O
microprocessor	B-Architecture
core	I-Architecture
that	O
can	O
be	O
wholly	O
implemented	O
using	O
logic	O
synthesis	O
.	O
</s>
<s>
It	O
can	O
be	O
implemented	O
via	O
different	O
semiconductor	O
devices	O
containing	O
programmable	O
logic	O
(	O
e.g.	O
,	O
ASIC	O
,	O
FPGA	B-Architecture
,	O
CPLD	B-General_Concept
)	O
,	O
including	O
both	O
high-end	O
and	O
commodity	O
variations	O
.	O
</s>
<s>
Most	O
systems	O
,	O
if	O
they	O
use	O
a	O
soft	B-Device
processor	I-Device
at	O
all	O
,	O
only	O
use	O
a	O
single	O
soft	B-Device
processor	I-Device
.	O
</s>
<s>
However	O
,	O
a	O
few	O
designers	O
tile	O
as	O
many	O
soft	O
cores	O
onto	O
an	O
FPGA	B-Architecture
as	O
will	O
fit	O
.	O
</s>
<s>
In	O
those	O
multi-core	B-Architecture
systems	O
,	O
rarely	O
used	O
resources	O
can	O
be	O
shared	O
between	O
all	O
the	O
cores	O
in	O
a	O
cluster	O
.	O
</s>
<s>
While	O
many	O
people	O
put	O
exactly	O
one	O
soft	B-Device
microprocessor	I-Device
on	O
a	O
FPGA	B-Architecture
,	O
a	O
sufficiently	O
large	O
FPGA	B-Architecture
can	O
hold	O
two	O
or	O
more	O
soft	B-Device
microprocessors	I-Device
,	O
resulting	O
in	O
a	O
multi-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
The	O
number	O
of	O
soft	B-Device
processors	I-Device
on	O
a	O
single	O
FPGA	B-Architecture
is	O
limited	O
only	O
by	O
the	O
size	O
of	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
Some	O
people	O
have	O
put	O
dozens	O
or	O
hundreds	O
of	O
soft	B-Device
microprocessors	I-Device
on	O
a	O
single	O
FPGA	B-Architecture
.	O
</s>
<s>
This	O
is	O
one	O
way	O
to	O
implement	O
massive	B-Operating_System
parallelism	I-Operating_System
in	O
computing	O
and	O
can	O
likewise	O
be	O
applied	O
to	O
in-memory	B-General_Concept
computing	I-General_Concept
.	O
</s>
<s>
A	O
soft	B-Device
microprocessor	I-Device
and	O
its	O
surrounding	O
peripherals	O
implemented	O
in	O
a	O
FPGA	B-Architecture
is	O
less	O
vulnerable	O
to	O
obsolescence	O
than	O
a	O
discrete	O
processor	O
.	O
</s>
<s>
Processor	O
Developer	O
Open	O
source	O
Bus	O
support	O
Notes	O
Project	O
home	O
Description	O
language	O
based	O
on	O
the	O
ARM	B-Architecture
instruction	I-Architecture
set	I-Architecture
architecture	O
Amber	B-Device
Conor	O
Santifort	O
Wishbone	B-Architecture
ARMv2a	B-Architecture
3-stage	O
or	O
5-stage	O
pipeline	O
Project	O
page	O
at	O
Opencores	O
Verilog	B-Language
Cortex-M1	O
ARM	B-Architecture
70	O
–	O
200MHz	O
,	O
32-bit	O
RISC	O
Verilog	B-Language
based	O
on	O
the	O
AVR	B-Architecture
instruction	O
set	O
architecture	O
Navré	O
Sébastien	O
Bourdeauducq	O
Direct	O
SRAM	O
Atmel	O
AVR-compatible	O
8-bit	O
RISC	O
Project	O
page	O
at	O
Opencores	O
Verilog	B-Language
pAVR	O
Doru	O
Cuturela	O
Atmel	O
AVR-compatible	O
8-bit	O
RISC	O
Project	O
page	O
at	O
Opencores	O
VHDL	B-Language
softavrcore	O
Andras	O
Pal	O
Standard	O
AVR	B-Architecture
buses	O
(	O
core-coupled	O
I/O	O
,	O
synchronous	O
SRAM	O
,	O
synchronous	O
program	O
ROM	O
)	O
Atmel	O
AVR-compatible	O
8-bit	O
RISC	O
(	O
up	O
to	O
AVR5	O
)	O
,	O
peripherals	O
and	O
SoC	O
features	O
included	O
Project	O
page	O
at	O
Opencores	O
Verilog	B-Language
based	O
on	O
the	O
MicroBlaze	B-Device
instruction	O
set	O
architecture	O
AEMB	O
Shawn	O
Tan	O
Wishbone	B-Architecture
MicroBlaze	B-Device
EDK	O
3.2	O
compatible	O
AEMB	O
Verilog	B-Language
MicroBlaze	B-Device
Xilinx	O
PLB	O
,	O
OPB	O
,	O
FSL	O
,	O
LMB	O
,	O
AXI4	O
Xilinx	O
MicroBlaze	B-Device
OpenFire	O
Virginia	O
Tech	O
CCM	O
Lab	O
OPB	O
,	O
FSL	O
Binary	O
compatible	O
with	O
the	O
MicroBlaze	B-Device
Verilog	B-Language
SecretBlaze	O
LIRMM	O
,	O
University	O
of	O
Montpellier	O
/	O
CNRS	O
Wishbone	B-Architecture
MicroBlaze	B-Device
ISA	O
,	O
VHDL	B-Language
SecretBlaze	O
VHDL	B-Language
based	O
on	O
the	O
MCS-51	B-Architecture
instruction	O
set	O
architecture	O
MCL51	O
MicroCore	O
Labs	O
Ultra-small-footprint	O
microsequencer-based	O
8051	B-Architecture
core	O
312	O
Artix-7	O
LUTs	O
.	O
</s>
<s>
Quad-core	B-Architecture
8051	B-Architecture
version	O
is	O
1227	O
LUTs	O
.	O
</s>
<s>
MCL51	O
Core	O
TSK51/52	O
Altium	B-Algorithm
Wishbone	B-Architecture
/	O
Intel	B-Architecture
8051	I-Architecture
8-bit	O
Intel	B-Architecture
8051	I-Architecture
instruction	O
set	O
compatible	O
,	O
lower	O
clock	O
cycle	O
alternative	O
Embedded	O
Design	O
on	O
Altium	B-Algorithm
Wiki	O
based	O
on	O
the	O
MIPS	B-Device
instruction	I-Device
set	I-Device
architecture	O
BERI	O
University	O
of	O
Cambridge	O
MIPS	B-Device
Project	O
page	O
Bluespec	O
Dossmatik	O
René	O
Doss	O
Pipelined	O
bus	O
MIPS	B-Device
I	O
instruction	O
set	O
pipeline	O
stages	O
Dossmatik	O
VHDL	B-Language
TSK3000A	O
Altium	B-Algorithm
Wishbone	B-Architecture
32-bit	O
R3000-style	O
RISC	O
modified	O
Harvard-architecture	O
CPU	O
Embedded	O
Design	O
on	O
Altium	B-Algorithm
Wiki	O
based	O
on	O
the	O
PicoBlaze	B-Device
instruction	O
set	O
architecture	O
PacoBlaze	O
Pablo	O
Bleyer	O
Compatible	O
with	O
the	O
PicoBlaze	B-Device
processors	O
PacoBlaze	O
Verilog	B-Language
PicoBlaze	B-Device
Xilinx	O
Xilinx	O
PicoBlaze	B-Device
VHDL	B-Language
,	O
Verilog	B-Language
based	O
on	O
the	O
RISC-V	B-Device
instruction	O
set	O
architecture	O
f32c	O
University	O
of	O
Zagreb	O
AXI	B-Protocol
,	O
SDRAM	O
,	O
SRAM	O
32-bit	O
,	O
RISC-V	B-Device
/	O
MIPS	B-Device
ISA	I-Device
subsets	O
(	O
retargetable	O
)	O
,	O
GCC	O
toolchain	O
f32c	O
VHDL	B-Language
NEORV32	O
Stephan	O
Nolting	O
Wishbone	B-Architecture
b4	O
,	O
AXI4	O
rv32[i/e]	O
 [ m ] 	O
 [ a ] 	O
 [ c ] 	O
 [ b ] 	O
 [ u ] 	O
 [ Zfinx ] 	O
 [ Zicsr ] 	O
[Zifencei],	O
RISC-V-compliant	O
,	O
CPU	O
&	O
SoC	O
available	O
,	O
highly	O
customizable	O
,	O
GCC	O
toolchain	O
GitHub	O
OpenCores	O
VHDL	B-Language
VexRiscvSpinalHDL	O
AXI4	O
/	O
Avalon	O
32-bit	O
,	O
RISC-V	B-Device
,	O
up	O
to	O
340MHz	O
on	O
Artix	O
7	O
.	O
</s>
<s>
https://github.com/SpinalHDL/VexRiscv	O
VHDLVerilog	O
(	O
SpinalHDL	O
)	O
based	O
on	O
the	O
SPARC	B-Architecture
instruction	O
set	O
architecture	O
LEON2(-FT )	O
ESA	O
AMBA2	O
SPARC	B-Architecture
V8	I-Architecture
ESA	O
VHDL	B-Language
LEON3/4	B-General_Concept
Aeroflex	O
Gaisler	O
AMBA2	O
SPARC	B-Architecture
V8	I-Architecture
Aeroflex	O
Gaisler	O
VHDL	B-Language
OpenPiton	O
Princeton	O
Parallel	O
Group	O
Manycore	B-General_Concept
SPARC	B-Architecture
V9	I-Architecture
OpenPiton	O
Verilog	B-Language
OpenSPARC	B-Device
T1	I-Device
Sun	O
64-bit	O
OpenSPARC.net	O
Verilog	B-Language
Tacus/PIPE5	O
TemLib	O
Pipelined	O
bus	O
SPARC	B-Architecture
V8	I-Architecture
TEMLIB	O
VHDL	B-Language
based	O
on	O
the	O
x86	B-Operating_System
instruction	O
set	O
architecture	O
CPU86	O
HT-Lab	O
8088-compatible	O
CPU	O
in	O
VHDL	B-Language
cpu86	O
VHDL	B-Language
MCL86	O
MicroCore	O
Labs	O
8088	O
BIU	O
provided	O
.	O
</s>
<s>
MCL86	O
Core	O
s80x86	O
Jamie	O
Iles	O
Custom	O
80186-compatible	O
GPLv3	O
core	O
s80x86	O
SystemVerilog	B-Language
Zet	B-Device
Zeus	O
Gómez	O
Marmolejo	O
Wishbone	B-Architecture
x86	B-Operating_System
PC	O
clone	O
Zet	B-Device
Verilog	B-Language
ao486	O
Aleksander	O
Osman	O
Avalon	O
i486	O
SX	O
compatible	O
core	O
ao486	O
Verilog	B-Language
based	O
on	O
the	O
PowerPC/Power	B-Architecture
instruction	O
set	O
architecture	O
PowerPC	O
405S	O
IBM	O
CoreConnect	B-Architecture
32-bit	O
PowerPC	O
v.2.03	O
Book	O
E	O
IBM	O
Verilog	B-Language
PowerPC	O
440S	O
IBM	O
CoreConnect	B-Architecture
32-bit	O
PowerPC	O
v.2.03	O
Book	O
E	O
IBM	O
Verilog	B-Language
PowerPC	O
470S	O
IBM	O
CoreConnect	B-Architecture
32-bit	O
PowerPC	O
v.2.05	O
Book	O
E	O
IBM	O
Verilog	B-Language
Microwatt	B-Device
IBM/OpenPOWER	O
Wishbone	B-Architecture
64-bit	O
PowerISA	O
3.0	O
proof	O
of	O
concept	O
Microwatt	B-Device
@	O
Github	O
VHDL	B-Language
Chiselwatt	O
IBM/OpenPOWER	O
Wishbone	B-Architecture
64-bit	O
PowerISA	O
3.0	O
Chiselwatt	O
@	O
Github	O
Chisel	O
Libre-SOC	B-General_Concept
Libre-SoC.org	O
Wishbone	B-Architecture
64-bit	O
PowerISA	O
3.0	O
.	O
</s>
<s>
CPU/GPU/VPU	O
implementation	O
and	O
custom	O
vector	O
instructions	O
Libre-SoC.org	O
python/nMigen	O
A2I	O
IBM/OpenPOWER	O
Custom	O
PBus	O
64-bit	O
PowerPC	O
2.6	O
Book	O
E	O
.	O
In	O
order	O
core	O
A2I	O
@	O
Github	O
VHDL	B-Language
A2O	O
IBM/OpenPOWER	O
Custom	O
PBus	O
64-bit	O
PowerPC	O
2.7	O
Book	O
E	O
.	O
Out	O
of	O
order	O
core	O
A2O	O
@	O
Github	O
Verilog	B-Language
Other	O
architectures	O
ARC	B-Application
ARC	B-Application
International	O
,	O
Synopsys	O
16/32/64	O
-bit	O
ISA	O
RISC	O
DesignWare	O
ARC	B-Application
Verilog	B-Language
ERIC5	O
Entner	O
Electronics	O
9-bit	O
RISC	O
,	O
very	O
small	O
size	O
,	O
C-programmable	O
ERIC5	O
VHDL	B-Language
H2	O
CPU	O
Richard	O
James	O
Howe	O
Custom	O
16-bit	O
Stack	O
Machine	O
,	O
designed	O
to	O
execute	O
Forth	O
directly	O
,	O
small	O
H2	O
CPU	O
VHDL	B-Language
Instant	O
SoC	O
FPGA	B-Architecture
Cores	O
Custom	O
32-bit	O
RISC-V	B-Device
M	O
Extension	O
,	O
SoC	O
defined	O
by	O
C++	O
Instant	O
SoC	O
VHDL	B-Language
JOP	B-Language
Martin	O
Schoeberl	O
SimpCon	O
/	O
Wishbone	B-Architecture
(	O
extension	O
)	O
Stack-oriented	O
,	O
hard	O
real-time	O
support	O
,	O
executing	O
Java	B-Language
bytecode	I-Language
directly	O
Jop	B-Language
VHDL	B-Language
LatticeMico8	B-Device
Lattice	O
Wishbone	B-Architecture
LatticeMico8	B-Device
Verilog	B-Language
LatticeMico32	B-Device
Lattice	O
Wishbone	B-Architecture
LatticeMico32	B-Device
Verilog	B-Language
LXP32	O
Alex	O
Kuznetsov	O
Wishbone	B-Architecture
32-bit	O
,	O
3-stage	O
pipeline	O
,	O
register	B-General_Concept
file	I-General_Concept
based	O
on	O
block	O
RAM	O
lxp32	O
VHDL	B-Language
MCL65	O
MicroCore	O
Labs	O
Ultra-small-footprint	O
microsequencer-based	O
6502	O
core	O
252	O
Spartan-7	O
LUTs	O
.	O
</s>
<s>
MCL65	O
Core	O
MRISC32-A1	O
Marcus	O
Geelnard	O
Wishbone	B-Architecture
,	O
B4/pipelined	O
32-bit	O
RISC/Vector	O
CPU	O
implementing	O
the	O
MRISC32	O
ISA	O
MRISC32	O
VHDL	B-Language
NEO430	O
Stephan	O
Nolting	O
Wishbone	B-Architecture
(	O
Avalon	O
,	O
AXI4-Lite	O
)	O
16-bit	O
MSP430	O
ISA-compatible	O
,	O
very	O
small	O
size	O
,	O
many	O
peripherals	O
,	O
highly	O
customizable	O
NEO430	O
VHDL	B-Language
Nios	B-Device
,	O
Nios	B-Device
II	I-Device
Altera	O
Avalon	O
Altera	O
Nios	B-Device
II	I-Device
Verilog	B-Language
OpenRISC	B-Device
OpenCores	O
Wishbone	B-Architecture
32-bit	O
;	O
done	O
in	O
ASIC	O
,	O
Actel	O
,	O
Altera	O
,	O
Xilinx	O
FPGA	B-Architecture
.	O
</s>
<s>
Verilog	B-Language
SpartanMC	O
TU	O
Darmstadt	O
/	O
TU	O
Dresden	O
Custom	O
(	O
AXI	B-Protocol
support	O
in	O
development	O
)	O
18-bit	O
ISA	O
(	O
GNU	O
Binutils	O
/	O
GCC	O
support	O
in	O
development	O
)	O
SpartanMC	O
Verilog	B-Language
SYNPIC12	O
Miguel	O
Angel	O
Ajo	O
Pelayo	O
PIC12F	O
compatible	O
,	O
program	O
synthesised	O
in	O
gates	O
nbee.es	O
VHDL	B-Language
xr16	O
Jan	O
Gray	O
XSOC	O
abstract	O
bus	O
16-bit	O
RISC	O
CPU	O
and	O
SoC	O
featured	O
in	O
Circuit	O
Cellar	O
Magazine	O
#116	O
-118	O
XSOC/xr16	O
Schematic	O
YASEP	O
Yann	O
Guidon	O
Direct	O
SRAM	O
16	O
or	O
32	O
bits	O
,	O
RTL	O
in	O
VHDL	B-Language
&	O
asm	O
in	O
JS	B-Language
,	O
microcontroller	O
subset	O
:	O
ready	O
yasep.org	O
(	O
Firefox	O
required	O
)	O
VHDL	B-Language
ZipCPU	O
Gisselquist	O
Technology	O
Wishbone	B-Architecture
,	O
B4/pipelined	O
32-bit	O
CPU	O
targeted	O
for	O
minimal	O
FPGA	B-Architecture
resource	O
usage	O
zipcpu.com	O
Verilog	B-Language
ZPU	O
Zylin	O
AS	O
Wishbone	B-Architecture
Stack	O
based	O
CPU	O
,	O
configurable	O
16/32	O
bit	O
datapath	O
,	O
eCos	B-Operating_System
support	O
Zylin	O
CPU	O
VHDLRISC5	O
Niklaus	O
Wirth	O
CustomRunning	O
a	O
complete	O
graphical	O
Oberon	O
System	O
including	O
an	O
editor	O
and	O
compiler	O
.	O
</s>
