<s>
LGA	B-Algorithm
2011	O
,	O
also	O
called	O
Socket	O
R	O
,	O
is	O
a	O
CPU	B-General_Concept
socket	I-General_Concept
by	O
Intel	O
released	O
on	O
November	O
14	O
,	O
2011	O
.	O
</s>
<s>
It	O
launched	O
along	O
with	O
LGA	B-Device
1356	I-Device
to	O
replace	O
its	O
predecessor	O
,	O
LGA	B-Device
1366	I-Device
(	O
Socket	B-Device
B	I-Device
)	O
and	O
LGA	B-Device
1567	I-Device
.	O
</s>
<s>
While	O
LGA	B-Device
1356	I-Device
was	O
designed	O
for	O
dual-processor	O
or	O
low-end	O
servers	O
,	O
LGA	B-Algorithm
2011	O
was	O
designed	O
for	O
high-end	O
desktops	O
and	O
high-performance	O
servers	O
.	O
</s>
<s>
The	O
LGA2011	O
socket	O
uses	O
QPI	B-Architecture
to	O
connect	O
the	O
CPU	O
to	O
additional	O
CPUs	O
.	O
</s>
<s>
DMI	B-Architecture
2.0	I-Architecture
is	O
used	O
to	O
connect	O
the	O
processor	O
to	O
the	O
PCH	B-Device
.	O
</s>
<s>
As	O
with	O
its	O
predecessor	O
LGA1366	B-Device
,	O
there	O
is	O
no	O
provisioning	O
for	O
integrated	O
graphics	O
.	O
</s>
<s>
This	O
socket	O
supports	O
four	O
DDR3	O
or	O
DDR4	O
SDRAM	O
memory	O
channels	O
with	O
up	O
to	O
three	O
unbuffered	O
or	O
registered	O
DIMMs	B-General_Concept
per	O
channel	O
,	O
as	O
well	O
as	O
up	O
to	O
40	O
PCI	O
Express	O
2.0	O
or	O
3.0	O
lanes	O
.	O
</s>
<s>
The	O
LGA2011	O
socket	O
is	O
used	O
by	O
Sandy	O
Bridge-E/EP	O
and	O
Ivy	O
Bridge-E/EP	O
processors	O
with	O
the	O
corresponding	O
X79	B-Device
(	O
E	O
enthusiast	O
class	O
)	O
and	O
C600-series	O
(	O
EP	O
Xeon	O
class	O
)	O
chipsets	O
.	O
</s>
<s>
It	O
and	O
LGA	B-Algorithm
1155	O
are	O
the	O
two	O
last	O
Intel	B-General_Concept
sockets	I-General_Concept
to	O
support	O
Windows	B-Application
XP	I-Application
and	O
Windows	B-Application
Server	I-Application
2003	I-Application
.	O
</s>
<s>
LGA	B-Algorithm
2011-1	O
(	O
Socket	O
R2	O
)	O
,	O
an	O
updated	O
generation	O
of	O
the	O
socket	O
and	O
the	O
successor	O
of	O
LGA	B-Algorithm
1567	O
,	O
is	O
used	O
for	O
Ivy	O
Bridge-EX	O
(	O
Xeon	O
E7	O
v2	O
)	O
,	O
Haswell-EX	O
(	O
Xeon	O
E7	O
v3	O
)	O
and	O
Broadwell-EX	O
(	O
Xeon	O
E7	O
v4	O
)	O
CPUs	O
,	O
which	O
were	O
released	O
in	O
February	O
2014	O
,	O
May	O
2015	O
and	O
July	O
2016	O
,	O
respectively	O
.	O
</s>
<s>
LGA	B-Algorithm
2011-v3	O
(	O
Socket	O
R3	O
,	O
also	O
referred	O
to	O
as	O
LGA	B-Algorithm
2011-3	O
)	O
is	O
another	O
updated	O
generation	O
of	O
the	O
socket	O
,	O
used	O
for	O
Haswell-E	O
and	O
Haswell-EP	O
CPUs	O
and	O
Broadwell-E	B-General_Concept
,	O
which	O
were	O
released	O
in	O
August	O
and	O
September	O
2014	O
,	O
respectively	O
.	O
</s>
<s>
In	O
the	O
server	O
market	O
,	O
it	O
was	O
succeeded	O
by	O
LGA	B-Device
3647	I-Device
,	O
when	O
in	O
high-end	O
desktop	O
and	O
workstation	O
markets	O
its	O
successor	O
is	O
LGA	B-Device
2066	I-Device
.	O
</s>
<s>
Intel	O
CPU	B-General_Concept
sockets	I-General_Concept
use	O
the	O
so-called	O
Independent	O
Loading	O
Mechanism	O
(	O
ILM	O
)	O
retention	O
device	O
to	O
apply	O
the	O
specific	O
amount	O
of	O
uniform	O
pressure	O
required	O
to	O
correctly	O
hold	O
the	O
CPU	O
against	O
the	O
socket	O
interface	O
.	O
</s>
<s>
These	O
protrusions	O
,	O
also	O
known	O
as	O
ILM	O
keying	O
,	O
have	O
the	O
purpose	O
of	O
preventing	O
installation	O
of	O
incompatible	O
CPUs	O
into	O
otherwise	O
physically	O
compatible	O
sockets	O
,	O
and	O
preventing	O
ILMs	O
to	O
be	O
mounted	O
with	O
a	O
180-degree	O
rotation	O
relative	O
to	O
the	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
CPUs	O
that	O
are	O
intended	O
to	O
be	O
mounted	O
into	O
LGA	B-Algorithm
2011-0	O
(	O
R	O
)	O
,	O
LGA	B-Algorithm
2011-1	O
(	O
R2	O
)	O
or	O
LGA	B-Algorithm
2011-v3	O
(	O
R3	O
)	O
sockets	O
are	O
all	O
mechanically	O
compatible	O
regarding	O
their	O
dimensions	O
and	O
ball	B-Algorithm
pattern	I-Algorithm
pitches	O
,	O
but	O
the	O
designations	O
of	O
contacts	O
are	O
different	O
between	O
generations	O
of	O
the	O
LGA2011	O
socket	O
and	O
CPUs	O
,	O
which	O
makes	O
them	O
electrically	O
and	O
logically	O
incompatible	O
.	O
</s>
<s>
LGA	B-Algorithm
2011-v3	O
socket	O
is	O
used	O
for	O
Haswell-E	O
and	O
Haswell-EP	O
CPUs	O
,	O
which	O
were	O
released	O
in	O
August	O
and	O
September	O
2014	O
,	O
respectively	O
.	O
</s>
<s>
Information	O
for	O
the	O
Intel	B-Device
X79	I-Device
(	O
for	O
desktop	O
)	O
and	O
C600	O
series	O
(	O
for	O
workstations	O
and	O
servers	O
,	O
codenamed	O
Romley	O
)	O
chipsets	O
is	O
in	O
the	O
table	O
below	O
.	O
</s>
<s>
The	O
X79	B-Device
appears	O
to	O
contain	O
the	O
same	O
silicon	O
as	O
the	O
C600	O
series	O
,	O
with	O
ECS	O
having	O
enabled	O
the	O
SAS	O
controller	O
for	O
one	O
of	O
their	O
boards	O
,	O
even	O
though	O
SAS	O
is	O
not	O
officially	O
supported	O
by	O
Intel	O
for	O
X79	B-Device
.	O
</s>
<s>
Desktop	O
processors	O
compatible	O
with	O
LGA2011	O
,	O
2011	O
–	O
3	O
socket	O
are	O
Sandy	B-Device
Bridge-E	I-Device
,	O
Ivy	B-Device
Bridge-E	I-Device
,	O
Haswell-E	O
and	O
Broadwell-E	B-General_Concept
.	O
</s>
<s>
Sandy	B-Device
Bridge-E	I-Device
and	O
Ivy	B-Device
Bridge-E	I-Device
processors	O
are	O
compatible	O
with	O
the	O
Intel	B-Device
X79	I-Device
chipset	O
.	O
</s>
<s>
Haswell-E	O
and	O
Broadwell-E	B-General_Concept
processors	O
are	O
compatible	O
with	O
the	O
Intel	B-Device
X99	I-Device
chipset	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Turbo	B-Device
Boost	I-Device
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
Hyper-threading	B-Operating_System
,	O
except	O
the	O
C1	O
stepping	O
models	O
,	O
which	O
lack	O
VT-d	O
.	O
</s>
<s>
Sandy	B-Device
Bridge-E	I-Device
,	O
Ivy	B-Device
Bridge-E	I-Device
and	O
Haswell-E	O
processors	O
are	O
not	O
bundled	O
with	O
standard	O
air-cooled	O
CPU	O
coolers	O
.	O
</s>
<s>
1	O
The	O
X79	B-Device
chipset	O
allows	O
for	O
increasing	O
the	O
base	O
clock	O
(	O
BCLK	O
)	O
,	O
Intel	O
calls	O
it	O
CPU	O
Strap	O
,	O
by	O
1.00	O
×	O
,	O
1.25	O
×	O
,	O
1.66	O
×	O
or	O
2.50	O
×	O
.	O
</s>
<s>
Server	O
processors	O
compatible	O
with	O
LGA2011	O
socket	O
are	O
Sandy	B-Device
Bridge-EP	I-Device
,	O
Ivy	B-Device
Bridge-E	I-Device
,	O
Haswell-E	O
and	O
Broadwell-E	B-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Not	O
all	O
support	O
Hyper-threading	B-Operating_System
and	O
Turbo	B-Device
Boost	I-Device
.	O
</s>
<s>
Server	O
processors	O
for	O
the	O
LGA	B-Algorithm
2011-v3	O
socket	O
are	O
listed	O
in	O
the	O
tables	O
below	O
.	O
</s>
<s>
These	O
processors	O
are	O
built	O
on	O
Broadwell-E	B-General_Concept
architecture	O
,	O
14nM	O
lithography	O
,	O
4-channel	O
DDR4	O
ECC	O
with	O
up	O
to	O
1.5TB	O
and	O
40-lanes	O
of	O
PCI	O
Express	O
3.0	O
.	O
</s>
<s>
E5-16xx	O
v4	O
do	O
not	O
have	O
QPI	B-Architecture
links	O
.	O
</s>
<s>
E5-26xx	O
v4	O
and	O
E5-46xx	O
4	O
processors	O
have	O
2	O
QPI	B-Architecture
links	O
.	O
</s>
