<s>
The	O
Socket	B-Device
G3	I-Device
Memory	I-Device
Extender	I-Device
(	O
G3MX	B-Device
)	O
was	O
a	O
planned	O
Advanced	O
Micro	O
Devices	O
 '	O
solution	O
to	O
the	O
problem	O
of	O
connecting	O
large	O
amounts	O
of	O
memory	O
to	O
a	O
single	O
microprocessor	O
.	O
</s>
<s>
The	O
G3MX	B-Device
was	O
expected	O
to	O
be	O
available	O
on	O
AMD	O
800S	O
series	O
chipset	O
for	O
server	O
market	O
starting	O
from	O
2009	O
,	O
but	O
was	O
officially	O
cancelled	O
together	O
with	O
the	O
cancellation	O
of	O
Socket	B-Device
G3	I-Device
in	O
early	O
2008	O
.	O
</s>
<s>
Electrical	O
limitations	O
preclude	O
connecting	O
more	O
than	O
2	O
unbuffered	O
DDR	O
SDRAM	O
DIMMs	B-General_Concept
or	O
4	O
buffered	O
DIMMs	B-General_Concept
to	O
a	O
single	O
shared	O
bus	O
.	O
</s>
<s>
Thus	O
,	O
it	O
is	O
impossible	O
to	O
connect	O
more	O
than	O
8	O
DIMMs	B-General_Concept
to	O
a	O
single	O
chip	O
.	O
</s>
<s>
The	O
obvious	O
solution	O
is	O
to	O
use	O
a	O
narrower	O
,	O
higher-speed	O
bus	O
to	O
interface	O
to	O
memory	O
,	O
and	O
to	O
implement	O
it	O
as	O
a	O
point-to-point	B-Architecture
link	I-Architecture
,	O
daisy-chaining	B-Application
additional	O
modules	O
.	O
</s>
<s>
However	O
,	O
the	O
high-speed	O
circuitry	O
increased	O
power	O
consumption	O
,	O
and	O
the	O
daisy-chaining	B-Application
caused	O
significantly	O
higher	O
memory	B-General_Concept
latency	I-General_Concept
.	O
</s>
<s>
Because	O
it	O
is	O
difficult	O
to	O
implement	O
high-speed	O
circuitry	O
on	O
the	O
same	O
semiconductor	B-Architecture
process	I-Architecture
,	O
costs	O
were	O
high	O
.	O
</s>
<s>
FB-DIMMs	B-General_Concept
add	O
a	O
separate	O
memory	O
controller	O
chip	O
to	O
each	O
memory	O
DIMM	B-General_Concept
.	O
</s>
<s>
AMD	O
's	O
answer	O
to	O
this	O
is	O
the	O
G3MX	B-Device
chip	O
.	O
</s>
<s>
This	O
is	O
very	O
similar	O
to	O
the	O
AMB	O
,	O
but	O
is	O
intended	O
to	O
be	O
placed	O
on	O
the	O
motherboard	B-Device
,	O
not	O
on	O
the	O
DIMM	B-General_Concept
.	O
</s>
<s>
It	O
can	O
connect	O
to	O
multiple	O
DIMMs	B-General_Concept
but	O
,	O
to	O
minimize	O
latency	O
,	O
is	O
not	O
designed	O
to	O
be	O
daisy-chained	O
.	O
</s>
<s>
The	O
G3MX	B-Device
has	O
an	O
asymmetrical	O
link	O
to	O
the	O
processor	O
,	O
to	O
match	O
typical	O
memory	O
usage	O
patterns	O
.	O
</s>
<s>
Thus	O
,	O
a	O
processor	O
can	O
easily	O
have	O
4	O
G3MX	B-Device
memory	O
interfaces	O
,	O
each	O
with	O
4	O
buffered	O
DIMMs	B-General_Concept
attached	O
,	O
allowing	O
up	O
to	O
16	O
DIMMs	B-General_Concept
to	O
feed	O
one	O
processor	O
.	O
</s>
