<s>
Skylake	B-Architecture
is	O
the	O
codename	B-Architecture
used	I-Architecture
by	I-Architecture
Intel	I-Architecture
for	O
a	O
processor	O
microarchitecture	B-General_Concept
that	O
was	O
launched	O
in	O
August	O
2015	O
succeeding	O
the	O
Broadwell	B-General_Concept
microarchitecture	B-General_Concept
.	O
</s>
<s>
Skylake	B-Architecture
is	O
a	O
microarchitecture	B-General_Concept
redesign	O
using	O
the	O
same	O
14	O
nm	O
manufacturing	B-Architecture
process	I-Architecture
technology	I-Architecture
as	O
its	O
predecessor	O
,	O
serving	O
as	O
a	O
tock	O
in	O
Intel	O
's	O
tick	B-Device
–	I-Device
tock	I-Device
manufacturing	O
and	O
design	O
model	O
.	O
</s>
<s>
According	O
to	O
Intel	O
,	O
the	O
redesign	O
brings	O
greater	O
CPU	O
and	O
GPU	B-Application
performance	O
and	O
reduced	O
power	O
consumption	O
.	O
</s>
<s>
Skylake	B-Architecture
CPUs	O
share	O
their	O
microarchitecture	B-General_Concept
with	O
Kaby	B-Device
Lake	I-Device
,	O
Coffee	B-Device
Lake	I-Device
,	O
Cannon	B-Device
Lake	I-Device
,	O
Whiskey	B-Device
Lake	I-Device
,	O
and	O
Comet	B-Device
Lake	I-Device
CPUs	O
.	O
</s>
<s>
Skylake	B-Architecture
is	O
the	O
last	O
Intel	O
platform	O
on	O
which	O
Windows	O
earlier	O
than	O
Windows	B-Operating_System
10	I-Operating_System
will	O
be	O
officially	O
supported	O
by	O
Microsoft	O
,	O
although	O
enthusiast-created	O
modifications	B-Device
exist	O
that	O
allow	O
Windows	B-Device
8.1	I-Device
and	O
earlier	O
to	O
continue	O
to	O
receive	O
Windows	O
Updates	O
on	O
later	O
platforms	O
.	O
</s>
<s>
Some	O
of	O
the	O
processors	O
based	O
on	O
the	O
Skylake	B-Architecture
microarchitecture	I-Architecture
are	O
marketed	O
as	O
6th-generation	O
Core	O
.	O
</s>
<s>
Intel	O
officially	O
declared	O
end	O
of	O
life	O
and	O
discontinued	O
Skylake	B-Architecture
LGA	B-Device
1151	I-Device
CPUs	O
on	O
March	O
4	O
,	O
2019	O
.	O
</s>
<s>
Skylake	B-Architecture
's	O
development	O
,	O
as	O
with	O
previous	O
processors	O
such	O
as	O
Banias	B-Architecture
,	O
Dothan	O
,	O
Conroe	O
,	O
Sandy	B-Device
Bridge	I-Device
,	O
and	O
Ivy	B-Device
Bridge	I-Device
,	O
was	O
primarily	O
undertaken	O
by	O
Intel	O
Israel	O
at	O
its	O
engineering	O
research	O
center	O
in	O
Haifa	B-Algorithm
,	I-Algorithm
Israel	I-Algorithm
.	O
</s>
<s>
A	O
major	O
priority	O
of	O
Skylake	B-Architecture
's	O
design	O
was	O
to	O
design	O
a	O
microarchitecture	B-General_Concept
for	O
envelopes	O
as	O
low	O
as	O
4.5W	O
to	O
embed	O
within	O
tablet	B-Device
computers	I-Device
and	O
notebooks	B-Device
in	O
addition	O
to	O
higher-power	O
desktop	B-Device
computers	I-Device
and	O
servers	B-Application
.	O
</s>
<s>
In	O
September	O
2014	O
,	O
Intel	O
announced	O
the	O
Skylake	B-Architecture
microarchitecture	I-Architecture
at	O
the	O
Intel	O
Developer	O
Forum	O
in	O
San	O
Francisco	O
,	O
and	O
that	O
volume	O
shipments	O
of	O
Skylake	B-Architecture
CPUs	O
were	O
scheduled	O
for	O
the	O
second	O
half	O
of	O
2015	O
.	O
</s>
<s>
The	O
Skylake	B-Architecture
development	O
platform	O
was	O
announced	O
to	O
be	O
available	O
in	O
Q1	O
2015	O
.	O
</s>
<s>
During	O
the	O
announcement	O
,	O
Intel	O
also	O
demonstrated	O
two	O
computers	O
with	O
desktop	O
and	O
mobile	O
Skylake	B-Architecture
prototypes	O
:	O
the	O
first	O
was	O
a	O
desktop	O
testbed	O
system	O
,	O
running	O
the	O
latest	O
version	O
of	O
3DMark	O
,	O
while	O
the	O
second	O
computer	O
was	O
a	O
fully	O
functional	O
laptop	B-Device
,	O
playing	O
4K	B-Architecture
video	I-Architecture
.	O
</s>
<s>
An	O
initial	O
batch	O
of	O
Skylake	B-Architecture
CPU	O
models	O
(	O
6600K	O
and	O
6700K	O
)	O
was	O
announced	O
for	O
immediate	O
availability	O
during	O
the	O
Gamescom	O
on	O
August	O
5	O
,	O
2015	O
,	O
unusually	O
soon	O
after	O
the	O
release	O
of	O
its	O
predecessor	O
,	O
Broadwell	B-General_Concept
,	O
which	O
had	O
suffered	O
from	O
launch	O
delays	O
.	O
</s>
<s>
Intel	O
acknowledged	O
in	O
2014	O
that	O
moving	O
from	O
22nm	O
(	O
Haswell	O
)	O
to	O
14nm	B-Algorithm
(	O
Broadwell	B-General_Concept
)	O
had	O
been	O
its	O
most	O
difficult	O
process	O
to	O
develop	O
yet	O
,	O
causing	O
Broadwell	B-General_Concept
's	O
planned	O
launch	O
to	O
slip	O
by	O
several	O
months	O
;	O
yet	O
,	O
the	O
14nm	B-Algorithm
production	O
was	O
back	O
on	O
track	O
and	O
in	O
full	O
production	O
as	O
of	O
Q3	O
2014	O
.	O
</s>
<s>
Industry	O
observers	O
had	O
initially	O
believed	O
that	O
the	O
issues	O
affecting	O
Broadwell	B-General_Concept
would	O
also	O
cause	O
Skylake	B-Architecture
to	O
slip	O
to	O
2016	O
,	O
but	O
Intel	O
was	O
able	O
to	O
bring	O
forward	O
Skylake	B-Architecture
's	O
release	O
and	O
shorten	O
Broadwell	B-General_Concept
's	O
release	O
cycle	O
instead	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
Broadwell	B-General_Concept
architecture	O
had	O
an	O
unusually	O
short	O
run	O
.	O
</s>
<s>
Officially	O
Intel	O
supported	O
overclocking	B-Application
of	O
only	O
the	O
K	O
and	O
X	O
versions	O
of	O
Skylake	B-Architecture
processors	O
.	O
</s>
<s>
However	O
,	O
it	O
was	O
later	O
discovered	O
that	O
other	O
non-K	O
chips	O
could	O
be	O
overclocked	O
by	O
modifying	O
the	O
base	O
clock	O
value	O
–	O
a	O
process	O
made	O
feasible	O
by	O
the	O
base	O
clock	O
applying	O
only	O
to	O
the	O
CPU	O
,	O
RAM	B-Architecture
,	O
and	O
integrated	O
graphics	O
on	O
Skylake	B-Architecture
.	O
</s>
<s>
When	O
overclocking	B-Application
unsupported	O
processors	O
using	O
these	O
UEFI	O
firmware	O
updates	O
,	O
several	O
issues	O
arise	O
:	O
</s>
<s>
These	O
issues	O
are	O
partly	O
caused	O
by	O
the	O
power	O
management	O
of	O
the	O
processor	O
needing	O
to	O
be	O
disabled	O
for	O
base	O
clock	O
overclocking	B-Application
to	O
work	O
.	O
</s>
<s>
On	O
February	O
9	O
,	O
2016	O
,	O
Intel	O
announced	O
that	O
it	O
would	O
no	O
longer	O
allow	O
such	O
overclocking	B-Application
of	O
non-K	O
processors	O
,	O
and	O
that	O
it	O
had	O
issued	O
a	O
CPU	O
microcode	B-Device
update	O
that	O
removes	O
the	O
function	O
.	O
</s>
<s>
In	O
April	O
2016	O
,	O
ASRock	O
started	O
selling	O
motherboards	O
that	O
allow	O
overclocking	B-Application
of	O
unsupported	O
CPUs	O
using	O
an	O
external	O
clock	O
generator	O
.	O
</s>
<s>
In	O
January	O
2016	O
,	O
Microsoft	O
announced	O
that	O
it	O
would	O
end	O
support	O
of	O
Windows	B-Device
7	I-Device
and	O
Windows	B-Device
8.1	I-Device
on	O
Skylake	B-Architecture
processors	O
effective	O
July	O
17	O
,	O
2017	O
;	O
after	O
this	O
date	O
,	O
only	O
the	O
most	O
critical	O
updates	O
for	O
the	O
two	O
operating	O
systems	O
would	O
be	O
released	O
for	O
Skylake	B-Architecture
users	O
if	O
they	O
have	O
been	O
judged	O
not	O
to	O
affect	O
the	O
reliability	O
of	O
the	O
OS	O
on	O
older	O
hardware	O
,	O
and	O
Windows	B-Operating_System
10	I-Operating_System
would	O
be	O
the	O
only	O
Microsoft	B-Application
Windows	I-Application
platform	O
officially	O
supported	O
on	O
Skylake	B-Architecture
,	O
as	O
well	O
as	O
all	O
future	O
Intel	B-Device
CPU	I-Device
microarchitectures	I-Device
beginning	O
with	O
Skylake	B-Architecture
's	O
successor	O
Kaby	B-Device
Lake	I-Device
.	O
</s>
<s>
Terry	O
Myerson	O
stated	O
that	O
Microsoft	O
had	O
to	O
make	O
a	O
large	O
investment	O
in	O
order	O
to	O
reliably	O
support	O
Skylake	B-Architecture
on	O
older	O
versions	O
of	O
Windows	O
,	O
and	O
that	O
future	O
generations	O
of	O
processors	O
would	O
require	O
further	O
investments	O
.	O
</s>
<s>
Microsoft	O
also	O
stated	O
that	O
due	O
to	O
the	O
age	O
of	O
the	O
platform	O
,	O
it	O
would	O
be	O
challenging	O
for	O
newer	O
hardware	O
,	O
firmware	O
,	O
and	O
device	O
driver	O
combinations	O
to	O
properly	O
run	O
under	O
Windows	B-Device
7	I-Device
.	O
</s>
<s>
On	O
March	O
18	O
,	O
2016	O
,	O
in	O
response	O
to	O
criticism	O
over	O
the	O
move	O
,	O
primarily	O
from	O
enterprise	O
customers	O
,	O
Microsoft	O
announced	O
revisions	O
to	O
the	O
support	O
policy	O
,	O
changing	O
the	O
cutoff	O
for	O
support	O
and	O
non-critical	O
updates	O
to	O
July	O
17	O
,	O
2018	O
and	O
stating	O
that	O
Skylake	B-Architecture
users	O
would	O
receive	O
all	O
critical	O
security	O
updates	O
for	O
Windows	B-Device
7	I-Device
and	O
8.1	B-Device
through	O
the	O
end	O
of	O
extended	O
support	O
.	O
</s>
<s>
In	O
August	O
2016	O
,	O
citing	O
"	O
a	O
strong	O
partnership	O
with	O
our	O
OEM	O
partners	O
and	O
Intel	O
"	O
,	O
Microsoft	O
stated	O
that	O
it	O
would	O
continue	O
to	O
fully	O
support	O
7	O
and	O
8.1	B-Device
on	O
Skylake	B-Architecture
through	O
the	O
end	O
of	O
their	O
respective	O
lifecycles	O
.	O
</s>
<s>
In	O
addition	O
,	O
an	O
enthusiast-created	O
modification	B-Device
was	O
released	O
that	O
disabled	O
the	O
Windows	O
Update	O
check	O
and	O
allowed	O
Windows	B-Device
8.1	I-Device
and	O
earlier	O
to	O
continue	O
to	O
be	O
updated	O
on	O
this	O
and	O
later	O
platforms	O
.	O
</s>
<s>
As	O
of	O
Linux	O
kernel	O
4.10	O
,	O
Skylake	B-Architecture
mobile	O
power	O
management	O
is	O
supported	O
with	O
most	O
Package	O
C	O
states	O
supported	O
seeing	O
some	O
use	O
.	O
</s>
<s>
Skylake	B-Architecture
is	O
fully	O
supported	O
on	O
OpenBSD	B-Operating_System
6.2	O
and	O
later	O
,	O
including	O
accelerated	B-General_Concept
graphics	O
.	O
</s>
<s>
For	O
Windows	B-Application
11	I-Application
,	O
only	O
the	O
high-end	O
Skylake-X	B-Architecture
processors	O
are	O
officially	O
listed	O
as	O
compatible	O
.	O
</s>
<s>
All	O
other	O
Skylake	B-Architecture
processors	O
are	O
not	O
officially	O
supported	O
due	O
to	O
security	O
concerns	O
.	O
</s>
<s>
However	O
,	O
it	O
is	O
still	O
possible	O
to	O
manually	O
upgrade	O
using	O
an	O
ISO	O
image	O
(	O
as	O
Windows	B-Operating_System
10	I-Operating_System
users	O
on	O
those	O
processors	O
wo	O
n't	O
be	O
offered	O
to	O
upgrade	O
to	O
Windows	B-Application
11	I-Application
via	O
Windows	O
Update	O
)	O
,	O
or	O
perform	O
a	O
clean	O
installation	O
as	O
long	O
as	O
the	O
system	O
has	O
Trusted	O
Platform	O
Module	O
(	O
TPM	O
)	O
2.0	O
enabled	O
,	O
but	O
the	O
user	O
must	O
accept	O
that	O
they	O
will	O
not	O
be	O
entitled	O
to	O
receive	O
updates	O
,	O
and	O
that	O
damage	O
caused	O
by	O
using	O
Windows	B-Application
11	I-Application
on	O
an	O
unsupported	O
configuration	O
are	O
not	O
covered	O
by	O
the	O
manufacturer	O
's	O
warranty	O
.	O
</s>
<s>
Like	O
its	O
predecessor	O
,	O
Broadwell	B-General_Concept
,	O
Skylake	B-Architecture
is	O
available	O
in	O
five	O
variants	O
,	O
identified	O
by	O
the	O
suffixes	O
S	O
(	O
SKL-S	B-Architecture
)	O
,	O
X	O
(	O
SKL-X	O
)	O
,	O
H	O
(	O
SKL-H	B-Architecture
)	O
,	O
U	O
(	O
SKL-U	B-Architecture
)	O
,	O
and	O
Y	O
(	O
SKL-Y	B-Architecture
)	O
.	O
</s>
<s>
SKL-S	B-Architecture
and	O
SKL-X	O
contain	O
overclockable	B-Application
K	O
and	O
X	O
variants	O
with	O
unlocked	O
multipliers	O
.	O
</s>
<s>
The	O
H	O
,	O
U	O
and	O
Y	O
variants	O
are	O
manufactured	O
in	O
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	O
)	O
packaging	O
,	O
while	O
the	O
S	O
and	O
X	O
variants	O
are	O
manufactured	O
in	O
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
packaging	O
using	O
a	O
new	O
socket	O
,	O
LGA	B-Device
1151	I-Device
(	O
LGA	B-Device
2066	I-Device
for	O
Skylake	B-Architecture
X	O
)	O
.	O
</s>
<s>
Skylake	B-Architecture
is	O
used	O
in	O
conjunction	O
with	O
Intel	O
100	O
Series	O
chipsets	O
,	O
also	O
known	O
as	O
Sunrise	O
Point	O
.	O
</s>
<s>
The	O
major	O
changes	O
between	O
the	O
Haswell	O
and	O
Skylake	B-Architecture
architectures	O
include	O
the	O
removal	O
of	O
the	O
fully	O
integrated	O
voltage	O
regulator	O
(	O
FIVR	O
)	O
introduced	O
with	O
Haswell	O
.	O
</s>
<s>
On	O
the	O
variants	O
that	O
will	O
use	O
a	O
discrete	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
,	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	O
)	O
2.0	O
is	O
replaced	O
by	O
DMI	O
3.0	O
,	O
which	O
allows	O
speeds	O
of	O
up	O
to	O
8GT/s	O
.	O
</s>
<s>
Skylake	B-Architecture
's	O
U	O
and	O
Y	O
variants	O
support	O
one	O
DIMM	B-General_Concept
slot	O
per	O
channel	O
,	O
while	O
H	O
and	O
S	O
variants	O
support	O
two	O
DIMM	B-General_Concept
slots	O
per	O
channel	O
.	O
</s>
<s>
Skylake	B-Architecture
's	O
launch	O
and	O
sales	O
lifespan	O
occur	O
at	O
the	O
same	O
time	O
as	O
the	O
ongoing	O
SDRAM	O
market	O
transition	O
,	O
with	O
DDR3	O
SDRAM	O
memory	O
gradually	O
being	O
replaced	O
by	O
DDR4	O
memory	O
.	O
</s>
<s>
Rather	O
than	O
working	O
exclusively	O
with	O
DDR4	O
,	O
the	O
Skylake	B-Architecture
microarchitecture	I-Architecture
remains	O
backward	B-General_Concept
compatible	I-General_Concept
by	O
interoperating	O
with	O
both	O
types	O
of	O
memory	O
.	O
</s>
<s>
Accompanying	O
the	O
microarchitecture	B-General_Concept
's	O
support	O
for	O
both	O
memory	O
standards	O
,	O
a	O
new	O
SO-DIMM	O
type	O
capable	O
of	O
carrying	O
either	O
DDR3	O
or	O
DDR4	O
memory	O
chips	O
,	O
called	O
UniDIMM	B-General_Concept
,	O
was	O
also	O
announced	O
.	O
</s>
<s>
Skylake	B-Architecture
's	O
few	O
P	O
variants	O
have	O
a	O
reduced	O
on-die	O
graphics	O
unit	O
(	O
12	O
execution	B-General_Concept
units	I-General_Concept
enabled	O
instead	O
of	O
24	O
execution	B-General_Concept
units	I-General_Concept
)	O
over	O
their	O
direct	O
counterparts	O
;	O
see	O
the	O
table	O
below	O
.	O
</s>
<s>
In	O
contrast	O
,	O
with	O
Ivy	B-Device
Bridge	I-Device
CPUs	O
the	O
P	O
suffix	O
was	O
used	O
for	O
CPUs	O
with	O
completely	O
disabled	O
on-die	O
video	O
chipset	O
.	O
</s>
<s>
Other	O
enhancements	O
include	O
Thunderbolt	B-Protocol
3.0	I-Protocol
,	O
SATA	B-Architecture
Express	I-Architecture
,	O
Iris	B-Application
Pro	I-Application
graphics	I-Application
with	O
Direct3D	O
feature	O
level12_1	O
with	O
up	O
to	O
128MB	O
of	O
L4	O
eDRAM	O
cache	B-General_Concept
on	O
certain	O
SKUs	O
.	O
</s>
<s>
The	O
Skylake	B-Architecture
line	O
of	O
processors	O
retires	O
VGA	B-Protocol
support	O
,	O
while	O
supporting	O
up	O
to	O
five	O
monitors	O
connected	O
via	O
HDMI	O
1.4	O
,	O
DisplayPort	O
1.2	O
or	O
Embedded	O
DisplayPort	O
(	O
eDP	O
)	O
interfaces	O
.	O
</s>
<s>
HDMI	O
2.0	O
(	O
4K	B-Architecture
@60Hz	O
)	O
is	O
only	O
supported	O
on	O
motherboards	O
equipped	O
with	O
Intel	O
's	O
Alpine	O
Ridge	O
Thunderbolt	B-Protocol
controller	O
.	O
</s>
<s>
The	O
Skylake	B-Architecture
instruction	O
set	O
changes	O
include	O
Intel	B-Device
MPX	I-Device
(	O
Memory	B-Device
Protection	I-Device
Extensions	I-Device
)	O
and	O
Intel	O
SGX	O
(	O
Software	O
Guard	O
Extensions	O
)	O
.	O
</s>
<s>
Future	O
Xeon	O
variants	O
will	O
also	O
have	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
3.2	O
(	O
AVX-512F	O
)	O
.	O
</s>
<s>
Skylake-based	O
laptops	B-Device
were	O
predicted	O
to	O
use	O
wireless	O
technology	O
called	O
Rezence	B-Algorithm
for	O
charging	O
,	O
and	O
other	O
wireless	O
technologies	O
for	O
communication	O
with	O
peripherals	O
.	O
</s>
<s>
Many	O
major	O
PC	O
vendors	O
agreed	O
to	O
use	O
this	O
technology	O
in	O
Skylake-based	O
laptops	B-Device
;	O
however	O
,	O
no	O
laptops	B-Device
were	O
released	O
with	O
the	O
technology	O
as	O
of	O
2019	O
.	O
</s>
<s>
The	O
integrated	O
GPU	B-Application
of	O
Skylake	B-Architecture
's	O
S	O
variant	O
supports	O
on	O
Windows	O
DirectX12	O
Feature	O
Level	O
12_1	O
,	O
OpenGL4.6	O
with	O
latest	O
Windows	B-Operating_System
10	I-Operating_System
driver	O
update	O
(	O
OpenGL	B-Application
4.5	O
on	O
Linux	O
)	O
and	O
OpenCL3.0	O
standards	O
.	O
</s>
<s>
The	O
Quick	B-Algorithm
Sync	I-Algorithm
video	I-Algorithm
engine	O
now	O
includes	O
support	O
for	O
VP9	B-Algorithm
(	O
GPU	B-Application
accelerated	B-General_Concept
decode	O
only	O
)	O
,	O
VP8	B-Algorithm
and	O
HEVC	B-Algorithm
(	O
hardware	B-General_Concept
accelerated	I-General_Concept
8-bit	O
encode/decode	O
and	O
GPU	B-Application
accelerated	B-General_Concept
10-bit	O
decode	O
)	O
,	O
and	O
supports	O
for	O
resolutions	O
up	O
to	O
40962048	O
.	O
</s>
<s>
Intel	O
also	O
released	O
unlocked	O
(	O
capable	O
of	O
overclocking	B-Application
)	O
mobile	O
Skylake	B-Architecture
CPUs	O
.	O
</s>
<s>
Unlike	O
previous	O
generations	O
,	O
Skylake-based	O
Xeon	O
E3	O
no	O
longer	O
works	O
with	O
a	O
desktop	O
chipset	O
that	O
supports	O
the	O
same	O
socket	O
,	O
and	O
requires	O
either	O
the	O
C232	O
or	O
the	O
C236	O
chipset	O
to	O
operate	O
.	O
</s>
<s>
Short	O
loops	O
with	O
a	O
specific	O
combination	O
of	O
instruction	O
use	O
may	O
cause	O
unpredictable	O
system	O
behavior	O
on	O
CPUs	O
with	O
hyperthreading	B-Operating_System
.	O
</s>
<s>
A	O
microcode	B-Device
update	O
was	O
issued	O
to	O
fix	O
the	O
issue	O
.	O
</s>
<s>
Skylake	B-Architecture
is	O
vulnerable	O
to	O
Spectre	B-Error_Name
attacks	I-Error_Name
.	O
</s>
<s>
The	O
latency	O
for	O
the	O
spinlock	B-Operating_System
instruction	O
has	O
been	O
increased	O
dramatically	O
(	O
from	O
the	O
usual	O
10	O
cycles	O
to	O
141	O
cycles	O
in	O
Skylake	B-Architecture
)	O
,	O
which	O
can	O
cause	O
performance	O
issues	O
with	O
older	O
programs	O
or	O
libraries	O
using	O
pause	O
instructions	O
.	O
</s>
<s>
Improved	O
front-end	O
,	O
deeper	O
out-of-order	O
buffers	O
,	O
improved	O
execution	B-General_Concept
units	I-General_Concept
,	O
more	O
execution	B-General_Concept
units	I-General_Concept
(	O
third	O
vector	O
integer	O
ALU(VALU )	O
)	O
for	O
five	O
ALUs	O
in	O
total	O
,	O
more	O
load/store	O
bandwidth	B-Algorithm
,	O
improved	O
hyper-threading	B-Operating_System
(	O
wider	O
retirement	O
)	O
,	O
speedup	O
of	O
AES-GCM	O
and	O
AES-CBC	O
by	O
17%	O
and	O
33%	O
accordingly	O
.	O
</s>
<s>
L1	O
cache	B-General_Concept
size	O
unchanged	O
at	O
32	O
KB	O
instruction	O
and	O
32	O
KB	O
data	B-General_Concept
cache	I-General_Concept
per	O
core	O
.	O
</s>
<s>
Enhancements	O
of	O
Intel	O
Processor	O
Trace	O
:	O
fine	O
grained	O
timing	O
through	O
CYC	O
packets	O
(	O
cycle-accurate	O
mode	O
)	O
and	O
support	O
for	O
IP	O
(	O
Instruction	B-General_Concept
Pointer	I-General_Concept
)	O
address	O
filtering	O
.	O
</s>
<s>
Full	O
fixed	O
function	O
HEVC	B-Algorithm
Main/8bit	O
encoding/decoding	O
acceleration	O
.	O
</s>
<s>
Hybrid/Partial	O
HEVC	B-Algorithm
Main10/10bit	O
decoding	O
acceleration	O
.	O
</s>
<s>
Partial	O
VP9	B-Algorithm
encoding/decoding	O
acceleration	O
.	O
</s>
<s>
Support	O
for	O
both	O
DDR3L	O
SDRAM	O
and	O
DDR4	O
SDRAM	O
in	O
mainstream	O
variants	O
,	O
using	O
custom	O
UniDIMM	B-General_Concept
SO-DIMM	O
form	O
factor	O
with	O
up	O
to	O
64GB	O
of	O
RAM	B-Architecture
on	O
LGA	O
1151	O
variants	O
.	O
</s>
<s>
Skylake	B-Architecture
processors	O
are	O
produced	O
in	O
five	O
main	O
families	O
:	O
Y	O
,	O
U	O
,	O
H	O
,	O
S	O
,	O
and	O
X	O
.	O
</s>
<s>
Common	O
features	O
of	O
the	O
mainstream	O
desktop	O
Skylake	B-Architecture
CPUs	O
:	O
</s>
<s>
Common	O
features	O
of	O
the	O
high	O
performance	O
Skylake-X	B-Architecture
CPUs	O
:	O
</s>
<s>
Xeon	O
W-3175X	O
was	O
the	O
only	O
Xeon	O
with	O
a	O
multiplier	O
unlocked	O
for	O
overclocking	B-Application
until	O
the	O
introduction	O
of	O
Sapphire	O
Rapids-WS	O
Xeon	O
CPUs	O
in	O
2023	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
AVX2	O
,	O
AVX-512	B-General_Concept
,	O
FMA3	B-General_Concept
,	O
MPX	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Turbo	B-Device
Boost	I-Device
(	O
excluding	O
W-2102	O
and	O
W-2104	O
)	O
,	O
Hyper-threading	B-Operating_System
(	O
excluding	O
W-2102	O
and	O
W-2104	O
)	O
,	O
AES-NI	B-Algorithm
,	O
Intel	B-Operating_System
TSX-NI	I-Operating_System
,	O
Smart	O
Cache	B-General_Concept
.	O
</s>
<s>
Supports	O
up	O
to	O
8	O
DIMMs	B-General_Concept
of	O
DDR4	O
memory	O
,	O
maximum	O
512	O
GB	O
.	O
</s>
<s>
memory	O
bandwidth	B-Algorithm
of	O
34.1	O
GB/s	O
dual	O
channel	O
memory	O
.	O
</s>
<s>
Unlike	O
its	O
predecessor	O
,	O
the	O
Skylake	B-Architecture
Xeon	O
CPUs	O
require	O
C230	O
series	O
(	O
C232/C236	O
)	O
or	O
C240	O
series	O
(	O
C242/C246	O
)	O
chipset	O
to	O
operate	O
,	O
with	O
integrated	O
graphics	O
working	O
only	O
with	O
C236	O
and	O
C246	O
chipsets	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
12	O
DIMMs	B-General_Concept
of	O
DDR4	O
memory	O
per	O
CPU	O
socket	O
.	O
</s>
<s>
Xeon	O
Platinum	O
,	O
Gold	O
61XX	O
,	O
and	O
Gold	O
5122	O
have	O
two	O
AVX-512	B-General_Concept
FMA	O
units	O
per	O
core	O
.	O
</s>
<s>
Xeon	O
Gold	O
51XX	O
(	O
except	O
5122	O
)	O
,	O
Silver	O
,	O
and	O
Bronze	O
have	O
a	O
single	O
AVX-512	B-General_Concept
FMA	O
unit	O
per	O
core	O
.	O
</s>
<s>
Xeon	O
Bronze	O
31XX	O
has	O
no	O
HT	O
or	O
Turbo	B-Device
Boost	I-Device
support	O
.	O
</s>
<s>
Xeon	O
Bronze	O
31XX	O
supports	O
DDR4-2133MHz	O
RAM	B-Architecture
.	O
</s>
<s>
Xeon	O
Silver	O
41XX	O
supports	O
DDR4-2400MHz	O
RAM	B-Architecture
.	O
</s>
<s>
Xeon	O
Gold	O
51XX	O
support	O
DDR4-2400MHz	O
RAM	B-Architecture
(	O
except	O
5122	O
)	O
.	O
</s>
<s>
Xeon	O
Gold	O
5122	O
and	O
61XX	O
support	O
DDR4-2666MHz	O
RAM	B-Architecture
.	O
</s>
<s>
Xeon	O
Platinum	O
supports	O
DDR4-2666MHz	O
RAM	B-Architecture
.	O
</s>
