<s>
Single	B-General_Concept
instruction	I-General_Concept
,	I-General_Concept
multiple	I-General_Concept
threads	I-General_Concept
(	O
SIMT	O
)	O
is	O
an	O
execution	O
model	O
used	O
in	O
parallel	B-Operating_System
computing	I-Operating_System
where	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
is	O
combined	O
with	O
multithreading	B-General_Concept
.	O
</s>
<s>
It	O
is	O
different	O
from	O
SPMD	B-Operating_System
in	O
that	O
all	O
instructions	O
in	O
all	O
"	O
threads	O
"	O
are	O
executed	O
in	O
lock-step	O
.	O
</s>
<s>
The	O
SIMT	O
execution	O
model	O
has	O
been	O
implemented	O
on	O
several	O
GPUs	B-Architecture
and	O
is	O
relevant	O
for	O
general-purpose	B-Architecture
computing	I-Architecture
on	I-Architecture
graphics	I-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPGPU	B-Architecture
)	O
,	O
e.g.	O
</s>
<s>
some	O
supercomputers	B-Architecture
combine	O
CPUs	O
with	O
GPUs	B-Architecture
.	O
</s>
<s>
This	O
is	O
achieved	O
by	O
each	O
processor	O
having	O
multiple	O
"	O
threads	O
"	O
(	O
or	O
"	O
work-items	O
"	O
or	O
"	O
Sequence	O
of	O
SIMD	B-General_Concept
Lane	I-General_Concept
operations	O
"	O
)	O
,	O
which	O
execute	O
in	O
lock-step	O
,	O
and	O
are	O
analogous	O
to	O
SIMD	B-General_Concept
lanes	I-General_Concept
.	O
</s>
<s>
The	O
simplest	O
way	O
to	O
understand	O
SIMT	O
is	O
to	O
imagine	O
a	O
multi-core	B-Architecture
system	O
,	O
where	O
each	O
core	O
has	O
its	O
own	O
register	O
file	O
,	O
its	O
own	O
ALUs	B-General_Concept
(	O
both	O
SIMD	B-Device
and	O
Scalar	O
)	O
and	O
its	O
own	O
data	O
cache	O
,	O
but	O
that	O
unlike	O
a	O
standard	O
multi-core	B-Architecture
system	O
which	O
has	O
multiple	O
independent	O
instruction	O
caches	O
and	O
decoders	O
,	O
as	O
well	O
as	O
multiple	O
independent	O
Program	O
Counter	O
registers	O
,	O
the	O
instructions	O
are	O
synchronously	O
broadcast	O
to	O
all	O
SIMT	O
cores	O
from	O
a	O
single	O
unit	O
with	O
a	O
single	O
instruction	O
cache	O
and	O
a	O
single	O
instruction	O
decoder	O
which	O
reads	O
instructions	O
using	O
a	O
single	O
Program	O
Counter	O
.	O
</s>
<s>
The	O
key	O
difference	O
between	O
SIMT	O
and	O
SIMD	B-General_Concept
lanes	I-General_Concept
is	O
that	O
each	O
of	O
the	O
SIMT	O
cores	O
may	O
have	O
a	O
completely	O
different	O
Stack	O
Pointer	O
(	O
and	O
thus	O
perform	O
computations	O
on	O
completely	O
different	O
data	O
sets	O
)	O
,	O
whereas	O
SIMD	B-General_Concept
lanes	I-General_Concept
are	O
simply	O
part	O
of	O
an	O
ALU	O
that	O
knows	O
nothing	O
about	O
memory	O
per	O
se	O
.	O
</s>
<s>
SIMT	O
was	O
introduced	O
by	O
Nvidia	O
in	O
the	O
Tesla	B-Operating_System
GPU	I-Operating_System
microarchitecture	I-Operating_System
with	O
the	O
G80	O
chip	O
.	O
</s>
<s>
ATI	O
Technologies	O
,	O
now	O
AMD	O
,	O
released	O
a	O
competing	O
product	O
slightly	O
later	O
on	O
May	O
14	O
,	O
2007	O
,	O
the	O
TeraScale	O
1-based	O
"	O
R600	O
"	O
GPU	B-Architecture
chip	O
.	O
</s>
<s>
As	O
access	O
time	O
of	O
all	O
the	O
widespread	O
RAM	B-Architecture
types	O
(	O
e.g.	O
</s>
<s>
DDR	O
SDRAM	O
,	O
GDDR	B-Device
SDRAM	I-Device
,	O
XDR	O
DRAM	O
,	O
etc	O
.	O
)	O
</s>
<s>
Strictly	O
,	O
the	O
latency-hiding	O
is	O
a	O
feature	O
of	O
the	O
zero-overhead	O
scheduling	O
implemented	O
by	O
modern	O
GPUs	B-Architecture
.	O
</s>
<s>
SIMT	O
is	O
intended	O
to	O
limit	O
instruction	B-General_Concept
fetching	I-General_Concept
overhead	O
,	O
i.e.	O
</s>
<s>
the	O
latency	O
that	O
comes	O
with	O
memory	O
access	O
,	O
and	O
is	O
used	O
in	O
modern	O
GPUs	B-Architecture
(	O
such	O
as	O
those	O
of	O
Nvidia	O
and	O
AMD	O
)	O
in	O
combination	O
with	O
'	O
latency	O
hiding	O
 '	O
to	O
enable	O
high-performance	O
execution	O
despite	O
considerable	O
latency	O
in	O
memory-access	O
operations	O
.	O
</s>
<s>
This	O
strategy	O
is	O
comparable	O
to	O
multithreading	B-General_Concept
in	I-General_Concept
CPUs	I-General_Concept
(	O
not	O
to	O
be	O
confused	O
with	O
multi-core	B-Architecture
)	O
.	O
</s>
<s>
As	O
with	O
SIMD	B-Device
,	O
another	O
major	O
benefit	O
is	O
the	O
sharing	O
of	O
the	O
control	O
logic	O
by	O
many	O
data	O
lanes	O
,	O
leading	O
to	O
an	O
increase	O
in	O
computational	O
density	O
.	O
</s>
<s>
The	O
masking	O
strategy	O
is	O
what	O
distinguishes	O
SIMT	O
from	O
ordinary	O
SIMD	B-Device
,	O
and	O
has	O
the	O
benefit	O
of	O
inexpensive	O
synchronization	O
between	O
the	O
threads	O
of	O
a	O
processor	O
.	O
</s>
