<s>
The	O
Single-Chip	B-General_Concept
Cloud	I-General_Concept
Computer	I-General_Concept
(	O
SCC	O
)	O
is	O
a	O
computer	O
processor	O
(	O
CPU	B-General_Concept
)	O
created	O
by	O
Intel	O
Corporation	O
in	O
2009	O
that	O
has	O
48	O
distinct	O
physical	O
cores	O
that	O
communicate	O
through	O
architecture	O
similar	O
to	O
that	O
of	O
a	O
cloud	B-Architecture
computer	I-Architecture
data	O
center	O
.	O
</s>
<s>
The	O
SCC	O
was	O
a	O
product	O
of	O
a	O
project	O
started	O
by	O
Intel	O
to	O
research	O
multi-core	B-Architecture
processors	I-Architecture
and	O
parallel	B-Operating_System
processing	I-Operating_System
(	O
doing	O
multiple	O
calculations	O
at	O
once	O
)	O
.	O
</s>
<s>
Additionally	O
Intel	O
wanted	O
to	O
experiment	O
with	O
incorporating	O
the	O
designs	O
and	O
architecture	O
of	O
huge	O
cloud	B-Architecture
computer	I-Architecture
data	O
centers	O
(	O
Cloud	B-Architecture
computing	I-Architecture
)	O
into	O
a	O
single	O
processing	O
chip	O
.	O
</s>
<s>
They	O
took	O
the	O
aspect	O
of	O
cloud	B-Architecture
computing	I-Architecture
in	O
which	O
there	O
are	O
many	O
remote	O
servers	O
that	O
communicate	O
with	O
each	O
other	O
and	O
applied	O
it	O
to	O
a	O
microprocessor	O
.	O
</s>
<s>
The	O
name	O
"	O
Single-chip	B-General_Concept
Cloud	I-General_Concept
Computer	I-General_Concept
"	O
originated	O
from	O
this	O
concept	O
.	O
</s>
<s>
It	O
currently	O
can	O
run	O
the	B-Operating_System
GNU	I-Operating_System
operating	I-Operating_System
system	I-Operating_System
on	O
the	O
chip	O
,	O
but	O
cannot	O
boot	O
Windows	O
.	O
</s>
<s>
Some	O
applications	O
of	O
the	O
SCC	O
are	O
web	B-Application
servers	I-Application
,	O
data	O
informatics	O
,	O
bioinformatics	O
,	O
and	O
financial	O
analytics	O
.	O
</s>
<s>
Each	O
tile	O
contained	O
two	O
cores	O
and	O
a	O
16KB	O
(	O
8	O
per	O
core	O
)	O
message	B-Architecture
passing	I-Architecture
buffer	O
(	O
MPB	O
)	O
shared	O
by	O
the	O
two	O
cores	O
,	O
essentially	O
a	O
router	O
.	O
</s>
<s>
The	O
SCC	O
contains	O
1.3	O
billion	O
45	O
nanometers	O
(	O
nm	O
)	O
long	O
transistors	B-Application
that	O
can	O
amplify	O
signals	O
or	O
act	O
as	O
a	O
switch	O
and	O
turn	O
core	O
pairs	O
on	O
and	O
off	O
.	O
</s>
<s>
These	O
transistors	B-Application
use	O
anywhere	O
from	O
25	O
to	O
125	O
watts	O
of	O
power	O
depending	O
on	O
the	O
processing	O
demand	O
.	O
</s>
<s>
Four	O
DDR3	O
memory	B-General_Concept
controllers	I-General_Concept
are	O
on	O
each	O
chip	O
,	O
connected	O
to	O
the	O
2D-mesh	O
as	O
well	O
.	O
</s>
<s>
These	O
controllers	O
are	O
capable	O
of	O
addressing	O
64GB	O
of	O
random-access	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
These	O
controllers	O
also	O
work	O
with	O
the	O
transistors	B-Application
to	O
control	O
when	O
certain	O
tiles	O
are	O
turned	O
on	O
and	O
off	O
to	O
save	O
power	O
when	O
not	O
in	O
use	O
.	O
</s>
<s>
When	O
proper	O
coding	O
is	O
implemented	O
all	O
of	O
these	O
pieces	O
are	O
put	O
together	O
you	O
get	O
a	O
functional	O
processor	O
that	O
is	O
fast	O
,	O
powerful	O
,	O
and	O
energy	O
efficient	O
with	O
a	O
framework	O
resembling	O
a	O
network	O
of	O
cloud	B-Architecture
computers	I-Architecture
.	O
</s>
<s>
The	O
SCC	O
comes	O
with	O
RCCE	O
,	O
a	O
simple	O
message	B-Application
passing	I-Application
interface	I-Application
provided	O
by	O
Intel	O
that	O
supports	O
basic	O
message	O
buffering	O
operations	O
.	O
</s>
<s>
In	O
processor	O
mode	O
cores	O
are	O
on	O
and	O
executing	O
code	O
from	O
the	O
system	O
memory	O
and	O
programmed	O
I/O	B-General_Concept
(	O
inputs	B-General_Concept
and	I-General_Concept
outputs	I-General_Concept
)	O
through	O
the	O
system	O
which	O
is	O
connected	O
to	O
the	O
system	O
board	O
FPGA	B-Architecture
.	O
</s>
<s>
Loading	O
memory	O
and	O
configuring	O
the	O
processor	O
for	O
bootstrapping	B-Application
(	O
sustaining	O
after	O
the	O
initial	O
load	O
)	O
is	O
currently	O
done	O
by	O
software	O
running	O
on	O
the	O
SCC	O
's	O
management	O
console	O
that	O
's	O
embedded	O
in	O
the	O
chip	O
.	O
</s>
<s>
Only	O
the	O
routers	O
,	O
transistors	B-Application
and	O
RAM	B-Architecture
controllers	O
are	O
on	O
and	O
they	O
are	O
sending	O
and	O
receiving	O
large	O
packets	B-Protocol
of	O
data	O
.	O
</s>
<s>
Additionally	O
there	O
is	O
no	O
memory	B-General_Concept
map	I-General_Concept
.	O
</s>
<s>
Intel	O
plans	O
to	O
share	O
this	O
technology	O
with	O
other	O
companies	O
such	O
as	O
HP	O
,	O
Yahoo	B-Application
,	O
and	O
Microsoft	O
to	O
have	O
multiple	O
companies	O
researching	O
the	O
SCC	O
to	O
more	O
efficiently	O
and	O
quickly	O
advance	O
the	O
technology	O
.	O
</s>
<s>
They	O
hope	O
to	O
improve	O
the	O
parallel	B-Operating_System
programming	I-Operating_System
productivity	O
and	O
power	O
management	O
to	O
take	O
advantage	O
of	O
the	O
chip	O
's	O
architecture	O
and	O
large	O
number	O
of	O
cores	O
.	O
</s>
