<s>
Simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
is	O
a	O
technique	O
for	O
improving	O
the	O
overall	O
efficiency	O
of	O
superscalar	B-General_Concept
CPUs	B-General_Concept
with	O
hardware	B-General_Concept
multithreading	I-General_Concept
.	O
</s>
<s>
SMT	O
permits	O
multiple	O
independent	O
threads	B-Operating_System
of	O
execution	O
to	O
better	O
use	O
the	O
resources	O
provided	O
by	O
modern	O
processor	B-General_Concept
architectures	I-General_Concept
.	O
</s>
<s>
The	O
term	O
multithreading	B-Operating_System
is	O
ambiguous	O
,	O
because	O
not	O
only	O
can	O
multiple	O
threads	B-Operating_System
be	O
executed	O
simultaneously	O
on	O
one	O
CPU	B-Architecture
core	I-Architecture
,	O
but	O
also	O
multiple	O
tasks	O
(	O
with	O
different	O
page	B-General_Concept
tables	I-General_Concept
,	O
different	O
task	B-Device
state	I-Device
segments	I-Device
,	O
different	O
protection	B-Operating_System
rings	I-Operating_System
,	O
different	O
I/O	O
permissions	O
,	O
etc	O
.	O
)	O
.	O
</s>
<s>
Multithreading	B-Operating_System
is	O
similar	O
in	O
concept	O
to	O
preemptive	O
multitasking	O
but	O
is	O
implemented	O
at	O
the	O
thread	B-Operating_System
level	O
of	O
execution	O
in	O
modern	O
superscalar	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
Simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
is	O
one	O
of	O
the	O
two	O
main	O
implementations	O
of	O
multithreading	B-Operating_System
,	O
the	O
other	O
form	O
being	O
temporal	B-Operating_System
multithreading	I-Operating_System
(	O
also	O
known	O
as	O
super-threading	B-Operating_System
)	O
.	O
</s>
<s>
In	O
temporal	B-Operating_System
multithreading	I-Operating_System
,	O
only	O
one	O
thread	B-Operating_System
of	O
instructions	O
can	O
execute	O
in	O
any	O
given	O
pipeline	O
stage	O
at	O
a	O
time	O
.	O
</s>
<s>
In	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
instructions	O
from	O
more	O
than	O
one	O
thread	B-Operating_System
can	O
be	O
executed	O
in	O
any	O
given	O
pipeline	O
stage	O
at	O
a	O
time	O
.	O
</s>
<s>
This	O
is	O
done	O
without	O
great	O
changes	O
to	O
the	O
basic	O
processor	O
architecture	O
:	O
the	O
main	O
additions	O
needed	O
are	O
the	O
ability	O
to	O
fetch	O
instructions	O
from	O
multiple	O
threads	B-Operating_System
in	O
a	O
cycle	O
,	O
and	O
a	O
larger	O
register	O
file	O
to	O
hold	O
data	O
from	O
multiple	O
threads	B-Operating_System
.	O
</s>
<s>
The	O
number	O
of	O
concurrent	O
threads	B-Operating_System
is	O
decided	O
by	O
the	O
chip	O
designers	O
.	O
</s>
<s>
Two	O
concurrent	O
threads	B-Operating_System
per	O
CPU	B-Architecture
core	I-Architecture
are	O
common	O
,	O
but	O
some	O
processors	O
support	O
up	O
to	O
eight	O
concurrent	O
threads	B-Operating_System
per	O
core	O
.	O
</s>
<s>
Because	O
it	O
inevitably	O
increases	O
conflict	O
on	O
shared	B-General_Concept
resources	I-General_Concept
,	O
measuring	O
or	O
agreeing	O
on	O
its	O
effectiveness	O
can	O
be	O
difficult	O
.	O
</s>
<s>
However	O
,	O
measured	O
energy	O
efficiency	O
of	O
SMT	O
with	O
parallel	O
native	O
and	O
managed	O
workloads	O
on	O
historical	O
130nm	O
to	O
32nm	O
Intel	O
SMT	O
(	O
hyper-threading	B-Operating_System
)	O
implementations	O
found	O
that	O
in	O
45nm	O
and	O
32nm	O
implementations	O
,	O
SMT	O
is	O
extremely	O
energy	O
efficient	O
,	O
even	O
with	O
in-order	O
Atom	B-Device
processors	I-Device
.	O
</s>
<s>
Some	O
researchers	O
have	O
shown	O
that	O
the	O
extra	O
threads	B-Operating_System
can	O
be	O
used	O
proactively	O
to	O
seed	O
a	O
shared	B-General_Concept
resource	I-General_Concept
like	O
a	O
cache	O
,	O
to	O
improve	O
the	O
performance	O
of	O
another	O
single	B-Operating_System
thread	I-Operating_System
,	O
and	O
claim	O
this	O
shows	O
that	O
SMT	O
does	O
not	O
only	O
increase	O
efficiency	O
.	O
</s>
<s>
However	O
,	O
in	O
most	O
current	O
cases	O
,	O
SMT	O
is	O
about	O
hiding	O
memory	B-General_Concept
latency	I-General_Concept
,	O
increasing	O
efficiency	O
,	O
and	O
increasing	O
throughput	O
of	O
computations	O
per	O
amount	O
of	O
hardware	O
used	O
.	O
</s>
<s>
In	O
processor	B-General_Concept
design	I-General_Concept
,	O
there	O
are	O
two	O
ways	O
to	O
increase	O
on-chip	O
parallelism	O
with	O
fewer	O
resource	O
requirements	O
:	O
one	O
is	O
superscalar	B-General_Concept
technique	O
which	O
tries	O
to	O
exploit	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
(	O
ILP	O
)	O
;	O
the	O
other	O
is	O
multithreading	B-Operating_System
approach	O
exploiting	O
thread-level	B-Operating_System
parallelism	I-Operating_System
(	O
TLP	O
)	O
.	O
</s>
<s>
Superscalar	B-General_Concept
means	O
executing	O
multiple	O
instructions	O
at	O
the	O
same	O
time	O
while	O
thread-level	B-Operating_System
parallelism	I-Operating_System
(	O
TLP	O
)	O
executes	O
instructions	O
from	O
multiple	O
threads	B-Operating_System
within	O
one	O
processor	O
chip	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
There	O
are	O
many	O
ways	O
to	O
support	O
more	O
than	O
one	O
thread	B-Operating_System
within	O
a	O
chip	O
,	O
namely	O
:	O
</s>
<s>
Interleaved	O
multithreading	B-Operating_System
:	O
Interleaved	O
issue	O
of	O
multiple	O
instructions	O
from	O
different	O
threads	B-Operating_System
,	O
also	O
referred	O
to	O
as	O
temporal	B-Operating_System
multithreading	I-Operating_System
.	O
</s>
<s>
It	O
can	O
be	O
further	O
divided	O
into	O
fine-grained	O
multithreading	B-Operating_System
or	O
coarse-grained	O
multithreading	B-Operating_System
depending	O
on	O
the	O
frequency	O
of	O
interleaved	O
issues	O
.	O
</s>
<s>
Fine-grained	O
multithreading	B-Operating_System
—	O
such	O
as	O
in	O
a	O
barrel	B-Operating_System
processor	I-Operating_System
—	O
issues	O
instructions	O
for	O
different	O
threads	B-Operating_System
after	O
every	O
cycle	O
,	O
while	O
coarse-grained	O
multithreading	B-Operating_System
only	O
switches	O
to	O
issue	O
instructions	O
from	O
another	O
thread	B-Operating_System
when	O
the	O
current	O
executing	O
thread	B-Operating_System
causes	O
some	O
long	O
latency	O
events	O
(	O
like	O
page	O
fault	O
etc	O
.	O
)	O
.	O
</s>
<s>
Coarse-grain	O
multithreading	B-Operating_System
is	O
more	O
common	O
for	O
less	O
context	O
switch	O
between	O
threads	B-Operating_System
.	O
</s>
<s>
For	O
example	O
,	O
Intel	O
's	O
Montecito	B-Device
processor	O
uses	O
coarse-grained	O
multithreading	B-Operating_System
,	O
while	O
Sun	O
's	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
uses	O
fine-grained	O
multithreading	B-Operating_System
.	O
</s>
<s>
For	O
those	O
processors	O
that	O
have	O
only	O
one	O
pipeline	O
per	O
core	O
,	O
interleaved	O
multithreading	B-Operating_System
is	O
the	O
only	O
possible	O
way	O
,	O
because	O
it	O
can	O
issue	O
at	O
most	O
one	O
instruction	O
per	O
cycle	O
.	O
</s>
<s>
Simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
:	O
Issue	O
multiple	O
instructions	O
from	O
multiple	O
threads	B-Operating_System
in	O
one	O
cycle	O
.	O
</s>
<s>
The	O
processor	O
must	O
be	O
superscalar	B-General_Concept
to	O
do	O
so	O
.	O
</s>
<s>
Chip-level	B-Architecture
multiprocessing	I-Architecture
(	O
CMP	O
or	O
multicore	B-Architecture
)	O
:	O
integrates	O
two	O
or	O
more	O
processors	O
into	O
one	O
chip	O
,	O
each	O
executing	O
threads	B-Operating_System
independently	O
.	O
</s>
<s>
The	O
key	O
factor	O
to	O
distinguish	O
them	O
is	O
to	O
look	O
at	O
how	O
many	O
instructions	O
the	O
processor	O
can	O
issue	O
in	O
one	O
cycle	O
and	O
how	O
many	O
threads	B-Operating_System
from	O
which	O
the	O
instructions	O
come	O
.	O
</s>
<s>
For	O
example	O
,	O
Sun	O
Microsystems	O
 '	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
is	O
a	O
multicore	B-Architecture
processor	I-Architecture
combined	O
with	O
fine-grain	O
multithreading	B-Operating_System
technique	O
instead	O
of	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
because	O
each	O
core	O
can	O
only	O
issue	O
one	O
instruction	O
at	O
a	O
time	O
.	O
</s>
<s>
While	O
multithreading	B-Operating_System
CPUs	B-General_Concept
have	O
been	O
around	O
since	O
the	O
1950s	O
,	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
was	O
first	O
researched	O
by	O
IBM	O
in	O
1968	O
as	O
part	O
of	O
the	O
ACS-360	B-Device
project	O
.	O
</s>
<s>
The	O
first	O
major	O
commercial	O
microprocessor	O
developed	O
with	O
SMT	O
was	O
the	O
Alpha	B-General_Concept
21464	I-General_Concept
(	O
EV8	O
)	O
.	O
</s>
<s>
The	O
microprocessor	O
was	O
never	O
released	O
,	O
since	O
the	O
Alpha	O
line	O
of	O
microprocessors	O
was	O
discontinued	O
shortly	O
before	O
HP	O
acquired	O
Compaq	O
which	O
had	O
in	O
turn	O
acquired	O
DEC	O
.	O
Dean	O
Tullsen	O
's	O
work	O
was	O
also	O
used	O
to	O
develop	O
the	O
hyper-threaded	B-Operating_System
versions	O
of	O
the	O
Intel	B-General_Concept
Pentium4	I-General_Concept
microprocessors	O
,	O
such	O
as	O
the	O
"	O
Northwood	O
"	O
and	O
"	O
Prescott	O
"	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
was	O
the	O
first	O
modern	O
desktop	O
processor	O
to	O
implement	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
starting	O
from	O
the	O
3.06GHz	O
model	O
released	O
in	O
2002	O
,	O
and	O
since	O
introduced	O
into	O
a	O
number	O
of	O
their	O
processors	O
.	O
</s>
<s>
Intel	O
calls	O
the	O
functionality	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
,	O
and	O
provides	O
a	O
basic	O
two-thread	O
SMT	O
engine	O
.	O
</s>
<s>
Intel	O
claims	O
up	O
to	O
a	O
30%	O
speed	O
improvement	O
compared	O
against	O
an	O
otherwise	O
identical	O
,	O
non-SMT	O
Pentium4	B-General_Concept
.	O
</s>
<s>
The	O
performance	O
improvement	O
seen	O
is	O
very	O
application-dependent	O
;	O
however	O
,	O
when	O
running	O
two	O
programs	O
that	O
require	O
full	O
attention	O
of	O
the	O
processor	O
it	O
can	O
actually	O
seem	O
like	O
one	O
or	O
both	O
of	O
the	O
programs	O
slows	O
down	O
slightly	O
when	O
Hyper-threading	B-Operating_System
is	O
turned	O
on	O
.	O
</s>
<s>
This	O
is	O
due	O
to	O
the	O
replay	B-Device
system	I-Device
of	O
the	O
Pentium4	B-General_Concept
tying	O
up	O
valuable	O
execution	O
resources	O
,	O
increasing	O
contention	O
for	O
resources	O
such	O
as	O
bandwidth	O
,	O
caches	O
,	O
TLBs	B-Architecture
,	O
re-order	B-General_Concept
buffer	I-General_Concept
entries	O
,	O
and	O
equalizing	O
the	O
processor	O
resources	O
between	O
the	O
two	O
programs	O
which	O
adds	O
a	O
varying	O
amount	O
of	O
execution	O
time	O
.	O
</s>
<s>
The	O
Pentium4	B-General_Concept
Prescott	O
core	O
gained	O
a	O
replay	O
queue	O
,	O
which	O
reduces	O
execution	O
time	O
needed	O
for	O
the	O
replay	B-Device
system	I-Device
.	O
</s>
<s>
The	O
latest	O
Imagination	O
Technologies	O
MIPS	B-Device
architecture	I-Device
designs	O
include	O
an	O
SMT	O
system	O
known	O
as	O
"	O
MIPS	O
MT	O
"	O
.	O
</s>
<s>
RMI	O
,	O
a	O
Cupertino-based	O
startup	O
,	O
is	O
the	O
first	O
MIPS	O
vendor	O
to	O
provide	O
a	O
processor	O
SOC	B-Architecture
based	O
on	O
eight	O
cores	O
,	O
each	O
of	O
which	O
runs	O
four	O
threads	B-Operating_System
.	O
</s>
<s>
The	O
threads	B-Operating_System
can	O
be	O
run	O
in	O
fine-grain	O
mode	O
where	O
a	O
different	O
thread	B-Operating_System
can	O
be	O
executed	O
each	O
cycle	O
.	O
</s>
<s>
The	O
threads	B-Operating_System
can	O
also	O
be	O
assigned	O
priorities	O
.	O
</s>
<s>
Imagination	O
Technologies	O
MIPS	O
CPUs	B-General_Concept
have	O
two	O
SMT	O
threads	B-Operating_System
per	O
core	O
.	O
</s>
<s>
The	O
IBM	O
POWER5	B-Device
,	O
announced	O
in	O
May	O
2004	O
,	O
comes	O
as	O
either	O
a	O
dual	B-Architecture
core	I-Architecture
dual-chip	O
module	O
(	O
DCM	O
)	O
,	O
or	O
quad-core	B-Architecture
or	O
oct-core	O
multi-chip	O
module	O
(	O
MCM	O
)	O
,	O
with	O
each	O
core	O
including	O
a	O
two-thread	O
SMT	O
engine	O
.	O
</s>
<s>
IBM	O
's	O
implementation	O
is	O
more	O
sophisticated	O
than	O
the	O
previous	O
ones	O
,	O
because	O
it	O
can	O
assign	O
a	O
different	O
priority	O
to	O
the	O
various	O
threads	B-Operating_System
,	O
is	O
more	O
fine-grained	O
,	O
and	O
the	O
SMT	O
engine	O
can	O
be	O
turned	O
on	O
and	O
off	O
dynamically	O
,	O
to	O
better	O
execute	O
those	O
workloads	O
where	O
an	O
SMT	O
processor	O
would	O
not	O
increase	O
performance	O
.	O
</s>
<s>
This	O
is	O
IBM	O
's	O
second	O
implementation	O
of	O
generally	O
available	O
hardware	B-General_Concept
multithreading	I-General_Concept
.	O
</s>
<s>
In	O
2010	O
,	O
IBM	O
released	O
systems	O
based	O
on	O
the	O
POWER7	O
processor	O
with	O
eight	O
cores	O
with	O
each	O
having	O
four	O
Simultaneous	O
Intelligent	O
Threads	B-Operating_System
.	O
</s>
<s>
This	O
switches	O
the	O
threading	O
mode	O
between	O
one	O
thread	B-Operating_System
,	O
two	O
threads	B-Operating_System
or	O
four	O
threads	B-Operating_System
depending	O
on	O
the	O
number	O
of	O
process	O
threads	B-Operating_System
being	O
scheduled	O
at	O
the	O
time	O
.	O
</s>
<s>
IBM	O
POWER8	B-Device
has	O
8	O
intelligent	O
simultaneous	O
threads	B-Operating_System
per	O
core	O
(	O
SMT8	O
)	O
.	O
</s>
<s>
IBM	B-Device
Z	I-Device
starting	O
with	O
the	O
z13	B-Device
processor	O
in	O
2013	O
has	O
two	O
threads	B-Operating_System
per	O
core	O
(	O
SMT-2	O
)	O
.	O
</s>
<s>
Although	O
many	O
people	O
reported	O
that	O
Sun	O
Microsystems	O
 '	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
(	O
known	O
as	O
"	O
Niagara	B-General_Concept
"	O
until	O
its	O
14	O
November	O
2005	O
release	O
)	O
and	O
the	O
now	O
defunct	O
processor	O
codenamed	O
"	O
Rock	B-Device
"	O
(	O
originally	O
announced	O
in	O
2005	O
,	O
but	O
after	O
many	O
delays	O
cancelled	O
in	O
2010	O
)	O
are	O
implementations	O
of	O
SPARC	B-Architecture
focused	O
almost	O
entirely	O
on	O
exploiting	O
SMT	O
and	O
CMP	O
techniques	O
,	O
Niagara	B-General_Concept
is	O
not	O
actually	O
using	O
SMT	O
.	O
</s>
<s>
The	O
Niagara	B-General_Concept
has	O
eight	O
cores	O
,	O
but	O
each	O
core	O
has	O
only	O
one	O
pipeline	O
,	O
so	O
actually	O
it	O
uses	O
fine-grained	O
multithreading	B-Operating_System
.	O
</s>
<s>
Unlike	O
SMT	O
,	O
where	O
instructions	O
from	O
multiple	O
threads	B-Operating_System
share	O
the	O
issue	O
window	O
each	O
cycle	O
,	O
the	O
processor	O
uses	O
a	O
round	O
robin	O
policy	O
to	O
issue	O
instructions	O
from	O
the	O
next	O
active	O
thread	B-Operating_System
each	O
cycle	O
.	O
</s>
<s>
This	O
makes	O
it	O
more	O
similar	O
to	O
a	O
barrel	B-Operating_System
processor	I-Operating_System
.	O
</s>
<s>
Sun	O
Microsystems	O
 '	O
Rock	B-Device
processor	I-Device
is	O
different	O
:	O
it	O
has	O
more	O
complex	O
cores	O
that	O
have	O
more	O
than	O
one	O
pipeline	O
.	O
</s>
<s>
The	B-Application
Oracle	I-Application
Corporation	I-Application
SPARC	B-Architecture
T3	O
has	O
eight	O
fine-grained	O
threads	B-Operating_System
per	O
core	O
;	O
SPARC	B-Architecture
T4	O
,	O
SPARC	B-Architecture
T5	O
,	O
SPARC	B-Architecture
M5	O
,	O
M6	O
and	O
M7	O
have	O
eight	O
fine-grained	O
threads	B-Operating_System
per	O
core	O
of	O
which	O
two	O
can	O
be	O
executed	O
simultaneously	O
.	O
</s>
<s>
Fujitsu	O
SPARC64	O
VI	O
has	O
coarse-grained	O
Vertical	O
Multithreading	B-Operating_System
(	O
VMT	O
)	O
SPARC	B-Architecture
VII	O
and	O
newer	O
have	O
2-way	O
SMT	O
.	O
</s>
<s>
Intel	B-General_Concept
Itanium	I-General_Concept
Montecito	B-Device
uses	O
coarse-grained	O
multithreading	B-Operating_System
and	O
Tukwila	O
and	O
newer	O
ones	O
use	O
2-way	O
SMT	O
(	O
with	O
dual-domain	O
multithreading	B-Operating_System
)	O
.	O
</s>
<s>
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
has	O
4-way	O
SMT	O
(	O
with	O
time-multiplexed	O
multithreading	B-Operating_System
)	O
with	O
hardware-based	O
threads	B-Operating_System
which	O
cannot	O
be	O
disabled	O
,	O
unlike	O
regular	O
Hyper-Threading	B-Operating_System
.	O
</s>
<s>
The	O
Intel	B-Device
Atom	I-Device
,	O
first	O
released	O
in	O
2008	O
,	O
is	O
the	O
first	O
Intel	O
product	O
to	O
feature	O
2-way	O
SMT	O
(	O
marketed	O
as	O
Hyper-Threading	B-Operating_System
)	O
without	O
supporting	O
instruction	O
reordering	O
,	O
speculative	O
execution	O
,	O
or	O
register	O
renaming	O
.	O
</s>
<s>
Intel	O
reintroduced	O
Hyper-Threading	B-Operating_System
with	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
,	O
after	O
its	O
absence	O
on	O
the	O
Core	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
AMD	O
Bulldozer	O
microarchitecture	O
FlexFPU	O
and	O
Shared	O
L2	O
cache	O
are	O
multithreaded	O
but	O
integer	O
cores	O
in	O
module	O
are	O
single	B-Operating_System
threaded	I-Operating_System
,	O
so	O
it	O
is	O
only	O
a	O
partial	O
SMT	O
implementation	O
.	O
</s>
<s>
VISC	O
architecture	O
uses	O
the	O
Virtual	O
Software	O
Layer	O
(	O
translation	O
layer	O
)	O
to	O
dispatch	O
a	O
single	B-Operating_System
thread	I-Operating_System
of	O
instructions	O
to	O
the	O
Global	O
Front	O
End	O
which	O
splits	O
instructions	O
into	O
virtual	O
hardware	O
threadlets	O
which	O
are	O
then	O
dispatched	O
to	O
separate	O
virtual	O
cores	O
.	O
</s>
<s>
Multiple	O
virtual	O
cores	O
can	O
push	O
threadlets	O
into	O
the	O
reorder	B-General_Concept
buffer	I-General_Concept
of	O
a	O
single	O
physical	O
core	O
,	O
which	O
can	O
split	O
partial	O
instructions	O
and	O
data	O
from	O
multiple	O
threadlets	O
through	O
the	O
execution	O
ports	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
This	O
form	O
of	O
multithreading	B-Operating_System
can	O
increase	O
single	B-Operating_System
threaded	I-Operating_System
performance	O
by	O
allowing	O
a	O
single	B-Operating_System
thread	I-Operating_System
to	O
use	O
all	O
resources	O
of	O
the	O
CPU	O
.	O
</s>
<s>
Depending	O
on	O
the	O
design	O
and	O
architecture	O
of	O
the	O
processor	O
,	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
can	O
decrease	O
performance	O
if	O
any	O
of	O
the	O
shared	B-General_Concept
resources	I-General_Concept
are	O
bottlenecks	O
for	O
performance	O
.	O
</s>
<s>
Critics	O
argue	O
that	O
it	O
is	O
a	O
considerable	O
burden	O
to	O
put	O
on	O
software	O
developers	O
that	O
they	O
have	O
to	O
test	O
whether	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
is	O
good	O
or	O
bad	O
for	O
their	O
application	O
in	O
various	O
situations	O
and	O
insert	O
extra	O
logic	O
to	O
turn	O
it	O
off	O
if	O
it	O
decreases	O
performance	O
.	O
</s>
<s>
Current	O
operating	O
systems	O
lack	O
convenient	O
API	B-Application
calls	O
for	O
this	O
purpose	O
and	O
for	O
preventing	O
processes	O
with	O
different	O
priority	O
from	O
taking	O
resources	O
from	O
each	O
other	O
.	O
</s>
<s>
There	O
is	O
also	O
a	O
security	O
concern	O
with	O
certain	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
implementations	O
.	O
</s>
<s>
Intel	O
's	O
hyperthreading	B-Operating_System
in	O
NetBurst-based	O
processors	O
has	O
a	O
vulnerability	O
through	O
which	O
it	O
is	O
possible	O
for	O
one	O
application	O
to	O
steal	O
a	O
cryptographic	O
key	O
from	O
another	O
application	O
running	O
in	O
the	O
same	O
processor	O
by	O
monitoring	O
its	O
cache	O
use	O
.	O
</s>
