<s>
The	O
Simple	B-Architecture
Bus	I-Architecture
Architecture	I-Architecture
(	O
SBA	O
)	O
is	O
a	O
form	O
of	O
computer	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
It	O
is	O
made	O
up	O
software	O
tools	O
and	O
intellectual	O
property	O
cores	O
(	O
IP	B-Architecture
Core	I-Architecture
)	O
interconnected	O
by	O
buses	B-General_Concept
using	O
simple	O
and	O
clear	O
rules	O
,	O
that	O
allow	O
the	O
implementation	O
of	O
an	O
embedded	B-Architecture
system	I-Architecture
(	O
SoC	B-Architecture
)	O
.	O
</s>
<s>
The	O
VHDL	B-Language
code	O
that	O
implements	O
this	O
architecture	O
is	O
portable	O
.	O
</s>
<s>
The	O
master	O
core	O
is	O
a	O
finite	B-Architecture
state	I-Architecture
machine	I-Architecture
(	O
FSM	O
)	O
and	O
performs	O
basic	O
data	O
flow	O
and	O
processing	O
,	O
similar	O
to	O
a	O
microprocessor	B-Architecture
,	O
but	O
with	O
lower	O
consumption	O
of	O
logic	O
resources	O
.	O
</s>
<s>
SBA	O
is	O
an	O
application	O
and	O
a	O
simplified	O
version	O
of	O
the	O
Wishbone	B-Architecture
specification	O
.	O
</s>
<s>
SBA	O
implements	O
the	O
minimum	O
essential	O
subset	O
of	O
the	O
Wishbone	B-Architecture
signals	O
interface	O
.	O
</s>
<s>
It	O
can	O
be	O
connected	O
with	O
simple	O
Wishbone	B-Architecture
IP	B-Architecture
Cores	I-Architecture
.	O
</s>
<s>
Several	O
slave	O
IP	B-Architecture
Cores	I-Architecture
were	O
developed	O
following	O
the	O
SBA	O
architecture	O
,	O
many	O
to	O
implement	O
virtual	O
instruments	O
.	O
</s>
