<s>
The	O
Simple-As-Possible	B-Architecture
(	O
SAP	O
)	O
computer	O
is	O
a	O
simplified	O
computer	B-General_Concept
architecture	I-General_Concept
designed	O
for	O
educational	O
purposes	O
and	O
described	O
in	O
the	O
book	O
Digital	O
Computer	O
Electronics	O
by	O
Albert	O
Paul	O
Malvino	O
and	O
Jerald	O
A	O
.	O
</s>
<s>
SAP-2	O
and	O
SAP-3	O
are	O
fully	O
Turing-complete	B-Algorithm
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
that	O
the	O
computer	O
final	O
version	O
(	O
SAP-3	O
)	O
is	O
designed	O
to	O
implement	O
is	O
patterned	O
after	O
and	O
upward	B-General_Concept
compatible	I-General_Concept
with	O
the	O
ISA	O
of	O
the	O
Intel	O
8080/8085	O
microprocessor	O
family	O
.	O
</s>
<s>
YouTuber	O
and	O
former	O
Khan	O
Academy	O
employee	O
Ben	O
Eater	O
created	O
a	O
tutorial	O
building	O
an	O
8-bit	O
Turing-complete	B-Algorithm
SAP	O
computer	O
on	O
breadboards	O
from	O
logical	O
chips	O
(	O
7400-series	O
)	O
capable	O
of	O
running	O
simple	O
programs	O
such	O
as	O
computing	O
the	O
Fibonacci	B-Algorithm
sequence	I-Algorithm
.	O
</s>
<s>
Three	O
register	B-General_Concept
modules	O
(	O
Register	B-General_Concept
A	O
,	O
Register	B-General_Concept
B	O
,	O
and	O
the	O
Instruction	O
Register	B-General_Concept
)	O
that	O
"	O
store	O
small	O
amounts	O
of	O
data	O
that	O
the	O
CPU	O
is	O
processing.	O
"	O
</s>
<s>
An	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
capable	O
of	O
adding	O
and	O
subtracting	O
8-bit	O
2	B-General_Concept
's	I-General_Concept
complement	I-General_Concept
integers	O
from	O
registers	O
A	O
and	O
B	O
.	O
</s>
<s>
This	O
module	O
also	O
has	O
a	O
flags	O
register	B-General_Concept
with	O
two	O
possible	O
flags	O
(	O
Z	O
and	O
C	O
)	O
.	O
</s>
<s>
A	O
RAM	B-Architecture
module	O
capable	O
of	O
storing	O
16	O
bytes	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
RAM	B-Architecture
is	O
4-bit	O
addressable	O
.	O
</s>
<s>
A	O
4-bit	O
program	B-General_Concept
counter	I-General_Concept
that	O
keeps	O
track	O
of	O
the	O
current	O
processor	O
instruction	O
,	O
corresponding	O
to	O
a	O
4-bit	O
addressable	O
RAM	B-Architecture
.	O
</s>
<s>
An	O
output	O
register	B-General_Concept
that	O
displays	O
its	O
content	O
on	O
four	O
7-segment	O
displays	O
,	O
capable	O
of	O
displaying	O
both	O
unsigned	O
and	O
2	B-General_Concept
's	I-General_Concept
complement	I-General_Concept
signed	O
integers	O
.	O
</s>
<s>
The	O
7-segment	O
display	O
outputs	O
are	O
controlled	O
by	O
EEPROMs	B-General_Concept
,	O
which	O
are	O
programmed	O
using	O
an	O
Arduino	O
microcontroller	B-Architecture
.	O
</s>
<s>
A	O
bus	B-General_Concept
that	O
connects	O
these	O
components	O
together	O
.	O
</s>
<s>
The	O
components	O
connect	O
to	O
the	O
bus	B-General_Concept
using	O
tri-state	B-Device
buffers	O
.	O
</s>
<s>
A	O
"	O
control	O
logic	O
"	O
module	O
that	O
defines	O
"	O
the	O
opcodes	O
the	O
processor	O
recognizes	O
and	O
what	O
happens	O
when	O
it	O
executes	O
each	O
instruction	O
,	O
"	O
as	O
well	O
as	O
enabling	O
the	O
computer	O
to	O
be	O
Turing-complete	B-Algorithm
.	O
</s>
<s>
The	O
CPU	O
microcodes	B-Device
are	O
programmed	O
into	O
EEPROMs	B-General_Concept
using	O
an	O
Arduino	O
microcontroller	B-Architecture
.	O
</s>
<s>
Ben	O
Eater	O
's	O
design	O
has	O
inspired	O
multiple	O
other	O
variants	O
and	O
improvements	O
,	O
primarily	O
on	O
Eater	O
's	O
Reddit	B-Application
forum	O
.	O
</s>
<s>
An	O
expanded	O
RAM	B-Architecture
module	O
capable	O
of	O
storing	O
256	O
bytes	O
,	O
utilizing	O
the	O
entire	O
8-bit	O
address	O
space	O
.	O
</s>
<s>
With	O
the	O
help	O
of	O
segmentation	B-General_Concept
registers	I-General_Concept
,	O
the	O
RAM	B-Architecture
module	O
can	O
be	O
further	O
expanded	O
to	O
a	O
16-bit	O
address	O
space	O
,	O
matching	O
the	O
standard	O
for	O
8-bit	O
computers	O
.	O
</s>
<s>
A	O
stack	O
register	B-General_Concept
that	O
allows	O
incrementing	O
and	O
decrementing	O
the	O
stack	O
pointer	O
.	O
</s>
