<s>
In	O
semiconductor	B-Architecture
manufacturing	I-Architecture
,	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
technology	O
is	O
fabrication	B-Architecture
of	O
silicon	O
semiconductor	O
devices	O
in	O
a	O
layered	O
silicon	O
–	O
insulator	O
–	O
silicon	O
substrate	B-Architecture
,	O
to	O
reduce	O
parasitic	O
capacitance	O
within	O
the	O
device	O
,	O
thereby	O
improving	O
performance	O
.	O
</s>
<s>
SOI-based	O
devices	O
differ	O
from	O
conventional	O
silicon-built	O
devices	O
in	O
that	O
the	O
silicon	O
junction	O
is	O
above	O
an	O
electrical	O
insulator	O
,	O
typically	O
silicon	O
dioxide	O
or	O
sapphire	B-Application
(	O
these	O
types	O
of	O
devices	O
are	O
called	O
silicon	B-Algorithm
on	I-Algorithm
sapphire	I-Algorithm
,	O
or	O
SOS	O
)	O
.	O
</s>
<s>
The	O
choice	O
of	O
insulator	O
depends	O
largely	O
on	O
intended	O
application	O
,	O
with	O
sapphire	B-Application
being	O
used	O
for	O
high-performance	O
radio	O
frequency	O
(	O
RF	O
)	O
and	O
radiation-sensitive	O
applications	O
,	O
and	O
silicon	O
dioxide	O
for	O
diminished	O
short-channel	O
effects	O
in	O
other	O
microelectronics	O
devices	O
.	O
</s>
<s>
Reported	O
benefits	O
of	O
SOI	O
relative	O
to	O
conventional	O
silicon	O
(	O
bulk	O
CMOS	B-Device
)	O
processing	O
include	O
:	O
</s>
<s>
From	O
a	O
manufacturing	O
perspective	O
,	O
SOI	O
substrates	B-Architecture
are	O
compatible	O
with	O
most	O
conventional	O
fabrication	B-Architecture
processes	O
.	O
</s>
<s>
Among	O
challenges	O
unique	O
to	O
SOI	O
are	O
novel	O
metrology	O
requirements	O
to	O
account	O
for	O
the	O
buried	B-Algorithm
oxide	I-Algorithm
layer	O
and	O
concerns	O
about	O
differential	O
stress	O
in	O
the	O
topmost	O
silicon	O
layer	O
.	O
</s>
<s>
The	O
primary	O
barrier	O
to	O
SOI	O
implementation	O
is	O
the	O
drastic	O
increase	O
in	O
substrate	B-Architecture
cost	O
,	O
which	O
contributes	O
an	O
estimated	O
1015%	O
increase	O
to	O
total	O
manufacturing	O
costs	O
.	O
</s>
<s>
An	O
SOI	B-Algorithm
MOSFET	I-Algorithm
is	O
a	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MOSFET	B-Architecture
)	O
device	O
in	O
which	O
a	O
semiconductor	O
layer	O
such	O
as	O
silicon	O
or	O
germanium	O
is	O
formed	O
on	O
an	O
insulator	O
layer	O
which	O
may	O
be	O
a	O
buried	B-Algorithm
oxide	I-Algorithm
(	O
BOX	O
)	O
layer	O
formed	O
in	O
a	O
semiconductor	O
substrate	B-Architecture
.	O
</s>
<s>
SOI	B-Algorithm
MOSFET	I-Algorithm
devices	O
are	O
adapted	O
for	O
use	O
by	O
the	O
computer	O
industry	O
.	O
</s>
<s>
The	O
buried	B-Algorithm
oxide	I-Algorithm
layer	O
can	O
be	O
used	O
in	O
SRAM	B-Architecture
designs	O
.	O
</s>
<s>
There	O
are	O
two	O
types	O
of	O
SOI	B-Algorithm
devices	I-Algorithm
:	O
PDSOI	O
(	O
partially	O
depleted	O
SOI	O
)	O
and	O
FDSOI	O
(	O
fully	O
depleted	O
SOI	O
)	O
MOSFETs	B-Architecture
.	O
</s>
<s>
For	O
an	O
n-type	O
PDSOI	O
MOSFET	B-Architecture
the	O
sandwiched	O
n-type	O
film	O
between	O
the	O
gate	O
oxide	O
(	O
GOX	O
)	O
and	O
buried	B-Algorithm
oxide	I-Algorithm
(	O
BOX	O
)	O
is	O
large	O
,	O
so	O
the	O
depletion	O
region	O
ca	O
n't	O
cover	O
the	O
whole	O
n	O
region	O
.	O
</s>
<s>
So	O
to	O
some	O
extent	O
PDSOI	O
behaves	O
like	O
bulk	O
MOSFET	B-Architecture
.	O
</s>
<s>
Obviously	O
there	O
are	O
some	O
advantages	O
over	O
the	O
bulk	O
MOSFETs	B-Architecture
.	O
</s>
<s>
The	O
limitation	O
of	O
the	O
depletion	O
charge	O
by	O
the	O
BOX	O
induces	O
a	O
suppression	O
of	O
the	O
depletion	O
capacitance	O
and	O
therefore	O
a	O
substantial	O
reduction	O
of	O
the	O
subthreshold	O
swing	O
allowing	O
FD	O
SOI	B-Algorithm
MOSFETs	I-Algorithm
to	O
work	O
at	O
lower	O
gate	O
bias	O
resulting	O
in	O
lower	O
power	O
operation	O
.	O
</s>
<s>
The	O
subthreshold	O
swing	O
can	O
reach	O
the	O
minimum	O
theoretical	O
value	O
for	O
MOSFET	B-Architecture
at	O
300K	O
,	O
which	O
is	O
60mV/decade	O
.	O
</s>
<s>
Other	O
drawbacks	O
in	O
bulk	O
MOSFETs	B-Architecture
,	O
like	O
threshold	O
voltage	O
roll	O
off	O
,	O
etc	O
.	O
</s>
<s>
SiO2-based	O
SOI	O
wafers	B-Architecture
can	O
be	O
produced	O
by	O
several	O
methods	O
:	O
</s>
<s>
Wafer	B-Algorithm
bonding	I-Algorithm
the	O
insulating	O
layer	O
is	O
formed	O
by	O
directly	O
bonding	O
oxidized	O
silicon	O
with	O
a	O
second	O
substrate	B-Architecture
.	O
</s>
<s>
The	O
majority	O
of	O
the	O
second	O
substrate	B-Architecture
is	O
subsequently	O
removed	O
,	O
the	O
remnants	O
forming	O
the	O
topmost	O
Si	O
layer	O
.	O
</s>
<s>
One	O
prominent	O
example	O
of	O
a	O
wafer	B-Algorithm
bonding	I-Algorithm
process	O
is	O
the	O
Smart	O
Cut	O
method	O
developed	O
by	O
the	O
French	O
firm	O
Soitec	O
which	O
uses	O
ion	O
implantation	O
followed	O
by	O
controlled	O
exfoliation	O
to	O
determine	O
the	O
thickness	O
of	O
the	O
uppermost	O
silicon	O
layer	O
.	O
</s>
<s>
Seed	O
methods	O
require	O
some	O
sort	O
of	O
template	O
for	O
homoepitaxy	O
,	O
which	O
may	O
be	O
achieved	O
by	O
chemical	O
treatment	O
of	O
the	O
insulator	O
,	O
an	O
appropriately	O
oriented	O
crystalline	O
insulator	O
,	O
or	O
vias	O
through	O
the	O
insulator	O
from	O
the	O
underlying	O
substrate	B-Architecture
.	O
</s>
<s>
The	O
silicon-on-insulator	B-Algorithm
concept	O
dates	O
back	O
to	O
1964	O
,	O
when	O
it	O
was	O
proposed	O
by	O
C.W.	O
</s>
<s>
Holloway	O
,	O
Kai	O
Fong	O
Lee	O
and	O
James	O
F	O
.	O
Gibbons	O
fabricated	B-Architecture
a	O
silicon-on-insulator	B-Algorithm
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
)	O
.	O
</s>
<s>
In	O
1983	O
,	O
a	O
Fujitsu	O
research	O
team	O
led	O
by	O
S	O
.	O
Kawamura	O
fabricated	B-Architecture
a	O
three-dimensional	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
with	O
SOI	O
CMOS	B-Device
(	O
complementary	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
)	O
structure	O
.	O
</s>
<s>
In	O
1984	O
,	O
the	O
same	O
Fujitsu	O
research	O
team	O
fabricated	B-Architecture
a	O
3D	O
gate	O
array	O
with	O
vertically	O
stacked	O
dual	O
SOI/CMOS	O
structure	O
using	O
beam	O
recrystallization	O
.	O
</s>
<s>
The	O
same	O
year	O
,	O
Electrotechnical	O
Laboratory	O
researchers	O
Toshihiro	O
Sekigawa	O
and	O
Yutaka	O
Hayashi	O
fabricated	B-Architecture
a	O
double-gate	B-Algorithm
MOSFET	I-Algorithm
,	O
demonstrating	O
that	O
short-channel	O
effects	O
can	O
be	O
significantly	O
reduced	O
by	O
sandwiching	O
a	O
fully	O
depleted	O
SOI	B-Algorithm
device	I-Algorithm
between	O
two	O
gate	O
electrodes	O
connected	O
together	O
.	O
</s>
<s>
In	O
1986	O
,	O
Jean-Pierre	O
Colinge	O
at	O
HP	O
Labs	O
fabricated	B-Architecture
SOI	O
NMOS	B-Algorithm
devices	O
using	O
90	O
nm	O
thin	O
silicon	O
films	O
.	O
</s>
<s>
Shahidi	O
was	O
a	O
key	O
figure	O
in	O
making	O
SOI	O
CMOS	B-Device
technology	O
a	O
manufacturable	O
reality	O
.	O
</s>
<s>
In	O
the	O
early	O
1990s	O
,	O
he	O
demonstrated	O
a	O
novel	O
technique	O
of	O
combining	O
silicon	O
epitaxial	O
overgrowth	O
and	O
chemical	O
mechanical	O
polishing	O
to	O
prepare	O
device-quality	O
SOI	O
material	O
for	O
fabricating	O
devices	O
and	O
simple	O
circuits	O
,	O
which	O
led	O
to	O
IBM	O
expanding	O
its	O
research	O
program	O
to	O
include	O
SOI	O
substrates	B-Architecture
.	O
</s>
<s>
He	O
was	O
also	O
the	O
first	O
to	O
demonstrate	O
the	O
power-delay	O
advantage	O
of	O
SOI	O
CMOS	B-Device
technology	O
over	O
traditional	O
bulk	O
CMOS	B-Device
in	O
microprocessor	B-Architecture
applications	O
.	O
</s>
<s>
He	O
overcame	O
barriers	O
preventing	O
the	O
semiconductor	O
industry	O
's	O
adoption	O
of	O
SOI	O
,	O
and	O
was	O
instrumental	O
in	O
driving	O
SOI	O
substrate	B-Architecture
development	O
to	O
the	O
quality	O
and	O
cost	O
levels	O
suitable	O
for	O
mass-production	O
.	O
</s>
<s>
In	O
1994	O
,	O
an	O
IBM	O
research	O
team	O
led	O
by	O
Shahidi	O
,	O
Bijan	O
Davari	O
and	O
Robert	O
H	O
.	O
Dennard	O
fabricated	B-Architecture
the	O
first	O
sub-100	O
nanometer	O
SOI	O
CMOS	B-Device
devices	O
.	O
</s>
<s>
In	O
1998	O
,	O
a	O
team	O
of	O
Hitachi	O
,	O
TSMC	O
and	O
UC	O
Berkeley	O
researchers	O
demonstrated	O
the	O
FinFET	O
(	O
fin	O
field-effect	O
transistor	O
)	O
,	O
which	O
is	O
a	O
non-planar	O
,	O
double-gate	B-Algorithm
MOSFET	I-Algorithm
built	O
on	O
an	O
SOI	O
substrate	B-Architecture
.	O
</s>
<s>
In	O
early	O
2001	O
,	O
Shahidi	O
used	O
SOI	O
to	O
developed	O
a	O
low-power	O
RF	O
CMOS	B-Device
device	O
,	O
resulting	O
in	O
increased	O
radio	O
frequency	O
,	O
at	O
IBM	O
.	O
</s>
<s>
Shahidi	O
's	O
research	O
at	O
IBM	O
led	O
to	O
the	O
first	O
commercial	O
use	O
of	O
SOI	O
in	O
mainstream	O
CMOS	B-Device
technology	O
.	O
</s>
<s>
SOI	O
was	O
first	O
commercialized	O
in	O
1995	O
,	O
when	O
Shahidi	O
's	O
work	O
on	O
SOI	O
convinced	O
John	O
Kelly	O
,	O
who	O
ran	O
IBM	O
's	O
server	O
division	O
,	O
to	O
adopt	O
SOI	O
in	O
the	O
AS/400	B-Device
line	O
of	O
server	O
products	O
,	O
which	O
used	O
220	O
nm	O
CMOS	B-Device
with	O
copper	O
metallization	O
SOI	B-Algorithm
devices	I-Algorithm
.	O
</s>
<s>
IBM	O
began	O
to	O
use	O
SOI	O
in	O
the	O
high-end	O
RS64-IV	O
"	O
Istar	O
"	O
PowerPC-AS	O
microprocessor	B-Architecture
in	O
2000	O
.	O
</s>
<s>
Other	O
examples	O
of	O
microprocessors	B-Architecture
built	O
on	O
SOI	O
technology	O
include	O
AMD	O
's	O
130nm	B-Algorithm
,	O
90nm	O
,	O
65nm	O
,	O
45nm	O
and	O
32nm	O
single	O
,	O
dual	O
,	O
quad	O
,	O
six	O
and	O
eight	O
core	O
processors	O
since	O
2001	O
.	O
</s>
<s>
In	O
late	O
2001	O
,	O
IBM	O
was	O
set	O
to	O
introduce	O
130	B-Algorithm
nanometer	I-Algorithm
CMOS	B-Device
SOI	B-Algorithm
devices	I-Algorithm
with	O
copper	O
and	O
low-κ	B-Algorithm
dielectric	I-Algorithm
for	O
the	O
back	O
end	O
,	O
based	O
on	O
Shahidi	O
's	O
work	O
.	O
</s>
<s>
Freescale	O
adopted	O
SOI	O
in	O
their	O
PowerPC	B-Architecture
7455	O
CPU	O
in	O
late	O
2001	O
.	O
</s>
<s>
The	O
90nm	O
PowerPC	B-Architecture
-	O
and	O
Power	O
ISA-based	O
processors	O
used	O
in	O
the	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
,	O
PlayStation	B-Operating_System
3	I-Operating_System
,	O
and	O
Wii	B-Operating_System
use	O
SOI	O
technology	O
as	O
well	O
.	O
</s>
<s>
Competitive	O
offerings	O
from	O
Intel	O
however	O
continue	O
to	O
use	O
conventional	O
bulk	O
CMOS	B-Device
technology	O
for	O
each	O
process	O
node	O
,	O
instead	O
focusing	O
on	O
other	O
venues	O
such	O
as	O
HKMG	B-Algorithm
and	O
tri-gate	O
transistors	O
to	O
improve	O
transistor	O
performance	O
.	O
</s>
<s>
In	O
1990	O
,	O
Peregrine	O
Semiconductor	O
began	O
development	O
of	O
an	O
SOI	O
process	O
technology	O
utilizing	O
a	O
standard	O
0.5μm	O
CMOS	B-Device
node	O
and	O
an	O
enhanced	O
sapphire	B-Application
substrate	B-Architecture
.	O
</s>
<s>
Its	O
patented	O
silicon	B-Algorithm
on	I-Algorithm
sapphire	I-Algorithm
(	O
SOS	O
)	O
process	O
is	O
widely	O
used	O
in	O
high-performance	O
RF	O
applications	O
.	O
</s>
<s>
The	O
intrinsic	O
benefits	O
of	O
the	O
insulating	O
sapphire	B-Application
substrate	B-Architecture
allow	O
for	O
high	O
isolation	O
,	O
high	O
linearity	O
and	O
electro-static	O
discharge	O
(	O
ESD	O
)	O
tolerance	O
.	O
</s>
<s>
SOI	O
wafers	B-Architecture
are	O
widely	O
used	O
in	O
silicon	O
photonics	O
.	O
</s>
<s>
used	O
conventional	O
silicon	B-Architecture
wafers	I-Architecture
to	O
build	O
their	O
CMOS	B-Device
chips	O
.	O
</s>
