<s>
A	O
shift	B-General_Concept
register	I-General_Concept
is	O
a	O
type	O
of	O
digital	O
circuit	O
using	O
a	O
cascade	O
of	O
flip-flops	B-General_Concept
where	O
the	O
output	O
of	O
one	O
flip-flop	B-General_Concept
is	O
connected	O
to	O
the	O
input	O
of	O
the	O
next	O
.	O
</s>
<s>
By	O
connecting	O
the	O
last	O
flip-flop	B-General_Concept
back	O
to	O
the	O
first	O
,	O
the	O
data	O
can	O
cycle	O
within	O
the	O
shifters	O
for	O
extended	O
periods	O
,	O
and	O
in	O
this	O
configuration	O
they	O
were	O
used	O
as	O
computer	B-General_Concept
memory	I-General_Concept
,	O
displacing	O
delay-line	O
memory	O
systems	O
in	O
the	O
late	O
1960s	O
and	O
early	O
1970s	O
.	O
</s>
<s>
In	O
most	O
cases	O
,	O
several	O
parallel	O
shift	B-General_Concept
registers	I-General_Concept
would	O
be	O
used	O
to	O
build	O
a	O
larger	O
memory	O
pool	O
known	O
as	O
a	O
"	O
bit	B-Data_Structure
array	I-Data_Structure
"	O
.	O
</s>
<s>
Data	O
was	O
stored	O
into	O
the	O
array	O
and	O
read	O
back	O
out	O
in	O
parallel	O
,	O
often	O
as	O
a	O
computer	O
word	O
,	O
while	O
each	O
bit	O
was	O
stored	O
serially	O
in	O
the	O
shift	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
There	O
is	O
an	O
inherent	O
trade-off	O
in	O
the	O
design	O
of	O
bit	B-Data_Structure
arrays	I-Data_Structure
;	O
putting	O
more	O
flip-flops	B-General_Concept
in	O
a	O
row	O
allows	O
a	O
single	O
shifter	O
to	O
store	O
more	O
bits	O
,	O
but	O
requires	O
more	O
clock	O
cycles	O
to	O
push	O
the	O
data	O
through	O
all	O
of	O
the	O
shifters	O
before	O
the	O
data	O
can	O
be	O
read	O
back	O
out	O
again	O
.	O
</s>
<s>
Shift	B-General_Concept
registers	I-General_Concept
can	O
have	O
both	O
parallel	O
and	O
serial	B-Protocol
inputs	O
and	O
outputs	O
.	O
</s>
<s>
These	O
are	O
often	O
configured	O
as	O
"	O
serial-in	O
,	O
parallel-out	O
"	O
(	O
SIPO	O
)	O
or	O
as	O
"	O
parallel-in	O
,	O
serial-out	O
"	O
(	O
PISO	O
)	O
.	O
</s>
<s>
There	O
are	O
also	O
types	O
that	O
have	O
both	O
serial	B-Protocol
and	O
parallel	O
input	O
and	O
types	O
with	O
serial	B-Protocol
and	O
parallel	O
output	O
.	O
</s>
<s>
There	O
are	O
also	O
"	O
bidirectional	O
"	O
shift	B-General_Concept
registers	I-General_Concept
,	O
which	O
allow	O
shifting	O
in	O
both	O
directions	O
:	O
L	O
→	O
R	O
or	O
R	O
→	O
L	O
.	O
</s>
<s>
The	O
serial	B-Protocol
input	O
and	O
last	O
output	O
of	O
a	O
shift	B-General_Concept
register	I-General_Concept
can	O
also	O
be	O
connected	O
to	O
create	O
a	O
"	O
circular	O
shift	B-General_Concept
register	I-General_Concept
"	O
.	O
</s>
<s>
+	O
Sample	O
usage	O
of	O
a	O
4-bit	O
shift	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
These	O
are	O
the	O
simplest	O
kind	O
of	O
shift	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
"	O
data	O
in	O
"	O
)	O
is	O
shifted	O
into	O
the	O
first	O
flip-flop	B-General_Concept
'	O
s	O
output	O
.	O
</s>
<s>
The	O
data	O
is	O
stored	O
after	O
each	O
flip-flop	B-General_Concept
on	O
the	O
"	O
Q	O
"	O
output	O
,	O
so	O
there	O
are	O
four	O
storage	O
"	O
slots	O
"	O
available	O
in	O
this	O
arrangement	O
,	O
hence	O
it	O
is	O
a	O
4-bit	O
register	O
.	O
</s>
<s>
The	O
right	O
hand	O
column	O
corresponds	O
to	O
the	O
right-most	O
flip-flop	B-General_Concept
'	O
s	O
output	O
pin	O
,	O
and	O
so	O
on	O
.	O
</s>
<s>
So	O
the	O
serial	B-Protocol
output	O
of	O
the	O
entire	O
register	O
is	O
00010110	O
.	O
</s>
<s>
This	O
arrangement	O
is	O
the	O
hardware	O
equivalent	O
of	O
a	O
queue	B-Application
.	O
</s>
<s>
This	O
configuration	O
allows	O
conversion	O
from	O
serial	B-Protocol
to	O
parallel	O
format	O
.	O
</s>
<s>
Data	O
input	O
is	O
serial	B-Protocol
,	O
as	O
described	O
in	O
the	O
SISO	O
section	O
above	O
.	O
</s>
<s>
In	O
this	O
configuration	O
,	O
each	O
flip-flop	B-General_Concept
is	O
edge	O
triggered	O
.	O
</s>
<s>
All	O
flip-flops	B-General_Concept
operate	O
at	O
the	O
given	O
clock	O
frequency	O
.	O
</s>
<s>
In	O
cases	O
where	O
the	O
parallel	O
outputs	O
should	O
not	O
change	O
during	O
the	O
serial	B-Protocol
loading	O
process	O
,	O
it	O
's	O
desirable	O
to	O
use	O
a	O
latched	O
or	O
buffered	B-General_Concept
output	O
.	O
</s>
<s>
In	O
a	O
latched	O
shift	B-General_Concept
register	I-General_Concept
(	O
such	O
as	O
the	O
74595	O
)	O
the	O
serial	B-Protocol
data	O
is	O
first	O
loaded	O
into	O
an	O
internal	O
buffer	B-General_Concept
register	O
,	O
then	O
upon	O
receipt	O
of	O
a	O
load	O
signal	O
the	O
state	O
of	O
the	O
buffer	B-General_Concept
register	O
is	O
copied	O
into	O
a	O
set	O
of	O
output	O
registers	O
.	O
</s>
<s>
In	O
general	O
,	O
the	O
practical	O
application	O
of	O
the	O
serial-in/parallel	O
-out	O
shift	B-General_Concept
register	I-General_Concept
is	O
to	O
convert	O
data	O
from	O
serial	B-Protocol
format	O
on	O
a	O
single	O
wire	O
to	O
parallel	O
format	O
on	O
multiple	O
wires	O
.	O
</s>
<s>
The	O
arrangement	O
now	O
acts	O
as	O
a	O
PISO	O
shift	B-General_Concept
register	I-General_Concept
,	O
with	O
D1	O
as	O
the	O
Data	O
Input	O
.	O
</s>
<s>
The	O
animation	O
below	O
shows	O
the	O
write/shift	O
sequence	O
,	O
including	O
the	O
internal	O
state	O
of	O
the	O
shift	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
One	O
of	O
the	O
most	O
common	O
uses	O
of	O
a	O
shift	B-General_Concept
register	I-General_Concept
is	O
to	O
convert	O
between	O
serial	B-Protocol
and	O
parallel	O
interfaces	O
.	O
</s>
<s>
This	O
is	O
useful	O
as	O
many	O
circuits	O
work	O
on	O
groups	O
of	O
bits	O
in	O
parallel	O
,	O
but	O
serial	B-Protocol
interfaces	O
are	O
simpler	O
to	O
construct	O
.	O
</s>
<s>
Shift	B-General_Concept
registers	I-General_Concept
can	O
be	O
used	O
as	O
simple	O
delay	O
circuits	O
.	O
</s>
<s>
Several	O
bidirectional	O
shift	B-General_Concept
registers	I-General_Concept
can	O
also	O
be	O
connected	O
in	O
parallel	O
for	O
a	O
hardware	O
implementation	O
of	O
a	O
stack	B-Application
.	O
</s>
<s>
SIPO	O
registers	O
are	O
commonly	O
attached	O
to	O
the	O
output	O
of	O
microprocessors	O
when	O
more	O
general-purpose	B-Architecture
input/output	I-Architecture
pins	O
are	O
required	O
than	O
are	O
available	O
.	O
</s>
<s>
The	O
devices	O
in	O
question	O
are	O
attached	O
to	O
the	O
parallel	O
outputs	O
of	O
the	O
shift	B-General_Concept
register	I-General_Concept
,	O
and	O
the	O
desired	O
state	O
for	O
all	O
those	O
devices	O
can	O
be	O
sent	O
out	O
of	O
the	O
microprocessor	O
using	O
a	O
single	O
serial	B-Protocol
connection	O
.	O
</s>
<s>
Similarly	O
,	O
PISO	O
configurations	O
are	O
commonly	O
used	O
to	O
add	O
more	O
binary	O
inputs	O
to	O
a	O
microprocessor	O
than	O
are	O
available	O
–	O
each	O
binary	O
input	O
(	O
such	O
as	O
a	O
button	O
or	O
more	O
complicated	O
circuitry	O
)	O
is	O
attached	O
to	O
a	O
parallel	O
input	O
of	O
the	O
shift	B-General_Concept
register	I-General_Concept
,	O
then	O
the	O
data	O
is	O
sent	O
back	O
via	O
serial	B-Protocol
to	O
the	O
microprocessor	O
using	O
several	O
fewer	O
lines	O
than	O
originally	O
required	O
.	O
</s>
<s>
Shift	B-General_Concept
registers	I-General_Concept
can	O
also	O
be	O
used	O
as	O
pulse	O
extenders	O
.	O
</s>
<s>
An	O
example	O
of	O
such	O
a	O
pulse	O
extender	O
is	O
the	O
Ronja	O
Twister	O
,	O
wherein	O
five	O
74164	O
shift	B-General_Concept
registers	I-General_Concept
create	O
the	O
core	O
of	O
the	O
timing	O
logic	O
this	O
way	O
(	O
)	O
.	O
</s>
<s>
In	O
early	O
computers	O
,	O
shift	B-General_Concept
registers	I-General_Concept
were	O
used	O
to	O
handle	O
data	O
processing	O
:	O
two	O
numbers	O
to	O
be	O
added	O
were	O
stored	O
in	O
two	O
shift	B-General_Concept
registers	I-General_Concept
and	O
clocked	O
out	O
into	O
an	O
arithmetic	B-General_Concept
and	I-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
with	O
the	O
result	O
being	O
fed	O
back	O
to	O
the	O
input	O
of	O
one	O
of	O
the	O
shift	B-General_Concept
registers	I-General_Concept
(	O
the	O
accumulator	O
)	O
,	O
which	O
was	O
one	O
bit	O
longer	O
,	O
since	O
binary	O
addition	O
can	O
only	O
result	O
in	O
an	O
answer	O
that	O
has	O
the	O
same	O
size	O
or	O
is	O
one	O
bit	O
longer	O
.	O
</s>
<s>
Very	O
large	O
serial-in	O
serial-out	O
shift	B-General_Concept
registers	I-General_Concept
(	O
thousands	O
of	O
bits	O
in	O
size	O
)	O
were	O
used	O
in	O
a	O
similar	O
manner	O
to	O
the	O
earlier	O
delay-line	O
memory	O
in	O
some	O
devices	O
built	O
in	O
the	O
early	O
1970s	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
Datapoint	O
3300	O
terminal	O
stored	O
its	O
display	O
of	O
25rows	O
of	O
72	O
columns	O
of	O
6-bit	O
upper-case	O
characters	O
using	O
54	O
200-bit	O
shift	B-General_Concept
registers	I-General_Concept
(	O
arranged	O
in	O
6	O
tracks	O
of	O
9	O
packs	O
)	O
,	O
providing	O
storage	O
for	O
1800	O
characters	O
.	O
</s>
<s>
The	O
shift	B-General_Concept
register	I-General_Concept
design	O
meant	O
that	O
scrolling	O
the	O
terminal	O
display	O
could	O
be	O
accomplished	O
by	O
simply	O
pausing	O
the	O
display	O
output	O
to	O
skip	O
one	O
line	O
of	O
characters	O
.	O
</s>
<s>
One	O
of	O
the	O
first	O
known	O
examples	O
of	O
a	O
shift	B-General_Concept
register	I-General_Concept
was	O
in	O
the	O
Mark	O
2	O
Colossus	B-Device
,	O
a	O
code-breaking	O
machine	O
built	O
in	O
1944	O
.	O
</s>
<s>
A	O
shift	B-General_Concept
register	I-General_Concept
was	O
also	O
used	O
in	O
the	O
IAS	B-Device
machine	I-Device
,	O
built	O
by	O
John	O
von	O
Neumann	O
and	O
others	O
at	O
the	O
Institute	O
for	O
Advanced	O
Study	O
in	O
the	O
late	O
1940s	O
.	O
</s>
