<s>
A	O
shelving	B-Operating_System
buffer	I-Operating_System
is	O
a	O
technique	O
used	O
in	O
computer	O
processors	O
to	O
increase	O
the	O
efficiency	O
of	O
superscalar	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
It	O
allows	O
for	O
multiple	O
instructions	O
to	O
be	O
dispatched	O
at	O
once	O
regardless	O
of	O
the	O
data	B-Operating_System
dependencies	I-Operating_System
between	O
those	O
instructions	O
.	O
</s>
<s>
This	O
allows	O
for	O
out-of-order	B-General_Concept
execution	I-General_Concept
to	O
occur	O
which	O
increases	O
the	O
throughput	O
of	O
the	O
microprocessor	O
.	O
</s>
<s>
A	O
superscalar	B-General_Concept
processor	I-General_Concept
allows	O
the	O
execution	O
of	O
a	O
number	O
of	O
instructions	O
simultaneously	O
in	O
the	O
core	O
of	O
the	O
processor	O
itself	O
,	O
although	O
this	O
behavior	O
is	O
not	O
to	O
be	O
confused	O
with	O
a	O
multi-processor	O
system	O
.	O
</s>
<s>
Most	O
modern	O
processors	O
are	O
superscalar	B-General_Concept
.	O
</s>
<s>
In	O
a	O
superscalar	B-General_Concept
processor	I-General_Concept
multiple	O
instructions	O
are	O
dispatched	O
from	O
the	O
same	O
thread	O
.	O
</s>
<s>
simultaneously	O
)	O
raises	O
problems	O
with	O
data	B-Operating_System
dependencies	I-Operating_System
,	O
meaning	O
that	O
some	O
instructions	O
may	O
be	O
dependent	O
on	O
the	O
results	O
of	O
others	O
,	O
and	O
hence	O
care	O
must	O
be	O
taken	O
to	O
execute	O
in	O
the	O
correct	O
order	O
.	O
</s>
<s>
The	O
update	O
to	O
r7	O
introduces	O
a	O
(	O
Read	O
After	O
Write	O
)	O
data	B-Operating_System
dependency	I-Operating_System
.	O
</s>
<s>
With	O
a	O
superscalar	B-General_Concept
processor	I-General_Concept
,	O
the	O
instruction	B-General_Concept
window	I-General_Concept
of	O
the	O
processor	O
fills	O
up	O
with	O
a	O
number	O
of	O
instructions	O
(	O
known	O
as	O
the	O
issue	O
rate	O
)	O
.	O
</s>
<s>
Depending	O
on	O
the	O
scheme	O
that	O
the	O
superscalar	B-General_Concept
processor	I-General_Concept
uses	O
to	O
dispatch	O
these	O
instruction	O
from	O
the	O
window	O
to	O
the	O
execution	O
core	O
of	O
the	O
CPU	O
,	O
there	O
may	O
be	O
problems	O
if	O
there	O
is	O
a	O
dependency	O
not	O
unlike	O
the	O
one	O
shown	O
above	O
.	O
</s>
<s>
Consider	O
an	O
instruction	B-General_Concept
window	I-General_Concept
3	O
instructions	O
wide	O
,	O
containing	O
i1	O
,	O
i2	O
,	O
i3	O
(	O
instructions	O
1	O
,	O
2	O
&	O
3	O
)	O
.	O
</s>
<s>
Without	O
the	O
use	O
of	O
a	O
shelving	B-Operating_System
buffer	I-Operating_System
,	O
the	O
superscalar	B-General_Concept
processor	I-General_Concept
will	O
execute	O
i1	O
,	O
wait	O
until	O
i2	O
can	O
be	O
executed	O
and	O
then	O
execute	O
i2	O
and	O
i3	O
simultaneously	O
.	O
</s>
<s>
However	O
,	O
with	O
the	O
use	O
of	O
a	O
shelving	B-Operating_System
buffer	I-Operating_System
,	O
the	O
instruction	B-General_Concept
window	I-General_Concept
will	O
be	O
emptied	O
into	O
shelving	B-Operating_System
buffers	I-Operating_System
regardless	O
of	O
contents	O
.	O
</s>
<s>
The	O
processor	O
will	O
then	O
search	O
for	O
an	O
appropriate	O
number	O
of	O
instructions	O
in	O
the	O
shelving	B-Operating_System
buffers	I-Operating_System
that	O
can	O
be	O
executed	O
in	O
parallel	O
(	O
i.e.	O
</s>
