<s>
In	O
computing	O
,	O
serial	B-General_Concept
presence	I-General_Concept
detect	I-General_Concept
(	O
SPD	O
)	O
is	O
a	O
standardized	O
way	O
to	O
automatically	O
access	O
information	O
about	O
a	O
memory	B-General_Concept
module	I-General_Concept
.	O
</s>
<s>
Earlier	O
72-pin	O
SIMMs	B-General_Concept
included	O
five	O
pins	O
that	O
provided	O
five	O
bits	O
of	O
parallel	O
presence	B-General_Concept
detect	I-General_Concept
(	O
PPD	O
)	O
data	O
,	O
but	O
the	O
168-pin	O
DIMM	B-General_Concept
standard	O
changed	O
to	O
a	O
serial	B-General_Concept
presence	I-General_Concept
detect	I-General_Concept
to	O
encode	O
much	O
more	O
information	O
.	O
</s>
<s>
When	O
an	O
ordinary	O
modern	O
computer	O
is	O
turned	O
on	O
,	O
it	O
starts	O
by	O
doing	O
a	O
power-on	B-Device
self-test	I-Device
(	O
POST	O
)	O
.	O
</s>
<s>
SPD	O
is	O
a	O
memory	O
hardware	O
feature	O
that	O
makes	O
it	O
possible	O
for	O
the	O
computer	O
to	O
know	O
what	O
memory	O
is	O
present	O
,	O
and	O
what	O
memory	B-General_Concept
timings	I-General_Concept
to	O
use	O
to	O
access	O
the	O
memory	O
.	O
</s>
<s>
In	O
most	O
cases	O
,	O
there	O
is	O
a	O
special	O
optional	O
procedure	O
for	O
accessing	O
BIOS	B-Operating_System
parameters	O
,	O
to	O
view	O
and	O
potentially	O
make	O
changes	O
in	O
settings	O
.	O
</s>
<s>
It	O
may	O
be	O
possible	O
to	O
control	O
how	O
the	O
computer	O
uses	O
the	O
memory	O
SPD	O
data	O
—	O
to	O
choose	O
settings	O
,	O
selectively	O
modify	O
memory	B-General_Concept
timings	I-General_Concept
,	O
or	O
possibly	O
to	O
completely	O
override	O
the	O
SPD	O
data	O
(	O
see	O
overclocking	B-Application
)	O
.	O
</s>
<s>
For	O
a	O
memory	B-General_Concept
module	I-General_Concept
to	O
support	O
SPD	O
,	O
the	O
JEDEC	O
standards	O
require	O
that	O
certain	O
parameters	O
be	O
in	O
the	O
lower	O
128	O
bytes	O
of	O
an	O
EEPROM	B-General_Concept
located	O
on	O
the	O
memory	B-General_Concept
module	I-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
the	O
SPD	O
data	O
on	O
an	O
SDRAM	O
module	O
might	O
provide	O
information	O
about	O
the	O
CAS	B-Architecture
latency	I-Architecture
so	O
the	O
system	O
can	O
set	O
this	O
correctly	O
without	O
user	O
intervention	O
.	O
</s>
<s>
The	O
SPD	O
EEPROM	B-General_Concept
firmware	O
is	O
accessed	O
using	O
SMBus	B-Algorithm
,	O
a	O
variant	O
of	O
the	O
I²C	O
protocol	O
.	O
</s>
<s>
The	O
EEPROM	B-General_Concept
shares	O
ground	O
pins	O
with	O
the	O
RAM	O
,	O
has	O
its	O
own	O
power	O
pin	O
,	O
and	O
has	O
three	O
additional	O
pins	O
(	O
SA0	O
–	O
2	O
)	O
to	O
identify	O
the	O
slot	O
,	O
which	O
are	O
used	O
to	O
assign	O
the	O
EEPROM	B-General_Concept
a	O
unique	O
address	O
in	O
the	O
range	O
0x50	O
–	O
0x57	O
.	O
</s>
<s>
Not	O
only	O
can	O
the	O
communication	O
lines	O
be	O
shared	O
among	O
8	O
memory	B-General_Concept
modules	I-General_Concept
,	O
the	O
same	O
SMBus	B-Algorithm
is	O
commonly	O
used	O
on	O
motherboards	O
for	O
system	O
health	O
monitoring	O
tasks	O
such	O
as	O
reading	O
power	O
supply	O
voltages	O
,	O
CPU	B-General_Concept
temperatures	O
,	O
and	O
fan	O
speeds	O
.	O
</s>
<s>
SPD	O
EEPROMs	B-General_Concept
also	O
respond	O
to	O
I²C	O
addresses	O
0x30	O
–	O
0x37	O
if	O
they	O
have	O
not	O
been	O
write	O
protected	O
,	O
and	O
an	O
extension	O
(	O
TSE	O
series	O
)	O
uses	O
addresses	O
0x18	O
–	O
0x1F	O
to	O
access	O
an	O
optional	O
on-chip	O
temperature	O
sensor	O
.	O
</s>
<s>
Before	O
SPD	O
,	O
memory	O
chips	O
were	O
spotted	O
with	O
parallel	O
presence	B-General_Concept
detect	I-General_Concept
(	O
PPD	O
)	O
.	O
</s>
<s>
PPD	O
used	O
a	O
separate	O
pin	O
for	O
each	O
bit	O
of	O
information	O
,	O
which	O
meant	O
that	O
only	O
the	O
speed	O
and	O
density	O
of	O
the	O
memory	B-General_Concept
module	I-General_Concept
could	O
be	O
stored	O
because	O
of	O
the	O
limited	O
space	O
for	O
pins	O
.	O
</s>
<s>
The	O
SPD	O
ROM	O
defines	O
up	O
to	O
three	O
DRAM	O
timings	O
,	O
for	O
three	O
CAS	B-Architecture
latencies	I-Architecture
specified	O
by	O
set	O
bits	O
in	O
byte	O
18	O
.	O
</s>
<s>
First	O
comes	O
the	O
highest	O
CAS	B-Architecture
latency	I-Architecture
(	O
fastest	O
clock	O
)	O
,	O
then	O
two	O
lower	O
CAS	B-Architecture
latencies	I-Architecture
with	O
progressively	O
lower	O
clock	O
speeds	O
.	O
</s>
<s>
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
0	O
0x00	O
Number	O
of	O
bytes	O
present	O
Typically	O
128	O
1	O
0x01	O
log2(size of SPD EEPROM )	O
Typically	O
8	O
(	O
256	O
bytes	O
)	O
2	O
0x02	O
Basic	O
memory	O
type	O
(	O
4	O
:	O
SPD	O
SDRAM	O
)	O
3	O
0x03	O
Bank	O
2	O
row	O
address	O
bits	O
(	O
0	O
–	O
15	O
)	O
Bank	O
1	O
row	O
address	O
bits	O
(	O
1	O
–	O
15	O
)	O
Bank	O
2	O
is	O
0	O
if	O
same	O
as	O
bank	O
1	O
4	O
0x04	O
Bank	O
2	O
column	O
address	O
bits	O
(	O
0	O
–	O
15	O
)	O
Bank	O
1	O
column	O
address	O
bits	O
(	O
1	O
–	O
15	O
)	O
Bank	O
2	O
is	O
0	O
if	O
same	O
as	O
bank	O
1	O
5	O
0x05	O
Number	O
of	O
RAM	O
banks	O
on	O
module	O
(	O
1	O
–	O
255	O
)	O
Commonly	O
1	O
or	O
2	O
6	O
0x06	O
Module	O
data	O
width	O
low	O
byte	O
Commonly	O
64	O
,	O
or	O
72	O
for	O
ECC	O
DIMMs	B-General_Concept
7	O
0x07	O
Module	O
data	O
width	O
high	O
byte	O
0	O
,	O
unless	O
width	O
≥	O
256	O
bits	O
8	O
0x08	O
Interface	O
voltage	O
level	O
of	O
this	O
assembly	O
(	O
not	O
the	O
same	O
as	O
Vcc	O
supply	O
voltage	O
)	O
(	O
0	O
–	O
4	O
)	O
Decoded	O
by	O
table	O
lookup	O
9	O
0x09	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
highest	O
CAS	B-Architecture
latency	I-Architecture
10	O
0x0a	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
SDRAM	O
access	O
time	O
from	O
clock	O
(	O
tAC	O
)	O
11	O
0x0b	O
DIMM	B-General_Concept
configuration	O
type	O
(	O
0	O
–	O
2	O
)	O
:	O
non-ECC	O
,	O
parity	O
,	O
ECC	O
Table	O
lookup	O
12	O
0x0c	O
Self	O
Refresh	O
period	O
(	O
0	O
–	O
5	O
)	O
:	O
64	O
,	O
256	O
,	O
128	O
,	O
32	O
,	O
16	O
,	O
8	O
kHz	O
Refresh	O
requirements	O
13	O
0x0d	O
Bank	O
2	O
2×	O
Bank	O
1	O
primary	O
SDRAM	O
width	O
(	O
1	O
–	O
127	O
,	O
usually	O
8	O
)	O
Width	O
of	O
bank	O
1	O
data	O
SDRAM	O
devices	O
.	O
</s>
<s>
Memory	B-General_Concept
module	I-General_Concept
feature	O
bitmap	O
22	O
0x16	O
—	O
—	O
Upper	O
Vcc	O
(	O
supply	O
voltage	O
)	O
tolerance	O
Lower	O
Vcc	O
(	O
supply	O
voltage	O
)	O
tolerance	O
Write/1	O
read	O
burst	O
Precharge	O
all	O
Auto-precharge	O
Early	O
precharge	O
Memory	O
chip	O
feature	O
support	O
bitmap	O
23	O
0x17	O
Nanoseconds	O
(	O
4	O
–	O
18	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0	O
–	O
9	O
:	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
medium	O
CAS	B-Architecture
latency	I-Architecture
24	O
0x18	O
Nanoseconds	O
(	O
4	O
–	O
18	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0	O
–	O
9	O
:	O
0.0	O
–	O
0.9	O
)	O
Data	O
access	O
time	O
from	O
clock	O
(	O
tAC	O
)	O
25	O
0x19	O
Nanoseconds	O
(	O
1	O
–	O
63	O
)	O
0.25	O
ns	O
(	O
0	O
–	O
3	O
:	O
0.00	O
–	O
0.75	O
)	O
Clock	O
cycle	O
time	O
at	O
short	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
The	O
DDR	O
DIMM	B-General_Concept
SPD	O
format	O
is	O
an	O
extension	O
of	O
the	O
SDR	O
SDRAM	O
format	O
.	O
</s>
<s>
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
0	O
0x00	O
Number	O
of	O
bytes	O
written	O
Typically	O
128	O
1	O
0x01	O
log2(size of SPD EEPROM )	O
Typically	O
8	O
(	O
256	O
bytes	O
)	O
2	O
0x02	O
Basic	O
memory	O
type	O
(	O
7	O
=	O
DDR	O
SDRAM	O
)	O
3	O
0x03	O
Bank	O
2	O
row	O
address	O
bits	O
(	O
0	O
–	O
15	O
)	O
Bank	O
1	O
row	O
address	O
bits	O
(	O
1	O
–	O
15	O
)	O
Bank	O
2	O
is	O
0	O
if	O
same	O
as	O
bank	O
1	O
.	O
</s>
<s>
5	O
0x05	O
Number	O
of	O
RAM	O
banks	O
on	O
module	O
(	O
1	O
–	O
255	O
)	O
Commonly	O
1	O
or	O
2	O
6	O
0x06	O
Module	O
data	O
width	O
low	O
byte	O
Commonly	O
64	O
,	O
or	O
72	O
for	O
ECC	O
DIMMs	B-General_Concept
7	O
0x07	O
Module	O
data	O
width	O
high	O
byte	O
0	O
,	O
unless	O
width	O
≥	O
256	O
bits	O
8	O
0x08	O
Interface	O
voltage	O
level	O
of	O
this	O
assembly	O
(	O
not	O
the	O
same	O
as	O
Vcc	O
supply	O
voltage	O
)	O
(	O
0	O
–	O
5	O
)	O
Decoded	O
by	O
table	O
lookup	O
9	O
0x09	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
highest	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
10	O
0x0a	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Hundredths	O
of	O
nanoseconds	O
(	O
0.00	O
–	O
0.09	O
)	O
SDRAM	O
access	O
time	O
from	O
clock	O
(	O
tAC	O
)	O
11	O
0x0b	O
DIMM	B-General_Concept
configuration	O
type	O
(	O
0	O
–	O
2	O
)	O
:	O
non-ECC	O
,	O
parity	O
,	O
ECC	O
Table	O
lookup	O
12	O
0x0c	O
Self	O
Refresh	O
period	O
(	O
0	O
–	O
5	O
)	O
:	O
64	O
,	O
256	O
,	O
128	O
,	O
32	O
,	O
16	O
,	O
8	O
kHz	O
Refresh	O
requirements	O
13	O
0x0d	O
Bank	O
2	O
2×	O
Bank	O
1	O
primary	O
SDRAM	O
width	O
(	O
1	O
–	O
127	O
)	O
Width	O
of	O
bank	O
1	O
data	O
SDRAM	O
devices	O
.	O
</s>
<s>
15	O
0x0f	O
Clock	O
delay	O
for	O
random	O
column	O
reads	O
Typically	O
1	O
16	O
0x10	O
Page	O
—	O
—	O
—	O
8	O
4	O
2	O
1	O
Burst	O
lengths	O
supported	O
(	O
bitmap	O
)	O
17	O
0x11	O
Banks	O
per	O
SDRAM	O
device	O
(	O
1	O
–	O
255	O
)	O
Typically	O
4	O
18	O
0x12	O
—	O
4	O
3.5	O
3	O
2.5	O
2	O
1.5	O
1	O
latencies	O
supported	O
(	O
bitmap	O
)	O
19	O
0x13	O
—	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
latencies	O
supported	O
(	O
bitmap	O
)	O
20	O
0x14	O
—	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
latencies	O
supported	O
(	O
bitmap	O
)	O
21	O
0x15	O
—	O
x	O
Diff	O
clock	O
FET	O
switch	O
external	O
enable	O
FET	O
switch	O
on-board	O
enable	O
On-card	O
PLL	O
Registered	O
Buffered	O
Memory	B-General_Concept
module	I-General_Concept
feature	O
bitmap	O
22	O
0x16	O
Fast	O
AP	O
Concurrent	O
auto	O
precharge	O
Upper	O
Vcc	O
(	O
supply	O
voltage	O
)	O
tolerance	O
Lower	O
Vcc	O
(	O
supply	O
voltage	O
)	O
tolerance	O
—	O
—	O
—	O
Includes	O
weak	O
driver	O
Memory	O
chip	O
feature	O
bitmap	O
23	O
0x17	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
medium	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
24	O
0x18	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Hundredths	O
of	O
nanoseconds	O
(	O
0.00	O
–	O
0.09	O
)	O
Data	O
access	O
time	O
from	O
clock	O
(	O
tAC	O
)	O
25	O
0x19	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
short	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
45	O
0x2d	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
1.2	O
)	O
Hundredths	O
of	O
nanoseconds	O
(	O
0.00	O
–	O
0.09	O
)	O
Read	O
data	O
hold	O
skew	O
factor	O
(	O
tQHS	O
)	O
46	O
0x2ecolspan	O
=	O
8	O
For	O
future	O
standardization	O
47	O
0x2f	O
—	O
Height	O
Height	O
of	O
DIMM	B-General_Concept
module	O
,	O
table	O
lookup	O
48	O
–	O
61	O
0x30	O
–	O
0x3dcolspan	O
=	O
8	O
For	O
future	O
standardization	O
62	O
0x3e	O
Major	O
revision	O
(	O
0	O
–	O
9	O
)	O
Minor	O
revision	O
(	O
0	O
–	O
9	O
)	O
SPD	O
revision	O
level	O
,	O
0.0	O
or	O
1.0	O
63	O
0x3f	O
Checksum	O
Sum	O
of	O
bytes	O
0	O
–	O
62	O
,	O
not	O
then	O
negated	O
64	O
–	O
71	O
0x40	O
–	O
47	O
Manufacturer	O
JEDEC	O
id	O
.	O
</s>
<s>
One	O
notable	O
deletion	O
is	O
the	O
confusing	O
and	O
little-used	O
support	O
for	O
DIMMs	B-General_Concept
with	O
two	O
ranks	O
of	O
different	O
sizes	O
.	O
</s>
<s>
+	O
SPD	O
contents	O
for	O
DDR2	O
SDRAM	O
Byte	O
Bit	O
Notes	O
Dec	O
Hex	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
0	O
0x00	O
Number	O
of	O
bytes	O
written	O
Typically	O
128	O
1	O
0x01	O
log2(size of SPD EEPROM )	O
Typically	O
8	O
(	O
256	O
bytes	O
)	O
2	O
0x02	O
Basic	O
memory	O
type	O
(	O
8	O
=	O
DDR2	O
SDRAM	O
)	O
3	O
0x03	O
colspan	O
=	O
4	O
Row	O
address	O
bits	O
(	O
1	O
–	O
15	O
)	O
4	O
0x04	O
colspan	O
=	O
4	O
Column	O
address	O
bits	O
(	O
1	O
–	O
15	O
)	O
5	O
0x05	O
Vertical	O
height	O
Stack	O
?	O
</s>
<s>
Ranks−1	O
(	O
1	O
–	O
8	O
)	O
Commonly	O
0	O
or	O
1	O
,	O
meaning	O
1	O
or	O
2	O
6	O
0x06	O
Module	O
data	O
width	O
Commonly	O
64	O
,	O
or	O
72	O
for	O
ECC	O
DIMMs	B-General_Concept
7	O
0x07	O
colspan	O
=	O
8	O
8	O
0x08	O
Interface	O
voltage	O
level	O
of	O
this	O
assembly	O
(	O
not	O
the	O
same	O
as	O
Vcc	O
supply	O
voltage	O
)	O
(	O
0	O
–	O
5	O
)	O
Decoded	O
by	O
table	O
lookup.Commonly	O
5	O
=	O
SSTL	O
1.8	O
V	O
9	O
0x09	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
highest	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
10	O
0x0a	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Hundredths	O
of	O
nanoseconds	O
(	O
0.00	O
–	O
0.09	O
)	O
SDRAM	O
access	O
time	O
from	O
clock	O
(	O
tAC	O
)	O
11	O
0x0b	O
DIMM	B-General_Concept
configuration	O
type	O
(	O
0	O
–	O
2	O
)	O
:	O
non-ECC	O
,	O
parity	O
,	O
ECC	O
Table	O
lookup	O
12	O
0x0c	O
Self	O
Refresh	O
period	O
(	O
0	O
–	O
5	O
)	O
:	O
64	O
,	O
256	O
,	O
128	O
,	O
32	O
,	O
16	O
,	O
8	O
kHz	O
Refresh	O
requirements	O
13	O
0x0d	O
Primary	O
SDRAM	O
width	O
(	O
1	O
–	O
255	O
)	O
Commonly	O
8	O
(	O
module	O
built	O
from	O
×8	O
parts	O
)	O
or	O
16	O
14	O
0x0e	O
ECC	O
SDRAM	O
width	O
(	O
0	O
–	O
255	O
)	O
Width	O
of	O
bank	O
ECC/parity	O
SDRAM	O
devices	O
.	O
</s>
<s>
15	O
0x0f	O
colspan	O
=	O
8	O
16	O
0x10	O
—	O
—	O
—	O
—	O
8	O
4	O
—	O
—	O
Burst	O
lengths	O
supported	O
(	O
bitmap	O
)	O
17	O
0x11	O
Banks	O
per	O
SDRAM	O
device	O
(	O
1	O
–	O
255	O
)	O
Typically	O
4	O
or	O
8	O
18	O
0x12	O
7	O
6	O
5	O
4	O
3	O
2	O
—	O
—	O
latencies	O
supported	O
(	O
bitmap	O
)	O
19	O
0x13	O
colspan	O
=	O
8	O
20	O
0x14	O
—	O
—	O
Mini-UDIMM	O
Mini-RDIMM	O
Micro-DIMM	B-General_Concept
SO-DIMM	O
UDIMM	O
RDIMM	O
DIMM	B-General_Concept
type	O
of	O
this	O
assembly	O
(	O
bitmap	O
)	O
21	O
0x15	O
—	O
Module	O
is	O
analysis	O
probe	O
—	O
FET	O
switch	O
external	O
enable	O
—	O
—	O
—	O
—	O
Memory	B-General_Concept
module	I-General_Concept
feature	O
bitmap	O
22	O
0x16	O
—	O
—	O
—	O
—	O
—	O
—	O
—	O
Includes	O
weak	O
driver	O
Memory	O
chip	O
feature	O
bitmap	O
23	O
0x17	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
medium	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
24	O
0x18	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Hundredths	O
of	O
nanoseconds	O
(	O
0.00	O
–	O
0.09	O
)	O
Data	O
access	O
time	O
from	O
clock	O
(	O
tAC	O
)	O
25	O
0x19	O
Nanoseconds	O
(	O
0	O
–	O
15	O
)	O
Tenths	O
of	O
nanoseconds	O
(	O
0.0	O
–	O
0.9	O
)	O
Clock	O
cycle	O
time	O
at	O
short	O
CAS	B-Architecture
latency	I-Architecture
.	O
</s>
<s>
Further	O
,	O
the	O
practice	O
of	O
specifying	O
different	O
time	O
values	O
depending	O
on	O
the	O
CAS	B-Architecture
latency	I-Architecture
has	O
been	O
dropped	O
;	O
now	O
there	O
are	O
just	O
a	O
single	O
set	O
of	O
timing	O
parameters	O
.	O
</s>
<s>
+	O
SPD	O
contents	O
for	O
DDR3	O
SDRAMJESD21-C	O
Annex	O
K	O
:	O
Serial	B-General_Concept
Presence	I-General_Concept
Detect	I-General_Concept
for	O
DDR3	O
SDRAM	O
Modules	O
,	O
Release	O
4	O
,	O
SPD	O
Revision	O
1.1JESD21-C	O
Annex	O
K	O
:	O
Serial	B-General_Concept
Presence	I-General_Concept
Detect	I-General_Concept
for	O
DDR3	O
SDRAM	O
Modules	O
,	O
Release	O
6	O
,	O
SPD	O
Revision	O
1.3	O
Byte	O
Bit	O
Notes	O
Dec	O
Hex	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
0	O
0x00	O
Exclude	O
serial	O
from	O
CRC	O
SPD	O
bytes	O
total	O
(	O
undef/256	O
)	O
SPD	O
bytes	O
used	O
(	O
undef/128/176/256	O
)	O
1	O
0x01	O
SPD	O
major	O
revision	O
SPD	O
minor	O
revision	O
1.0	O
,	O
1.1	O
,	O
1.2	O
or	O
1.3	O
2	O
0x02	O
Basic	O
memory	O
type	O
(	O
11	O
=	O
DDR3	O
SDRAM	O
)	O
Type	O
of	O
RAM	O
chips	O
3	O
0x03	O
colspan	O
=	O
4	O
Module	O
type	O
Type	O
of	O
module	O
;	O
e.g.	O
,	O
2	O
=	O
Unbuffered	O
DIMM	B-General_Concept
,	O
3	O
=	O
SO-DIMM	O
,	O
11	O
=	O
LRDIMM	O
4	O
0x04	O
Bank	O
address	O
bits−3	O
log2(bits per chip )	O
−28	O
Zero	O
means	O
8	O
banks	O
,	O
256	O
Mibit	O
.	O
</s>
<s>
7	O
0x07	O
colspan	O
=	O
2	O
ranks−1	O
log2( 	O
I/O	O
bits/chip	O
)	O
−2	O
Module	O
organization	O
8	O
0x08	O
colspan	O
=3	O
ECC	O
bits	O
(	O
001	O
=	O
8	O
)	O
log2(data bits )	O
−3	O
0x03	O
for	O
64-bit	O
,	O
non-ECC	O
DIMM	B-General_Concept
.	O
</s>
<s>
9	O
0x09	O
Dividend	O
,	O
picoseconds	O
(	O
1	O
–	O
15	O
)	O
Divisor	O
,	O
picoseconds	O
(	O
1	O
–	O
15	O
)	O
Fine	O
Time	O
Base	O
,	O
dividend/divisor	O
10	O
0x0a	O
Dividend	O
,	O
nanoseconds	O
(	O
1	O
–	O
255	O
)	O
Medium	O
Time	O
Base	O
,	O
dividend/divisor	O
;	O
commonly	O
1/8	O
11	O
0x0b	O
Divisor	O
,	O
nanoseconds	O
(	O
1	O
–	O
255	O
)	O
12	O
0x0c	O
Minimum	O
cycle	O
time	O
tCKmin	O
In	O
multiples	O
of	O
MTB	O
13	O
0x0d	O
colspan	O
=	O
8	O
14	O
0x0e	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
(	O
bitmap	O
)	O
15	O
0x0f	O
18	O
17	O
16	O
15	O
14	O
13	O
12	O
16	O
0x10	O
Minimum	O
CAS	B-Architecture
latency	I-Architecture
time	O
,	O
tAAmin	O
In	O
multiples	O
of	O
MTB	O
;	O
e.g.	O
,	O
80/8	O
ns	O
.	O
</s>
<s>
29	O
0x1d	O
Minimum	O
four	O
activate	O
window	O
delay	O
tFAWmin	O
,	O
bits	O
7:0	O
30	O
0x1e	O
DLL-off	O
colspan	O
=	O
5	O
RZQ/7	O
RZQ/6	O
SDRAM	O
optional	O
features	O
support	O
bitmap	O
31	O
0x1f	O
PASR	O
colspan	O
=3	O
ODTS	O
ASR	O
ETR	O
1×	O
ETR	O
(	O
95	O
°C	O
)	O
SDRAM	O
thermal	O
and	O
refresh	O
options	O
32	O
0x20	O
Present	O
Accuracy	O
(	O
TBD	O
;	O
currently	O
0	O
=	O
undefined	O
)	O
DIMM	B-General_Concept
thermal	O
sensor	O
present	O
?	O
</s>
<s>
41	O
0x29	O
Vendor	O
specific	O
tMAW	O
Maximum	O
Activate	O
Count	O
(	O
MAC	O
)	O
(	O
untested/700k/600k/.../200k/reserved/	O
∞	O
)	O
For	O
row	B-General_Concept
hammer	I-General_Concept
mitigation	O
42	O
–	O
59	O
0x2a	O
–	O
0x3b	O
colspan	O
=	O
8	O
For	O
future	O
standardization	O
.	O
</s>
<s>
The	O
DDR4	O
SDRAM	O
"	O
Annex	O
L	O
"	O
standard	O
for	O
SPD	O
changes	O
the	O
EEPROM	B-General_Concept
module	O
used	O
.	O
</s>
<s>
Instead	O
of	O
the	O
old	O
AT24C02-compatible	O
256-byte	O
EEPROMs	B-General_Concept
,	O
JEDEC	O
now	O
defines	O
a	O
new	O
nonstandard	O
EE1004	O
type	O
with	O
two	O
pages	O
at	O
the	O
SMBus	B-Algorithm
level	O
each	O
with	O
256	O
bytes	O
.	O
</s>
<s>
The	O
new	O
memory	O
still	O
uses	O
the	O
old	O
0x50	O
–	O
0x57	O
addresses	O
,	O
but	O
two	O
additional	O
address	O
at	O
0x36	O
(	O
SPA0	O
)	O
and	O
0x37	O
(	O
SPA1	O
)	O
are	O
now	O
used	O
to	O
receive	O
commands	O
to	O
select	O
the	O
currently-active	O
page	O
for	O
the	O
bus	O
,	O
a	O
form	O
of	O
bank	B-General_Concept
switching	I-General_Concept
.	O
</s>
<s>
Annex	O
L	O
defines	O
a	O
few	O
different	O
layouts	O
that	O
can	O
be	O
plugged	O
into	O
a	O
512-byte	O
(	O
of	O
which	O
a	O
maximum	O
of	O
320	O
bytes	O
are	O
defined	O
)	O
template	O
,	O
depending	O
on	O
the	O
type	O
of	O
the	O
memory	B-General_Concept
module	I-General_Concept
.	O
</s>
<s>
+	O
SPD	O
contents	O
for	O
DDR4	O
SDRAMJESD21-C	O
Annex	O
L	O
:	O
Serial	B-General_Concept
Presence	I-General_Concept
Detect	I-General_Concept
for	O
DDR4	O
SDRAM	O
Modules	O
,	O
Release	O
5	O
Byte	O
Bit	O
Notes	O
Dec	O
Hex	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
0	O
0x00	O
SPD	O
bytes	O
used	O
1	O
0x01	O
SPD	O
revision	O
n	O
Typically	O
0x10	O
,	O
0x11	O
,	O
0x12	O
2	O
0x02	O
Basic	O
memory	O
type	O
(	O
12	O
=	O
DDR4	O
SDRAM	O
)	O
Type	O
of	O
RAM	O
chips	O
3	O
0x03	O
colspan	O
=	O
4	O
Module	O
type	O
Type	O
of	O
module	O
;	O
e.g.	O
,	O
2	O
=	O
Unbuffered	O
DIMM	B-General_Concept
,	O
3	O
=	O
SO-DIMM	O
,	O
11	O
=	O
LRDIMM	O
4	O
0x04	O
Bank	O
group	O
bits	O
Bank	O
address	O
bits−2	O
Total	O
SDRAM	O
capacity	O
per	O
die	O
in	O
Gb	O
Zero	O
means	O
no	O
bank	O
groups	O
,	O
4	O
banks	O
,	O
256	O
Mibit	O
.	O
</s>
<s>
5	O
0x05	O
colspan	O
=	O
2	O
Row	O
address	O
bits−12	O
Column	O
address	O
bits−9	O
6	O
0x06	O
Primary	O
SDRAM	O
package	O
type	O
Die	O
count	O
colspan	O
=	O
2	O
Signal	O
loading	O
7	O
0x07	O
colspan	O
=	O
2	O
Maximum	O
activate	O
window	O
(	O
tMAW	O
)	O
Maximum	O
activate	O
count	O
(	O
MAC	O
)	O
SDRAM	O
optional	O
features	O
8	O
0x08	O
colspan	O
=	O
8	O
SDRAM	O
thermal	O
and	O
refresh	O
options	O
9	O
0x09	O
Post	O
package	O
repair	O
(	O
PPR	O
)	O
Soft	O
PPR	O
colspan	O
=	O
5	O
Other	O
SDRAM	O
optional	O
features	O
10	O
0x0a	O
SDRAM	O
package	O
type	O
Die	O
count−1	O
DRAM	O
density	O
ratio	O
Signal	O
loading	O
Secondary	O
SDRAM	O
package	O
type	O
11	O
0x0b	O
colspan	O
=	O
6	O
Endurant	O
flag	O
Operable	O
flag	O
Module	O
nominal	O
voltage	O
,	O
VDD	O
12	O
0x0c	O
Rank	O
mix	O
Package	O
ranks	O
per	O
DIMM−1	O
SDRAM	O
device	O
width	O
Module	O
organization	O
13	O
0x0d	O
colspan	O
=3	O
Bus	O
width	O
extensionPrimary	O
bus	O
widthModule	O
memory	O
bus	O
width	O
in	O
bits	O
14	O
0x0e	O
Thermal	O
sensor	O
colspan	O
=	O
7	O
Module	O
thermal	O
sensor	O
15	O
0x0f	O
colspan	O
=	O
4	O
Extended	O
base	O
module	O
type	O
16	O
0x10	O
colspan	O
=	O
8	O
17	O
0x11	O
colspan	O
=	O
4	O
Medium	O
timebase	O
(	O
MTB	O
)	O
Fine	O
timebase	O
(	O
FTB	O
)	O
Measured	O
in	O
ps	O
.	O
</s>
<s>
20	O
0x14	O
14	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
bit-mask	O
21	O
0x15	O
22	O
21	O
20	O
19	O
18	O
17	O
16	O
15	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
bit-mask	O
22	O
0x16	O
30	O
29	O
28	O
27	O
26	O
25	O
24	O
23	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
bit-mask	O
23	O
0x17	O
Low	O
CL	O
range	O
36	O
35	O
34	O
33	O
32	O
31	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
bit-mask	O
24	O
0x18	O
Minimum	O
CAS	B-Architecture
latency	I-Architecture
time	O
,	O
tAAmin	O
In	O
multiples	O
of	O
MTB	O
;	O
e.g.	O
,	O
1280/8	O
ns	O
.	O
</s>
<s>
However	O
,	O
a	O
256-byte	O
EEPROM	B-General_Concept
is	O
generally	O
provided	O
.	O
</s>
<s>
Enthusiasts	O
often	O
spend	O
considerable	O
time	O
manually	O
adjusting	O
the	O
memory	B-General_Concept
timings	I-General_Concept
for	O
higher	O
speed	O
.	O
</s>
<s>
The	O
EPP	O
information	O
is	O
stored	O
in	O
the	O
same	O
EEPROM	B-General_Concept
,	O
but	O
in	O
bytes	O
99	O
–	O
127	O
,	O
which	O
are	O
unused	O
by	O
standard	O
DDR2	O
SPD	O
.	O
</s>
<s>
The	O
parameters	O
are	O
particularly	O
designed	O
to	O
fit	O
the	O
memory	B-General_Concept
controller	I-General_Concept
on	O
the	O
nForce	B-Device
5	I-Device
,	O
nForce	B-Device
6	I-Device
and	O
nForce	B-Device
7	I-Device
chipsets	O
.	O
</s>
<s>
Nvidia	O
encourages	O
support	O
for	O
EPP	O
in	O
the	O
BIOS	B-Operating_System
for	O
its	O
high-end	O
motherboard	O
chipsets	O
.	O
</s>
<s>
This	O
is	O
intended	O
to	O
provide	O
"	O
one-click	O
overclocking	B-Application
"	O
to	O
get	O
better	O
performance	O
with	O
minimal	O
effort	O
.	O
</s>
<s>
The	O
term	O
"	O
SLI-ready-memory	O
"	O
has	O
caused	O
some	O
confusion	O
,	O
as	O
it	O
has	O
nothing	O
to	O
do	O
with	O
SLI	B-Device
video	I-Device
.	O
</s>
<s>
One	O
can	O
use	O
EPP/SLI	O
memory	O
with	O
a	O
single	O
video	O
card	O
(	O
even	O
a	O
non-Nvidia	O
card	O
)	O
,	O
and	O
one	O
can	O
run	O
a	O
multi-card	O
SLI	B-Device
video	I-Device
setup	O
without	O
EPP/SLI	O
memory	O
.	O
</s>
<s>
A	O
similar	O
,	O
Intel-developed	O
JEDEC	O
SPD	O
extension	O
was	O
developed	O
for	O
DDR3	O
SDRAM	O
DIMMs	B-General_Concept
,	O
later	O
used	O
in	O
DDR3	O
SDRAM	O
as	O
well	O
.	O
</s>
<s>
XMP	O
uses	O
bytes	O
176	O
–	O
255	O
,	O
which	O
are	O
unallocated	O
by	O
JEDEC	O
,	O
to	O
encode	O
higher-performance	O
memory	B-General_Concept
timings	I-General_Concept
.	O
</s>
<s>
Later	O
,	O
AMD	O
developed	O
AMP	O
,	O
an	O
equivalent	O
technology	O
to	O
XMP	O
,	O
for	O
use	O
in	O
its	O
"	O
Radeon	O
Memory	O
"	O
line	O
of	O
memory	B-General_Concept
modules	I-General_Concept
optimized	O
for	O
use	O
in	O
AMD	O
platforms	O
.	O
</s>
<s>
Also	O
included	O
in	O
the	O
header	O
is	O
the	O
number	O
of	O
DIMMs	B-General_Concept
per	O
memory	O
channel	O
that	O
the	O
profile	O
is	O
designed	O
to	O
support	O
;	O
including	O
more	O
DIMMs	B-General_Concept
may	O
not	O
work	O
well	O
.	O
</s>
<s>
+	O
XMP	O
Header	O
bytes	O
DDR3	O
Byte	O
Bits	O
Use	O
176	O
7:0	O
XMP	O
magic	O
number	O
byte	O
1	O
0x0C	O
177	O
7:0	O
XMP	O
magic	O
number	O
byte	O
2	O
0x4A	O
178	O
0	O
Profile	O
1	O
enabled	O
(	O
if	O
0	O
,	O
disabled	O
)	O
1	O
Profile	O
2	O
enabled	O
3:2	O
Profile	O
1	O
DIMMs	B-General_Concept
per	O
channel	O
(	O
1	O
–	O
4	O
encoded	O
as	O
0	O
–	O
3	O
)	O
5:4	O
Profile	O
2	O
DIMMs	B-General_Concept
per	O
channel	O
7:6	O
179	O
3:0	O
XMP	O
minor	O
version	O
number	O
(	O
x.0	O
or	O
x.1	O
)	O
7:4	O
XMP	O
major	O
version	O
number	O
(	O
0.x	O
or	O
1.x	O
)	O
180	O
7:0	O
Medium	O
timebase	O
dividend	O
for	O
profile	O
1	O
181	O
7:0	O
Medium	O
timebase	O
divisor	O
for	O
profile	O
1	O
(	O
MTB	O
=	O
dividend/divisor	O
ns	O
)	O
182	O
7:0	O
Medium	O
timebase	O
dividend	O
for	O
profile	O
2	O
(	O
e.g.	O
</s>
<s>
+	O
XMP	O
profile	O
bytes	O
DDR3	O
Byte	O
1	O
DDR3	O
Byte	O
2	O
Bits	O
Use	O
185	O
220	O
0	O
Module	O
Vdd	O
voltage	O
twentieths	O
(	O
0.00	O
or	O
0.05	O
)	O
4:1	O
Module	O
Vdd	O
voltage	O
tenths	O
(	O
0.0	O
–	O
0.9	O
)	O
6:5	O
Module	O
Vdd	O
voltage	O
units	O
(	O
0	O
–	O
2	O
)	O
7	O
186	O
221	O
7:0	O
Minimum	O
SDRAM	O
clock	O
period	O
tCKmin	O
(	O
MTB	O
units	O
)	O
187	O
222	O
7:0	O
Minimum	O
CAS	B-Architecture
latency	I-Architecture
time	O
tAAmin	O
(	O
MTB	O
units	O
)	O
188	O
223	O
7:0	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
(	O
bitmap	O
,	O
4	O
–	O
11	O
encoded	O
as	O
bits	O
0	O
–	O
7	O
)	O
189	O
224	O
6:0	O
CAS	B-Architecture
latencies	I-Architecture
supported	O
(	O
bitmap	O
,	O
12	O
–	O
18	O
encoded	O
as	O
bits	O
0	O
–	O
6	O
)	O
7	O
190	O
225	O
7:0	O
Minimum	O
CAS	O
write	O
latency	O
time	O
tCWLmin	O
(	O
MTB	O
units	O
)	O
191	O
226	O
7:0	O
Minimum	O
row	O
precharge	O
delay	O
time	O
tRPmin	O
(	O
MTB	O
units	O
)	O
192	O
227	O
7:0	O
Minimum	O
RAS	O
to	O
CAS	O
delay	O
time	O
tRCDmin	O
(	O
MTB	O
units	O
)	O
193	O
228	O
7:0	O
Minimum	O
write	O
recovery	O
time	O
tWRmin	O
(	O
MTB	O
units	O
)	O
194	O
229	O
3:0	O
tRASmin	O
upper	O
nibble	O
(	O
bits	O
11:8	O
)	O
7:4	O
tRCmin	O
upper	O
nibble	O
(	O
bits	O
11:8	O
)	O
195	O
230	O
7:0	O
Minimum	O
active	O
to	O
precharge	O
delay	O
time	O
tRASmin	O
bits	O
7:0	O
(	O
MTB	O
units	O
)	O
196	O
231	O
7:0	O
Minimum	O
active	O
to	O
active/refresh	O
delay	O
time	O
tRCmin	O
bits	O
7:0	O
(	O
MTB	O
units	O
)	O
197	O
232	O
7:0	O
Maximum	O
average	O
refresh	O
interval	O
tREFI	O
lsbyte	O
(	O
MTB	O
units	O
)	O
198	O
233	O
7:0	O
Maximum	O
average	O
refresh	O
interval	O
tREFI	O
msbyte	O
(	O
MTB	O
units	O
)	O
199	O
234	O
7:0	O
Minimum	O
refresh	O
recovery	O
delay	O
time	O
tRFCmin	O
lsbyte	O
(	O
MTB	O
units	O
)	O
200	O
235	O
7:0	O
Minimum	O
refresh	O
recovery	O
delay	O
time	O
tRFCmin	O
msbyte	O
(	O
MTB	O
units	O
)	O
201	O
236	O
7:0	O
Minimum	O
internal	O
read	O
to	O
precharge	O
command	O
delay	O
time	O
tRTPmin	O
(	O
MTB	O
units	O
)	O
202	O
237	O
7:0	O
Minimum	O
row	O
active	O
to	O
row	O
active	O
delay	O
time	O
tRRDmin	O
(	O
MTB	O
units	O
)	O
203	O
238	O
3:0	O
tFAWmin	O
upper	O
nibble	O
(	O
bits	O
11:8	O
)	O
7:4	O
204	O
239	O
7:0	O
Minimum	O
four	O
activate	O
window	O
delay	O
time	O
tFAWmin	O
bits	O
7:0	O
(	O
MTB	O
units	O
)	O
205	O
240	O
7:0	O
Minimum	O
internal	O
write	O
to	O
read	O
command	O
delay	O
time	O
tWTRmin	O
(	O
MTB	O
units	O
)	O
206	O
241	O
2:0	O
Write	O
to	O
read	O
command	O
turnaround	O
time	O
adjustment	O
(	O
0	O
–	O
7	O
clock	O
cycles	O
)	O
3	O
Write	O
to	O
read	O
command	O
turnaround	O
adjustment	O
sign	O
(	O
0	O
=	O
pull-in	O
,	O
1	O
=	O
push-out	O
)	O
6:4	O
Read	O
to	O
write	O
command	O
turnaround	O
time	O
adjustment	O
(	O
0	O
–	O
7	O
clock	O
cycles	O
)	O
7	O
Read	O
to	O
write	O
command	O
turnaround	O
adjustment	O
sign	O
(	O
0	O
=	O
pull-in	O
,	O
1	O
=	O
push-out	O
)	O
207	O
242	O
2:0	O
Back-to-back	O
command	O
turnaround	O
time	O
adjustment	O
(	O
0	O
–	O
7	O
clock	O
cycles	O
)	O
3	O
Back-to-back	O
turnaround	O
adjustment	O
sign	O
(	O
0	O
=	O
pull-in	O
,	O
1	O
=	O
push-out	O
)	O
7:4	O
208	O
243	O
7:0	O
System	O
CMD	O
rate	O
mode	O
.	O
</s>
<s>
AMD	O
's	O
Extended	O
Profiles	O
for	O
Overclocking	B-Application
(	O
EXPO	O
)	O
is	O
a	O
JEDEC	O
SPD	O
extension	O
developed	O
for	O
DDR5	O
DIMMs	B-General_Concept
to	O
apply	O
a	O
one-click	O
automatic	O
overclocking	B-Application
profile	O
to	O
system	O
memory	O
.	O
</s>
<s>
AMD	O
EXPO-certified	O
DIMMs	B-General_Concept
include	O
optimised	O
timings	O
that	O
optimise	O
the	O
performance	O
of	O
its	O
Zen	O
4	O
processors	O
.	O
</s>
<s>
A	O
common	O
misuse	O
is	O
to	O
write	O
information	O
to	O
certain	O
memory	O
regions	O
to	O
bind	O
vendor-specific	O
memory	B-General_Concept
modules	I-General_Concept
to	O
a	O
specific	O
system	O
.	O
</s>
<s>
Adding	O
different	O
memory	B-General_Concept
module	I-General_Concept
to	O
the	O
system	O
usually	O
results	O
in	O
a	O
refusal	O
or	O
other	O
counter-measures	O
(	O
like	O
pressing	O
F1	O
on	O
every	O
boot	O
)	O
.	O
</s>
<s>
This	O
is	O
the	O
output	O
of	O
a	O
512MB	O
memory	B-General_Concept
module	I-General_Concept
from	O
Micron	O
Technologies	O
,	O
branded	O
for	O
Fujitsu-Siemens	O
Computers	O
,	O
note	O
the	O
"	O
FSC	O
"	O
string	O
.	O
</s>
<s>
The	O
system	B-Operating_System
BIOS	I-Operating_System
rejects	O
memory	B-General_Concept
modules	I-General_Concept
that	O
do	O
n't	O
have	O
this	O
information	O
starting	O
at	O
offset	O
128h	O
.	O
</s>
<s>
Incidentally	O
this	O
can	O
also	O
be	O
a	O
symptom	O
of	O
BIOS	B-Operating_System
corruption	O
as	O
well	O
.	O
</s>
<s>
Memory	B-General_Concept
module	I-General_Concept
manufacturers	O
write	O
the	O
SPD	O
information	O
to	O
the	O
EEPROM	B-General_Concept
on	O
the	O
module	O
.	O
</s>
<s>
Motherboard	O
BIOSes	O
read	O
the	O
SPD	O
information	O
to	O
configure	O
the	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
program	O
that	O
can	O
decode	O
information	O
about	O
memory	O
(	O
and	O
other	O
things	O
)	O
and	O
runs	O
on	O
Linux	B-Application
,	O
FreeBSD	B-Operating_System
,	O
NetBSD	B-Device
,	O
OpenBSD	B-Operating_System
,	O
BeOS	B-Application
,	O
Cygwin	B-Language
and	O
Solaris	B-Application
.	O
</s>
<s>
On	O
Linux	B-Application
systems	O
and	O
FreeBSD	B-Operating_System
,	O
the	O
user	B-Operating_System
space	I-Operating_System
program	O
decode-dimms	O
provided	O
by	O
i2c-tools	O
decodes	O
and	O
prints	O
information	O
on	O
any	O
memory	O
with	O
SPD	O
information	O
in	O
the	O
computer	O
.	O
</s>
<s>
It	O
requires	O
SMBus	B-Algorithm
controller	O
support	O
in	O
the	O
kernel	O
,	O
the	O
EEPROM	B-General_Concept
kernel	O
driver	O
,	O
and	O
also	O
that	O
the	O
SPD	O
EEPROMs	B-General_Concept
are	O
connected	O
to	O
the	O
SMBus	B-Algorithm
.	O
</s>
<s>
On	O
older	O
Linux	B-Application
distributions	O
,	O
decode-dimms.pl	O
was	O
available	O
as	O
part	O
of	O
lm_sensors	O
.	O
</s>
<s>
OpenBSD	B-Operating_System
has	O
included	O
a	O
driver	O
(	O
)	O
since	O
version	O
4.3	O
to	O
provide	O
information	O
about	O
memory	B-General_Concept
modules	I-General_Concept
.	O
</s>
<s>
The	O
driver	O
was	O
ported	O
from	O
NetBSD	B-Device
,	O
where	O
it	O
is	O
available	O
since	O
release	O
5.0	O
.	O
</s>
<s>
Coreboot	B-Device
reads	O
and	O
uses	O
SPD	O
information	O
to	O
initialize	O
all	O
memory	B-General_Concept
controllers	I-General_Concept
in	O
a	O
computer	O
with	O
timing	O
,	O
size	O
and	O
other	O
properties	O
.	O
</s>
<s>
Windows	B-Application
systems	O
use	O
programs	O
like	O
HWiNFO	O
,	O
CPU-Z	B-Application
and	O
Speccy	B-Application
,	O
which	O
can	O
read	O
and	O
display	O
DRAM	O
module	O
information	O
from	O
SPD	O
.	O
</s>
<s>
Chipset-independent	O
reading	O
and	O
writing	O
of	O
SPD	O
information	O
is	O
done	O
by	O
accessing	O
the	O
memory	O
's	O
EEPROM	B-General_Concept
directly	O
with	O
eeprom	B-General_Concept
programmer	O
hardware	O
and	O
software	O
.	O
</s>
<s>
A	O
not	O
so	O
common	O
use	O
for	O
old	O
laptops	O
is	O
as	O
generic	O
SMBus	B-Algorithm
readers	O
,	O
as	O
the	O
internal	O
EEPROM	B-General_Concept
on	O
the	O
module	O
can	O
be	O
disabled	O
once	O
the	O
BIOS	B-Operating_System
has	O
read	O
it	O
so	O
the	O
bus	O
is	O
essentially	O
available	O
for	O
use	O
.	O
</s>
<s>
The	O
method	O
used	O
is	O
to	O
pull	O
low	O
the	O
A0	O
,	O
A1	O
lines	O
so	O
the	O
internal	O
memory	O
shuts	O
down	O
,	O
allowing	O
the	O
external	O
device	O
to	O
access	O
the	O
SMBus	B-Algorithm
.	O
</s>
<s>
Once	O
this	O
is	O
done	O
,	O
a	O
custom	O
Linux	B-Application
build	O
or	O
DOS	O
application	O
can	O
then	O
access	O
the	O
external	O
device	O
.	O
</s>
<s>
On	O
some	O
chipsets	O
the	O
message	O
"	O
Incompatible	O
SMBus	B-Algorithm
driver	O
?	O
"	O
</s>
<s>
Some	O
memory	B-General_Concept
modules	I-General_Concept
(	O
especially	O
on	O
Gaming	B-Device
PCs	I-Device
)	O
support	O
RGB	O
LEDs	O
that	O
are	O
controlled	O
by	O
proprietary	O
SMBus	B-Algorithm
commands	O
.	O
</s>
<s>
Some	O
older	O
equipment	O
require	O
the	O
use	O
of	O
SIMMs	B-General_Concept
with	O
parallel	O
presence	B-General_Concept
detect	I-General_Concept
(	O
more	O
commonly	O
called	O
simply	O
presence	B-General_Concept
detect	I-General_Concept
or	O
PD	O
)	O
.	O
</s>
