<s>
The	O
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
(	O
SPI	O
)	O
is	O
a	O
synchronous	B-Application
serial	B-Protocol
communication	I-Protocol
interface	O
specification	O
used	O
for	O
short-distance	O
communication	O
,	O
primarily	O
in	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Typical	O
applications	O
include	O
Secure	B-Device
Digital	I-Device
cards	I-Device
and	O
liquid	B-Device
crystal	I-Device
displays	I-Device
.	O
</s>
<s>
SPI	O
devices	O
communicate	O
in	O
full	O
duplex	O
mode	O
using	O
a	O
master	B-Operating_System
–	I-Operating_System
slave	I-Operating_System
architecture	O
usually	O
with	O
a	O
single	O
master	O
(	O
though	O
some	O
Atmel	O
and	O
Silabs	O
devices	O
support	O
changing	O
roles	O
on	O
the	O
fly	O
depending	O
on	O
an	O
external	O
(	O
SS	O
)	O
pin	O
)	O
.	O
</s>
<s>
The	O
master	O
(	O
controller	O
)	O
device	O
originates	O
the	O
frame	B-Protocol
for	O
reading	O
and	O
writing	O
.	O
</s>
<s>
Multiple	O
slave-devices	O
may	O
be	O
supported	O
through	O
selection	O
with	O
individual	O
chip	B-Architecture
select	I-Architecture
(	O
CS	B-Language
)	O
,	O
sometimes	O
called	O
slave	B-Architecture
select	I-Architecture
(	O
SS	O
)	O
lines	O
.	O
</s>
<s>
Sometimes	O
SPI	O
is	O
called	O
a	O
four-wire	O
serial	B-Protocol
bus	B-General_Concept
,	O
contrasting	O
with	O
three-	O
,	O
two-	O
,	O
and	O
one-wire	O
serial	B-Protocol
buses	O
.	O
</s>
<s>
The	O
SPI	O
may	O
be	O
accurately	O
described	O
as	O
a	O
synchronous	B-Protocol
serial	I-Protocol
interface	I-Protocol
,	O
but	O
it	O
is	O
different	O
from	O
the	O
Synchronous	B-Protocol
Serial	I-Protocol
Interface	I-Protocol
(	O
SSI	O
)	O
protocol	O
,	O
which	O
is	O
also	O
a	O
four-wire	O
synchronous	B-Application
serial	B-Protocol
communication	I-Protocol
protocol	O
.	O
</s>
<s>
The	O
SPI	B-Architecture
bus	I-Architecture
specifies	O
four	O
logic	O
signals	O
:	O
</s>
<s>
MOSI	B-Architecture
on	O
a	O
master	O
connects	O
to	O
MOSI	B-Architecture
on	O
a	O
slave	O
.	O
</s>
<s>
MISO	B-Architecture
on	O
a	O
master	O
connects	O
to	O
MISO	B-Architecture
on	O
a	O
slave	O
.	O
</s>
<s>
Slave	B-Architecture
Select	I-Architecture
has	O
the	O
same	O
functionality	O
as	O
chip	B-Architecture
select	I-Architecture
and	O
is	O
used	O
instead	O
of	O
an	O
addressing	O
concept	O
.	O
</s>
<s>
The	O
signal	O
names	O
above	O
can	B-Protocol
be	O
used	O
to	O
label	O
both	O
the	O
master	O
and	O
slave	O
device	O
pins	O
as	O
well	O
as	O
the	O
signal	O
lines	O
between	O
them	O
in	O
an	O
unambiguous	O
way	O
,	O
and	O
are	O
the	O
most	O
common	O
in	O
modern	O
products	O
.	O
</s>
<s>
"	O
Chip	B-Architecture
Select	I-Architecture
"	O
,	O
not	O
"	O
chip	B-Architecture
select	I-Architecture
"	O
)	O
.	O
</s>
<s>
Many	O
products	O
can	B-Protocol
have	O
nonstandard	O
SPI	O
pin	O
names	O
:	O
</s>
<s>
Serial	B-Protocol
Clock	O
:	O
</s>
<s>
Master	O
Output	O
→	O
Slave	O
Input	O
(	O
MOSI	B-Architecture
)	O
:	O
</s>
<s>
Master	O
Input	O
←	O
Slave	O
Output	O
(	O
MISO	B-Architecture
)	O
:	O
</s>
<s>
Slave	B-Architecture
Select	I-Architecture
:	O
</s>
<s>
The	O
SPI	B-Architecture
bus	I-Architecture
can	B-Protocol
operate	O
with	O
a	O
single	O
master	O
device	O
and	O
with	O
one	O
or	O
more	O
slave	O
devices	O
.	O
</s>
<s>
Some	O
slaves	O
require	O
a	O
falling	O
edge	O
of	O
the	O
chip	B-Architecture
select	I-Architecture
signal	O
to	O
initiate	O
an	O
action	O
.	O
</s>
<s>
Most	O
slave	O
devices	O
have	O
tri-state	O
outputs	O
so	O
their	O
MISO	B-Architecture
signal	O
becomes	O
high	O
impedance	O
(	O
electrically	O
disconnected	O
)	O
when	O
the	O
device	O
is	O
not	O
selected	O
.	O
</s>
<s>
Devices	O
without	O
tri-state	O
outputs	O
cannot	O
share	O
SPI	B-Architecture
bus	I-Architecture
segments	O
with	O
other	O
devices	O
without	O
using	O
an	O
external	O
tri-state	O
buffer	O
.	O
</s>
<s>
To	O
begin	O
communication	O
,	O
the	O
bus	B-General_Concept
master	O
configures	O
the	O
clock	O
,	O
using	O
a	O
frequency	O
supported	O
by	O
the	O
slave	O
device	O
,	O
typically	O
up	O
to	O
a	O
few	O
MHz	O
.	O
</s>
<s>
The	O
master	O
sends	O
a	O
bit	O
on	O
the	O
MOSI	B-Architecture
line	O
and	O
the	O
slave	O
reads	O
it	O
,	O
while	O
the	O
slave	O
sends	O
a	O
bit	O
on	O
the	O
MISO	B-Architecture
line	O
and	O
the	O
master	O
reads	O
it	O
.	O
</s>
<s>
Transmissions	O
normally	O
involve	O
two	O
shift	B-General_Concept
registers	I-General_Concept
of	O
some	O
given	O
word-size	O
,	O
such	O
as	O
eight	O
bits	O
,	O
one	O
in	O
the	O
master	O
and	O
one	O
in	O
the	O
slave	O
;	O
they	O
are	O
connected	O
in	O
a	O
virtual	O
ring	O
topology	O
.	O
</s>
<s>
On	O
the	O
next	O
clock	O
edge	O
,	O
at	O
each	O
receiver	O
the	O
bit	O
is	O
sampled	O
from	O
the	O
transmission	O
line	O
and	O
set	O
as	O
a	O
new	O
least-significant	O
bit	O
of	O
the	O
shift	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
If	O
more	O
data	O
needs	O
to	O
be	O
exchanged	O
,	O
the	O
shift	B-General_Concept
registers	I-General_Concept
are	O
reloaded	O
and	O
the	O
process	O
repeats	O
.	O
</s>
<s>
However	O
,	O
other	O
word-sizes	O
are	O
also	O
common	O
,	O
for	O
example	O
,	O
sixteen-bit	O
words	O
for	O
touch-screen	O
controllers	O
or	O
audio	B-Algorithm
codecs	I-Algorithm
,	O
such	O
as	O
the	O
TSC2101	O
by	O
Texas	O
Instruments	O
,	O
or	O
twelve-bit	O
words	O
for	O
many	O
digital-to-analog	O
or	O
analog-to-digital	O
converters	O
.	O
</s>
<s>
Every	O
slave	O
on	O
the	O
bus	B-General_Concept
that	O
has	O
not	O
been	O
activated	O
using	O
its	O
chip	B-Architecture
select	I-Architecture
line	O
must	O
disregard	O
the	O
input	O
clock	O
and	O
MOSI	B-Architecture
signals	O
and	O
should	O
not	O
drive	O
MISO	B-Architecture
(	O
i.e.	O
,	O
must	O
have	O
a	O
tristate	B-Device
output	I-Device
)	O
although	O
some	O
devices	O
need	O
external	O
tristate	B-Device
buffers	I-Device
to	O
implement	O
this	O
.	O
</s>
<s>
Motorola	B-Architecture
SPI	I-Architecture
Block	O
Guide	O
names	O
these	O
two	O
options	O
as	O
CPOL	O
and	O
CPHA	O
(	O
for	O
clock	O
polarity	O
and	O
phase	O
)	O
respectively	O
,	O
a	O
convention	O
most	O
vendors	O
have	O
also	O
adopted	O
.	O
</s>
<s>
The	O
timing	B-Application
diagram	I-Application
is	O
shown	O
to	O
the	O
right	O
.	O
</s>
<s>
The	O
polarities	O
can	B-Protocol
be	O
converted	O
with	O
a	O
simple	O
inverter	O
.	O
</s>
<s>
For	O
the	O
first	O
cycle	O
,	O
the	O
first	O
bit	O
must	O
be	O
on	O
the	O
MOSI	B-Architecture
line	O
before	O
the	O
leading	O
clock	O
edge	O
.	O
</s>
<s>
For	O
the	O
last	O
cycle	O
,	O
the	O
slave	O
holds	O
the	O
MISO	B-Architecture
line	O
valid	O
until	O
slave	B-Architecture
select	I-Architecture
is	O
deasserted	O
.	O
</s>
<s>
The	O
MOSI	B-Architecture
and	O
MISO	B-Architecture
signals	O
are	O
usually	O
stable	O
(	O
at	O
their	O
reception	O
points	O
)	O
for	O
the	O
half	O
cycle	O
until	O
the	O
next	O
clock	O
transition	O
.	O
</s>
<s>
For	O
"	O
Microchip	B-Architecture
PIC	I-Architecture
"	O
/	O
"	O
ARM-based	O
"	O
microcontrollers	O
(	O
note	O
that	O
NCPHA	O
is	O
the	O
inversion	O
of	O
CPHA	O
)	O
:	O
</s>
<s>
In	O
the	O
independent	O
slave	O
configuration	O
,	O
there	O
is	O
an	O
independent	O
chip	B-Architecture
select	I-Architecture
line	O
for	O
each	O
slave	O
.	O
</s>
<s>
The	O
master	O
asserts	O
only	O
one	O
chip	B-Architecture
select	I-Architecture
at	O
a	O
time	O
.	O
</s>
<s>
Pull-up	O
resistors	O
between	O
power	O
source	O
and	O
chip	B-Architecture
select	I-Architecture
lines	O
are	O
recommended	O
for	O
systems	O
where	O
the	O
master	O
's	O
chip	B-Architecture
select	I-Architecture
pins	O
may	O
default	O
to	O
an	O
undefined	O
state	O
.	O
</s>
<s>
When	O
separate	O
software	O
routines	O
initialize	O
each	O
chip	B-Architecture
select	I-Architecture
and	O
communicate	O
with	O
its	O
slave	O
,	O
pull-up	O
resistors	O
prevent	O
other	O
uninitialized	O
slaves	O
from	O
responding	O
.	O
</s>
<s>
Since	O
the	O
MISO	B-Architecture
pins	O
of	O
the	O
slaves	O
are	O
connected	O
together	O
,	O
they	O
are	O
required	O
to	O
be	O
tri-state	O
pins	O
(	O
high	O
,	O
low	O
or	O
high-impedance	O
)	O
,	O
where	O
the	O
high-impedance	O
output	O
must	O
be	O
applied	O
when	O
the	O
slave	O
is	O
not	O
selected	O
.	O
</s>
<s>
Slave	O
devices	O
not	O
supporting	O
tri-state	O
may	O
be	O
used	O
in	O
independent	O
slave	O
configuration	O
by	O
adding	O
a	O
tri-state	O
buffer	O
chip	O
controlled	O
by	O
the	O
chip	B-Architecture
select	I-Architecture
signal	O
.	O
</s>
<s>
Some	O
products	O
that	O
implement	O
SPI	O
may	O
be	O
connected	O
in	O
a	O
daisy	B-Application
chain	I-Application
configuration	O
,	O
the	O
first	O
slave	O
output	O
being	O
connected	O
to	O
the	O
second	O
slave	O
input	O
,	O
etc	O
.	O
</s>
<s>
The	O
whole	O
chain	O
acts	O
as	O
a	O
communication	O
shift	B-General_Concept
register	I-General_Concept
;	O
daisy	O
chaining	O
is	O
often	O
done	O
with	O
shift	B-General_Concept
registers	I-General_Concept
to	O
provide	O
a	O
bank	O
of	O
inputs	O
or	O
outputs	O
through	O
SPI	O
.	O
</s>
<s>
Other	O
applications	O
that	O
can	B-Protocol
potentially	O
interoperate	O
with	O
SPI	O
that	O
require	O
a	O
daisy	B-Application
chain	I-Application
configuration	O
include	O
SGPIO	O
,	O
JTAG	O
,	O
and	O
Two	O
Wire	O
Interface	O
.	O
</s>
<s>
Another	O
variation	O
uses	O
exactly	O
two	O
chip	B-Architecture
selects	I-Architecture
.	O
</s>
<s>
One	O
chip	B-Architecture
select	I-Architecture
controls	O
a	O
block	O
of	O
selection	O
logic	O
,	O
the	O
other	O
is	O
routed	O
by	O
the	O
selection	O
logic	O
.	O
</s>
<s>
The	O
application	O
is	O
common	O
enough	O
that	O
there	O
are	O
available	O
serial-controlled	O
multiplexers	O
.	O
</s>
<s>
This	O
can	B-Protocol
standardize	O
and	O
future-proof	O
a	O
connector	O
,	O
so	O
that	O
a	O
controller	O
can	B-Protocol
support	O
many	O
devices	O
with	O
a	O
change	O
of	O
software	O
.	O
</s>
<s>
A	O
similar	O
application	O
pairs	O
serial	B-Protocol
controlled	O
multiplexer	O
with	O
a	O
merchant	O
USB-to-SPI	O
controller	O
,	O
controlled	O
by	O
a	O
PC	O
or	O
smart-phone	O
.	O
</s>
<s>
In	O
electrically	O
noisy	O
environments	O
,	O
the	O
SPI	O
standard	O
has	O
few	O
signals	O
,	O
and	O
it	O
can	B-Protocol
be	O
economical	O
to	O
reduce	O
the	O
effects	O
of	O
common	O
mode	O
noise	O
by	O
adapting	O
SPI	O
to	O
use	O
low-voltage	B-Architecture
differential	I-Architecture
signaling	I-Architecture
.	O
</s>
<s>
Another	O
advantage	O
is	O
that	O
the	O
controlled	O
devices	O
can	B-Protocol
be	O
designed	O
to	O
loop-back	O
to	O
test	O
signal	O
integrity	O
.	O
</s>
<s>
SPI	O
lends	O
itself	O
to	O
a	O
"	O
bus	B-General_Concept
driver	O
"	O
software	O
design	O
.	O
</s>
<s>
Software	O
for	O
attached	O
devices	O
is	O
written	O
to	O
call	O
a	O
"	O
bus	B-General_Concept
driver	O
"	O
that	O
handles	O
the	O
actual	O
low-level	O
SPI	O
hardware	O
.	O
</s>
<s>
This	O
permits	O
the	O
driver	O
code	O
for	O
attached	O
devices	O
to	O
port	O
easily	O
to	O
other	O
hardware	O
,	O
including	O
a	O
bit-banging	B-Algorithm
design	O
.	O
</s>
<s>
Below	O
is	O
an	O
example	O
of	O
bit-banging	B-Algorithm
the	O
SPI	B-Architecture
protocol	I-Architecture
as	O
an	O
SPI	O
master	O
with	O
CPOL	O
=	O
0	O
,	O
CPHA	O
=	O
0	O
,	O
and	O
eight	O
bits	O
per	O
transfer	O
.	O
</s>
<s>
The	O
example	O
is	O
written	O
in	O
the	O
C	B-Language
programming	I-Language
language	I-Language
.	O
</s>
<s>
Because	O
this	O
is	O
CPOL	O
=	O
0	O
the	O
clock	O
must	O
be	O
pulled	O
low	O
before	O
the	O
chip	B-Architecture
select	I-Architecture
is	O
activated	O
.	O
</s>
<s>
The	O
chip	B-Architecture
select	I-Architecture
line	O
must	O
be	O
activated	O
,	O
which	O
normally	O
means	O
being	O
toggled	O
low	O
,	O
for	O
the	O
peripheral	O
before	O
the	O
start	O
of	O
the	O
transfer	O
,	O
and	O
then	O
deactivated	O
afterward	O
.	O
</s>
<s>
Higher	O
throughput	O
than	O
I²C	O
or	O
SMBus	B-Algorithm
.	O
</s>
<s>
Only	O
handles	O
short	O
distances	O
compared	O
to	O
RS-232	O
,	O
RS-485	O
,	O
or	O
CAN-bus	B-Protocol
.	O
</s>
<s>
(	O
Its	O
distance	O
can	B-Protocol
be	O
extended	O
with	O
the	O
use	O
of	O
transceivers	O
like	O
RS-422	O
.	O
)	O
</s>
<s>
SPI	O
does	O
not	O
support	O
hot	B-Device
swapping	I-Device
(	O
dynamically	O
adding	O
nodes	O
)	O
.	O
</s>
<s>
Interrupts	O
must	O
either	O
be	O
implemented	O
with	O
out-of-band	O
signals	O
or	O
be	O
faked	O
by	O
using	O
periodic	O
polling	O
similarly	O
to	O
USB	B-Protocol
1.1	O
and	O
2.0	O
.	O
</s>
<s>
Some	O
variants	O
like	O
dual	O
SPI	O
,	O
quad	O
SPI	O
,	O
and	O
three-wire	O
serial	B-Protocol
buses	O
defined	O
below	O
are	O
half-duplex	O
.	O
</s>
<s>
The	O
board	O
real	O
estate	O
savings	O
compared	O
to	O
a	O
parallel	O
I/O	B-General_Concept
bus	I-General_Concept
are	O
significant	O
,	O
and	O
have	O
earned	O
SPI	O
a	O
solid	O
role	O
in	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
That	O
is	O
true	O
for	O
most	O
system-on-a-chip	B-Architecture
processors	O
,	O
both	O
with	O
higher	O
end	O
32-bit	O
processors	O
such	O
as	O
those	O
using	O
ARM	B-Architecture
,	O
MIPS	B-Device
,	O
or	O
PowerPC	B-Architecture
and	O
with	O
other	O
microcontrollers	O
such	O
as	O
the	O
AVR	B-Architecture
,	O
PIC	B-Architecture
,	O
and	O
MSP430	B-Architecture
.	O
</s>
<s>
In-system	B-Device
programmable	I-Device
AVR	B-Architecture
controllers	I-Architecture
(	O
including	O
blank	O
ones	O
)	O
can	B-Protocol
be	O
programmed	O
using	O
a	O
SPI	B-Architecture
interface	I-Architecture
.	O
</s>
<s>
Chip	O
or	O
FPGA	B-Architecture
based	O
designs	O
sometimes	O
use	O
SPI	O
to	O
communicate	O
between	O
internal	O
components	O
;	O
on-chip	O
real	O
estate	O
can	B-Protocol
be	O
as	O
costly	O
as	O
its	O
on-board	O
cousin	O
.	O
</s>
<s>
Some	O
devices	O
use	O
the	O
full-duplex	O
mode	O
to	O
implement	O
an	O
efficient	O
,	O
swift	O
data	O
stream	O
for	O
applications	O
such	O
as	O
digital	O
audio	O
,	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
,	O
or	O
telecommunications	O
channels	O
,	O
but	O
most	O
off-the-shelf	O
chips	O
stick	O
to	O
half-duplex	O
request/response	O
protocols	O
.	O
</s>
<s>
For	O
high-performance	O
systems	O
,	O
FPGAs	B-Architecture
sometimes	O
use	O
SPI	O
to	O
interface	O
as	O
a	O
slave	O
to	O
a	O
host	O
,	O
as	O
a	O
master	O
to	O
sensors	O
,	O
or	O
for	O
flash	O
memory	O
used	O
to	O
bootstrap	O
if	O
they	O
are	O
SRAM-based	O
.	O
</s>
<s>
Although	O
there	O
are	O
some	O
similarities	O
between	O
the	O
SPI	B-Architecture
bus	I-Architecture
and	O
the	O
JTAG	O
(	O
IEEE	O
1149.1-2013	O
)	O
protocol	O
,	O
they	O
are	O
not	O
interchangeable	O
.	O
</s>
<s>
The	O
SPI	B-Architecture
bus	I-Architecture
is	O
intended	O
for	O
high	O
speed	O
,	O
on	O
board	O
initialization	O
of	O
device	O
peripherals	O
,	O
while	O
the	O
JTAG	O
protocol	O
is	O
intended	O
to	O
provide	O
reliable	O
test	O
access	O
to	O
the	O
I/O	O
pins	O
from	O
an	O
off	O
board	O
controller	O
with	O
less	O
precise	O
signal	O
delay	O
and	O
skew	O
parameters	O
.	O
</s>
<s>
The	O
SPI	B-Architecture
bus	I-Architecture
is	O
a	O
de	O
facto	O
standard	O
.	O
</s>
<s>
Chip	B-Architecture
selects	I-Architecture
are	O
sometimes	O
active-high	O
rather	O
than	O
active-low	O
.	O
</s>
<s>
SPI	B-Architecture
Bus	I-Architecture
was	O
originally	O
defined	O
by	O
Motorola	O
.	O
</s>
<s>
When	O
NXP	O
acquired	O
Freescale	O
,	O
NXP	O
also	O
acquired	O
responsibility	O
for	O
AN991	O
which	O
was	O
last	O
revised	O
in	O
January	O
2002	O
as	O
AN991/D	O
and	O
still	O
serves	O
as	O
the	O
"	O
official	O
"	O
defining	O
document	O
for	O
SPI	B-Architecture
Bus	I-Architecture
.	O
</s>
<s>
Many	O
of	O
the	O
read	O
clocks	O
run	O
from	O
the	O
chip	B-Architecture
select	I-Architecture
line	O
.	O
</s>
<s>
Examples	O
include	O
initiating	O
an	O
ADC	O
conversion	O
,	O
addressing	O
the	O
right	O
page	O
of	O
flash	O
memory	O
,	O
and	O
processing	O
enough	O
of	O
a	O
command	O
that	O
device	O
firmware	O
can	B-Protocol
load	O
the	O
first	O
word	O
of	O
the	O
response	O
.	O
</s>
<s>
Such	O
chips	O
can	B-Protocol
not	O
interoperate	O
with	O
the	O
JTAG	O
or	O
SGPIO	O
protocols	O
,	O
or	O
any	O
other	O
protocol	O
that	O
requires	O
messages	O
that	O
are	O
not	O
multiples	O
of	O
8	O
bits	O
.	O
</s>
<s>
Some	O
chips	O
combine	O
MOSI	B-Architecture
and	O
MISO	B-Architecture
into	O
a	O
single	O
data	O
line	O
(	O
SI/SO	O
)	O
;	O
this	O
is	O
sometimes	O
called	O
'	O
three-wire	O
'	O
signaling	O
(	O
in	O
contrast	O
to	O
normal	O
'	O
four-wire	O
'	O
SPI	O
)	O
.	O
</s>
<s>
Another	O
variation	O
of	O
SPI	O
removes	O
the	O
chip	B-Architecture
select	I-Architecture
line	O
,	O
managing	O
protocol	O
state	O
machine	O
entry/exit	O
using	O
other	O
methods	O
.	O
</s>
<s>
Anyone	O
needing	O
an	O
external	O
connector	O
for	O
SPI	O
defines	O
their	O
own	O
:	O
UEXT	B-Protocol
,	O
JTAG	O
connector	O
,	O
Secure	B-Device
Digital	I-Device
card	I-Device
socket	O
,	O
etc	O
.	O
</s>
<s>
When	O
developing	O
or	O
troubleshooting	O
systems	O
using	O
SPI	O
,	O
visibility	O
at	O
the	O
level	O
of	O
hardware	O
signals	O
can	B-Protocol
be	O
important	O
.	O
</s>
<s>
There	O
are	O
a	O
number	O
of	O
USB	B-Protocol
hardware	O
solutions	O
to	O
provide	O
computers	O
,	O
running	O
Linux	B-Application
,	O
macOS	B-Application
,	O
or	O
Windows	B-Application
,	O
SPI	O
master	O
or	O
slave	O
capabilities	O
.	O
</s>
<s>
Many	O
of	O
them	O
also	O
provide	O
scripting	O
or	O
programming	O
capabilities	O
(	O
Visual	O
Basic	O
,	O
C/C	O
++	O
,	O
VHDL	O
,	O
etc	O
.	O
</s>
<s>
An	O
SPI	O
host	O
adapter	O
lets	O
the	O
user	O
play	O
the	O
role	O
of	O
a	O
master	O
on	O
an	O
SPI	B-Architecture
bus	I-Architecture
directly	O
from	O
a	O
PC	O
.	O
</s>
<s>
They	O
are	O
used	O
for	O
embedded	B-Architecture
systems	I-Architecture
,	O
chips	O
(	O
FPGA	B-Architecture
,	O
ASIC	O
,	O
and	O
SoC	O
)	O
and	O
peripheral	O
testing	O
,	O
programming	O
and	O
debugging	O
.	O
</s>
<s>
The	O
key	O
parameters	O
of	O
SPI	O
are	O
:	O
the	O
maximum	O
supported	O
frequency	O
for	O
the	O
serial	B-Protocol
interface	O
,	O
command-to-command	O
latency	O
and	O
the	O
maximum	O
length	O
for	O
SPI	O
commands	O
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
find	O
SPI	O
adapters	O
on	O
the	O
market	O
today	O
that	O
support	O
up	O
to	O
100MHz	O
serial	B-Protocol
interfaces	O
,	O
with	O
virtually	O
unlimited	O
access	O
length	O
.	O
</s>
<s>
SPI	B-Architecture
protocol	I-Architecture
being	O
a	O
de	O
facto	O
standard	O
,	O
some	O
SPI	O
host	O
adapters	O
also	O
have	O
the	O
ability	O
of	O
supporting	O
other	O
protocols	O
beyond	O
the	O
traditional	O
4-wire	O
SPI	O
(	O
for	O
example	O
,	O
support	O
of	O
quad-SPI	O
protocol	O
or	O
other	O
custom	O
serial	B-Protocol
protocol	O
that	O
derive	O
from	O
SPI	O
)	O
.	O
</s>
<s>
SPI	B-Architecture
protocol	I-Architecture
analyzers	O
are	O
tools	O
which	O
sample	O
an	O
SPI	B-Architecture
bus	I-Architecture
and	O
decode	O
the	O
electrical	O
signals	O
to	O
provide	O
a	O
higher-level	O
view	O
of	O
the	O
data	O
being	O
transmitted	O
on	O
a	O
specific	O
bus	B-General_Concept
.	O
</s>
<s>
SPI	B-Architecture
signals	I-Architecture
can	B-Protocol
be	O
accessed	O
via	O
analog	O
oscilloscope	O
channels	O
or	O
with	O
digital	O
MSO	O
channels	O
.	O
</s>
<s>
When	O
developing	O
or	O
troubleshooting	O
the	O
SPI	B-Architecture
bus	I-Architecture
,	O
examination	O
of	O
hardware	O
signals	O
can	B-Protocol
be	O
very	O
important	O
.	O
</s>
<s>
Logic	O
analyzers	O
are	O
tools	O
which	O
collect	O
,	O
analyze	O
,	O
decode	O
,	O
and	O
store	O
signals	O
so	O
people	O
can	B-Protocol
view	O
the	O
high-speed	O
waveforms	O
at	O
their	O
leisure	O
.	O
</s>
<s>
Logic	O
analyzers	O
display	O
time-stamps	O
of	O
each	O
signal	O
level	O
change	O
,	O
which	O
can	B-Protocol
help	O
find	O
protocol	O
problems	O
.	O
</s>
<s>
Most	O
logic	O
analyzers	O
have	O
the	O
capability	O
to	O
decode	O
bus	B-General_Concept
signals	O
into	O
high-level	O
protocol	O
data	O
and	O
show	O
ASCII	O
data	O
.	O
</s>
<s>
A	O
Queued	B-Architecture
Serial	I-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
(	O
QSPI	O
;	O
see	O
also	O
Quad	O
SPI	O
)	O
is	O
a	O
type	O
of	O
SPI	O
controller	O
that	O
uses	O
a	O
data	B-Application
queue	I-Application
to	O
transfer	O
data	O
across	O
the	O
SPI	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
It	O
has	O
a	O
wrap-around	B-Data_Structure
mode	O
allowing	O
continuous	O
transfers	O
to	O
and	O
from	O
the	O
queue	B-Application
with	O
only	O
intermittent	O
attention	O
from	O
the	O
CPU	O
.	O
</s>
<s>
Consequently	O
,	O
the	O
peripherals	O
appear	O
to	O
the	O
CPU	O
as	O
memory-mapped	B-Architecture
parallel	O
devices	O
.	O
</s>
<s>
Other	O
programmable	O
features	O
in	O
QSPI	O
are	O
chip	B-Architecture
selects	I-Architecture
and	O
transfer	O
length/delay	O
.	O
</s>
<s>
SPI	O
controllers	O
from	O
different	O
vendors	O
support	O
different	O
feature	O
sets	O
;	O
such	O
DMA	O
queues	B-Application
are	O
not	O
uncommon	O
,	O
although	O
they	O
may	O
be	O
associated	O
with	O
separate	O
DMA	O
engines	O
rather	O
than	O
the	O
SPI	O
controller	O
itself	O
,	O
such	O
as	O
used	O
by	O
Multichannel	O
Buffered	O
Serial	B-Protocol
Port	O
(	O
MCBSP	O
)	O
.	O
</s>
<s>
Most	O
SPI	O
master	O
controllers	O
integrate	O
support	O
for	O
up	O
to	O
four	O
chip	B-Architecture
selects	I-Architecture
,	O
although	O
some	O
require	O
chip	B-Architecture
selects	I-Architecture
to	O
be	O
managed	O
separately	O
through	O
GPIO	B-Architecture
lines	O
.	O
</s>
<s>
There	O
was	O
no	O
specified	O
improvement	O
in	O
serial	B-Protocol
clock	O
speed	O
.	O
</s>
<s>
As	O
mentioned	O
,	O
one	O
variant	O
of	O
SPI	O
uses	O
a	O
single	O
bidirectional	O
data	O
line	O
(	O
slave	O
out/slave	O
in	O
,	O
called	O
SISO	O
or	O
master	O
out/master	O
in	O
,	O
called	O
MOMI	O
)	O
instead	O
of	O
two	O
unidirectional	O
ones	O
(	O
MOSI	B-Architecture
and	O
MISO	B-Architecture
)	O
.	O
</s>
<s>
Few	O
SPI	O
master	O
controllers	O
support	O
this	O
mode	O
;	O
although	O
it	O
can	B-Protocol
often	O
be	O
easily	O
bit-banged	B-Algorithm
in	O
software	O
.	O
</s>
<s>
Typically	O
a	O
command	O
byte	O
is	O
sent	O
requesting	O
a	O
response	O
in	O
dual	O
mode	O
,	O
after	O
which	O
the	O
MOSI	B-Architecture
line	O
becomes	O
SIO0	O
(	O
serial	B-Protocol
I/O	I-Protocol
0	O
)	O
and	O
carries	O
even	O
bits	O
,	O
while	O
the	O
MISO	B-Architecture
line	O
becomes	O
SIO1	O
and	O
carries	O
odd	O
bits	O
.	O
</s>
<s>
Dual	O
read	O
commands	O
the	O
send	O
and	O
address	B-General_Concept
from	O
the	O
master	O
in	O
single	O
mode	O
,	O
and	O
return	O
the	O
data	O
in	O
dual	O
mode	O
.	O
</s>
<s>
Dual	O
I/O	O
commands	O
send	O
the	O
command	O
in	O
single	O
mode	O
,	O
then	O
send	O
the	O
address	B-General_Concept
and	O
return	O
data	O
in	O
dual	O
mode	O
.	O
</s>
<s>
Intel	O
has	O
developed	O
a	O
successor	O
to	O
its	O
Low	O
Pin	O
Count	O
(	O
LPC	O
)	O
bus	B-General_Concept
that	O
it	O
calls	O
the	O
Enhanced	O
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
Bus	I-Architecture
,	O
or	O
eSPI	O
for	O
short	O
.	O
</s>
<s>
Intel	O
aims	O
to	O
allow	O
the	O
reduction	O
in	O
the	O
number	O
of	O
pins	O
required	O
on	O
motherboards	O
compared	O
to	O
systems	O
using	O
LPC	O
,	O
have	O
more	O
available	O
throughput	O
than	O
LPC	O
,	O
reduce	O
the	O
working	O
voltage	O
to	O
1.8	O
volts	O
to	O
facilitate	O
smaller	O
chip	O
manufacturing	O
processes	O
,	O
allow	O
eSPI	O
peripherals	O
to	O
share	O
SPI	O
flash	O
devices	O
with	O
the	O
host	O
(	O
the	O
LPC	O
bus	B-General_Concept
did	O
not	O
allow	O
firmware	O
hubs	O
to	O
be	O
used	O
by	O
LPC	O
peripherals	O
)	O
,	O
tunnel	O
previous	O
out-of-band	O
pins	O
through	O
the	O
eSPI	O
bus	B-General_Concept
,	O
and	O
allow	O
system	O
designers	O
to	O
trade	O
off	O
cost	O
and	O
performance	O
.	O
</s>
<s>
The	O
eSPI	O
bus	B-General_Concept
can	B-Protocol
either	O
be	O
shared	O
with	O
SPI	O
devices	O
to	O
save	O
pins	O
or	O
be	O
separate	O
from	O
the	O
SPI	B-Architecture
bus	I-Architecture
to	O
allow	O
more	O
performance	O
,	O
especially	O
when	O
eSPI	O
devices	O
need	O
to	O
use	O
SPI	O
flash	O
devices	O
.	O
</s>
<s>
All	O
communications	O
that	O
were	O
out-of-band	O
of	O
the	O
LPC	O
bus	B-General_Concept
like	O
general-purpose	B-Architecture
input/output	I-Architecture
(	O
GPIO	B-Architecture
)	O
and	O
System	B-Algorithm
Management	I-Algorithm
Bus	I-Algorithm
(	O
SMBus	B-Algorithm
)	O
are	O
tunneled	O
through	O
the	O
eSPI	O
bus	B-General_Concept
via	O
virtual	O
wire	O
cycles	O
and	O
out-of-band	O
message	O
cycles	O
respectively	O
in	O
order	O
to	O
remove	O
those	O
pins	O
from	O
motherboard	O
designs	O
using	O
eSPI	O
.	O
</s>
<s>
This	O
significantly	O
reduces	O
overhead	O
compared	O
to	O
the	O
LPC	O
bus	B-General_Concept
,	O
where	O
all	O
cycles	O
except	O
for	O
the	O
128-byte	O
firmware	O
hub	O
read	O
cycle	O
spends	O
more	O
than	O
one-half	O
of	O
all	O
of	O
the	O
bus	B-General_Concept
's	O
throughput	O
and	O
time	O
in	O
overhead	O
.	O
</s>
<s>
eSPI	O
slaves	O
are	O
allowed	O
to	O
initiate	O
bus	B-General_Concept
master	O
versions	O
of	O
all	O
of	O
the	O
memory	O
cycles	O
.	O
</s>
<s>
Bus	B-General_Concept
master	O
I/O	O
cycles	O
,	O
which	O
were	O
introduced	O
by	O
the	O
LPC	O
bus	B-General_Concept
specification	O
,	O
and	O
ISA-style	O
DMA	O
including	O
the	O
32-bit	O
variant	O
introduced	O
by	O
the	O
LPC	O
bus	B-General_Concept
specification	O
,	O
are	O
not	O
present	O
in	O
eSPI	O
.	O
</s>
<s>
Therefore	O
,	O
bus	B-General_Concept
master	O
memory	O
cycles	O
are	O
the	O
only	O
allowed	O
DMA	O
in	O
this	O
standard	O
.	O
</s>
<s>
64-bit	O
memory	O
addressing	O
is	O
also	O
added	O
,	O
but	O
is	O
only	O
permitted	O
when	O
there	O
is	O
no	O
equivalent	O
32-bit	O
address	B-General_Concept
.	O
</s>
<s>
The	O
Intel	O
Z170	O
chipset	O
can	B-Protocol
be	O
configured	O
to	O
implement	O
either	O
this	O
bus	B-General_Concept
or	O
a	O
variant	O
of	O
the	O
LPC	O
bus	B-General_Concept
that	O
is	O
missing	O
its	O
ISA-style	O
DMA	O
capability	O
and	O
is	O
underclocked	O
to	O
24MHz	O
instead	O
of	O
the	O
standard	O
33MHz	O
.	O
</s>
