<s>
Semiconductor	B-Architecture
memory	I-Architecture
is	O
a	O
digital	O
electronic	O
semiconductor	O
device	O
used	O
for	O
digital	B-Architecture
data	I-Architecture
storage	I-Architecture
,	O
such	O
as	O
computer	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
It	O
typically	O
refers	O
to	O
devices	O
in	O
which	O
data	O
is	O
stored	O
within	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
memory	B-Algorithm
cells	I-Algorithm
on	O
a	O
silicon	O
integrated	O
circuit	O
memory	B-Architecture
chip	I-Architecture
.	O
</s>
<s>
The	O
two	O
main	O
types	O
of	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
are	O
static	B-Architecture
RAM	I-Architecture
(	O
SRAM	O
)	O
,	O
which	O
uses	O
several	O
transistors	B-Application
per	O
memory	B-Algorithm
cell	I-Algorithm
,	O
and	O
dynamic	O
RAM	B-Architecture
(	O
DRAM	O
)	O
,	O
which	O
uses	O
a	O
transistor	B-Application
and	O
a	O
MOS	O
capacitor	O
per	O
cell	O
.	O
</s>
<s>
Non-volatile	B-General_Concept
memory	I-General_Concept
(	O
such	O
as	O
EPROM	B-General_Concept
,	O
EEPROM	B-General_Concept
and	O
flash	B-Device
memory	I-Device
)	O
uses	O
floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
,	O
which	O
consist	O
of	O
a	O
single	O
floating-gate	B-Algorithm
transistor	I-Algorithm
per	O
cell	O
.	O
</s>
<s>
Most	O
types	O
of	O
semiconductor	B-Architecture
memory	I-Architecture
have	O
the	O
property	O
of	O
random	B-General_Concept
access	I-General_Concept
,	O
which	O
means	O
that	O
it	O
takes	O
the	O
same	O
amount	O
of	O
time	O
to	O
access	O
any	O
memory	B-General_Concept
location	I-General_Concept
,	O
so	O
data	O
can	O
be	O
efficiently	O
accessed	O
in	O
any	O
random	O
order	O
.	O
</s>
<s>
This	O
contrasts	O
with	O
data	O
storage	B-General_Concept
media	O
such	O
as	O
hard	B-Device
disks	I-Device
and	O
CDs	O
which	O
read	O
and	O
write	O
data	O
consecutively	O
and	O
therefore	O
the	O
data	O
can	O
only	O
be	O
accessed	O
in	O
the	O
same	O
sequence	O
it	O
was	O
written	O
.	O
</s>
<s>
Semiconductor	B-Architecture
memory	I-Architecture
also	O
has	O
much	O
faster	O
access	B-General_Concept
times	I-General_Concept
than	O
other	O
types	O
of	O
data	O
storage	B-General_Concept
;	O
a	O
byte	B-Application
of	O
data	O
can	O
be	O
written	O
to	O
or	O
read	O
from	O
semiconductor	B-Architecture
memory	I-Architecture
within	O
a	O
few	O
nanoseconds	O
,	O
while	O
access	B-General_Concept
time	I-General_Concept
for	O
rotating	O
storage	B-General_Concept
such	O
as	O
hard	B-Device
disks	I-Device
is	O
in	O
the	O
range	O
of	O
milliseconds	O
.	O
</s>
<s>
For	O
these	O
reasons	O
it	O
is	O
used	O
for	O
primary	O
storage	B-General_Concept
,	O
to	O
hold	O
the	O
program	O
and	O
data	O
the	O
computer	O
is	O
currently	O
working	O
on	O
,	O
among	O
other	O
uses	O
.	O
</s>
<s>
,	O
semiconductor	B-Architecture
memory	I-Architecture
chips	O
sell	O
annually	O
,	O
accounting	O
for	O
%	O
of	O
the	O
semiconductor	O
industry	O
.	O
</s>
<s>
Shift	B-General_Concept
registers	I-General_Concept
,	O
processor	B-General_Concept
registers	I-General_Concept
,	O
data	B-General_Concept
buffers	I-General_Concept
and	O
other	O
small	O
digital	O
registers	O
that	O
have	O
no	O
memory	B-Device
address	I-Device
decoding	I-Device
mechanism	I-Device
are	O
typically	O
not	O
referred	O
to	O
as	O
memory	O
although	O
they	O
also	O
store	O
digital	O
data	O
.	O
</s>
<s>
In	O
a	O
semiconductor	B-Architecture
memory	I-Architecture
chip	O
,	O
each	O
bit	O
of	O
binary	O
data	O
is	O
stored	O
in	O
a	O
tiny	O
circuit	O
called	O
a	O
memory	B-Algorithm
cell	I-Algorithm
consisting	O
of	O
one	O
to	O
several	O
transistors	B-Application
.	O
</s>
<s>
The	O
memory	B-Algorithm
cells	I-Algorithm
are	O
laid	O
out	O
in	O
rectangular	O
arrays	O
on	O
the	O
surface	O
of	O
the	O
chip	O
.	O
</s>
<s>
The	O
1-bit	O
memory	B-Algorithm
cells	I-Algorithm
are	O
grouped	O
in	O
small	O
units	O
called	O
words	O
which	O
are	O
accessed	O
together	O
as	O
a	O
single	O
memory	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
Data	O
is	O
accessed	O
by	O
means	O
of	O
a	O
binary	O
number	O
called	O
a	O
memory	B-General_Concept
address	I-General_Concept
applied	O
to	O
the	O
chip	O
's	O
address	O
pins	O
,	O
which	O
specifies	O
which	O
word	O
in	O
the	O
chip	O
is	O
to	O
be	O
accessed	O
.	O
</s>
<s>
If	O
the	O
memory	B-General_Concept
address	I-General_Concept
consists	O
of	O
M	O
bits	O
,	O
the	O
number	O
of	O
addresses	O
on	O
the	O
chip	O
is	O
2M	O
,	O
each	O
containing	O
an	O
N	O
bit	O
word	O
.	O
</s>
<s>
The	O
memory	O
storage	B-General_Concept
capacity	I-General_Concept
for	O
M	O
number	O
of	O
address	O
lines	O
is	O
given	O
by	O
2M	O
,	O
which	O
is	O
usually	O
in	O
power	O
of	O
two	O
:	O
2	O
,	O
4	O
,	O
8	O
,	O
16	O
,	O
32	O
,	O
64	O
,	O
128	O
,	O
256	O
and	O
512	O
and	O
measured	O
in	O
kilobits	O
,	O
megabits	O
,	O
gigabits	O
or	O
terabits	O
,	O
etc	O
.	O
</s>
<s>
the	O
largest	O
semiconductor	B-Architecture
memory	I-Architecture
chips	O
hold	O
a	O
few	O
gigabits	O
of	O
data	O
,	O
but	O
higher	O
capacity	O
memory	O
is	O
constantly	O
being	O
developed	O
.	O
</s>
<s>
The	O
two	O
basic	O
operations	O
performed	O
by	O
a	O
memory	B-Architecture
chip	I-Architecture
are	O
"	O
read	O
"	O
,	O
in	O
which	O
the	O
data	O
contents	O
of	O
a	O
memory	O
word	O
is	O
read	O
out	O
(	O
nondestructively	O
)	O
,	O
and	O
"	O
write	O
"	O
in	O
which	O
data	O
is	O
stored	O
in	O
a	O
memory	O
word	O
,	O
replacing	O
any	O
data	O
that	O
was	O
previously	O
stored	O
there	O
.	O
</s>
<s>
To	O
increase	O
data	O
rate	O
,	O
in	O
some	O
of	O
the	O
latest	O
types	O
of	O
memory	B-Architecture
chips	I-Architecture
such	O
as	O
DDR	O
SDRAM	O
multiple	O
words	O
are	O
accessed	O
with	O
each	O
read	O
or	O
write	O
operation	O
.	O
</s>
<s>
In	O
addition	O
to	O
standalone	O
memory	B-Architecture
chips	I-Architecture
,	O
blocks	O
of	O
semiconductor	B-Architecture
memory	I-Architecture
are	O
integral	O
parts	O
of	O
many	O
computer	O
and	O
data	O
processing	O
integrated	O
circuits	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
microprocessor	B-Architecture
chips	O
that	O
run	O
computers	O
contain	O
cache	B-General_Concept
memory	I-General_Concept
to	O
store	O
instructions	O
awaiting	O
execution	O
.	O
</s>
<s>
Volatile	B-General_Concept
memory	I-General_Concept
loses	O
its	O
stored	O
data	O
when	O
the	O
power	O
to	O
the	O
memory	B-Architecture
chip	I-Architecture
is	O
turned	O
off	O
.	O
</s>
<s>
However	O
it	O
can	O
be	O
faster	O
and	O
less	O
expensive	O
than	O
non-volatile	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
This	O
type	O
is	O
used	O
for	O
the	O
main	O
memory	O
in	O
most	O
computers	O
,	O
since	O
data	O
is	O
stored	O
on	O
the	O
hard	B-Device
disk	I-Device
while	O
the	O
computer	O
is	O
off	O
.	O
</s>
<s>
RAM	B-Architecture
(	O
Random-access	B-Architecture
memory	I-Architecture
)	O
This	O
has	O
become	O
a	O
generic	O
term	O
for	O
any	O
semiconductor	B-Architecture
memory	I-Architecture
that	O
can	O
be	O
written	O
to	O
,	O
as	O
well	O
as	O
read	O
from	O
,	O
in	O
contrast	O
to	O
ROM	B-Device
(	O
below	O
)	O
,	O
which	O
can	O
only	O
be	O
read	O
.	O
</s>
<s>
All	O
semiconductor	B-Architecture
memory	I-Architecture
,	O
not	O
just	O
RAM	B-Architecture
,	O
has	O
the	O
property	O
of	O
random	B-General_Concept
access	I-General_Concept
.	O
</s>
<s>
DRAM	O
(	O
Dynamic	O
random-access	B-Architecture
memory	I-Architecture
)	O
This	O
uses	O
memory	B-Algorithm
cells	I-Algorithm
consisting	O
of	O
one	O
MOSFET	B-Architecture
(	O
MOS	O
field-effect	O
transistor	B-Application
)	O
and	O
one	O
MOS	O
capacitor	O
to	O
store	O
each	O
bit	O
.	O
</s>
<s>
This	O
type	O
of	O
RAM	B-Architecture
is	O
the	O
cheapest	O
and	O
highest	O
in	O
density	O
,	O
so	O
it	O
is	O
used	O
for	O
the	O
main	O
memory	O
in	O
computers	O
.	O
</s>
<s>
However	O
,	O
the	O
electric	O
charge	O
that	O
stores	O
the	O
data	O
in	O
the	O
memory	B-Algorithm
cells	I-Algorithm
slowly	O
leaks	O
out	O
,	O
so	O
the	O
memory	B-Algorithm
cells	I-Algorithm
must	O
be	O
periodically	O
refreshed	B-General_Concept
(	O
rewritten	O
)	O
which	O
requires	O
additional	O
circuitry	O
.	O
</s>
<s>
EDO	O
DRAM	O
(	O
Extended	O
data	O
out	O
DRAM	O
)	O
An	O
older	O
type	O
of	O
asynchronous	O
DRAM	O
which	O
had	O
faster	O
access	B-General_Concept
time	I-General_Concept
than	O
earlier	O
types	O
by	O
being	O
able	O
to	O
initiate	O
a	O
new	O
memory	O
access	O
while	O
data	O
from	O
the	O
previous	O
access	O
was	O
still	O
being	O
transferred	O
.	O
</s>
<s>
VRAM	O
(	O
Video	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
)	O
An	O
older	O
type	O
of	O
dual-ported	B-General_Concept
memory	O
once	O
used	O
for	O
the	O
frame	B-Algorithm
buffers	I-Algorithm
of	O
video	B-Device
adapters	I-Device
(	O
video	B-Device
cards	I-Device
)	O
.	O
</s>
<s>
SDRAM	O
(	O
Synchronous	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
)	O
This	O
added	O
circuitry	O
to	O
the	O
DRAM	O
chip	O
which	O
synchronizes	O
all	O
operations	O
with	O
a	O
clock	O
signal	O
added	O
to	O
the	O
computer	O
's	O
memory	O
bus	O
.	O
</s>
<s>
This	O
allowed	O
the	O
chip	O
to	O
process	O
multiple	O
memory	O
requests	O
simultaneously	O
using	O
pipelining	B-General_Concept
,	O
to	O
increase	O
the	O
speed	O
.	O
</s>
<s>
This	O
became	O
the	O
dominant	O
type	O
of	O
computer	B-General_Concept
memory	I-General_Concept
by	O
about	O
the	O
year	O
2000	O
.	O
</s>
<s>
SGRAM	O
(	O
Synchronous	O
graphics	O
RAM	B-Architecture
)	O
A	O
specialized	O
type	O
of	O
SDRAM	O
made	O
for	O
graphics	B-Device
adaptors	I-Device
(	O
video	B-Device
cards	I-Device
)	O
.	O
</s>
<s>
HBM	O
(	O
High	O
Bandwidth	O
Memory	O
)	O
A	O
development	O
of	O
SDRAM	O
used	O
in	O
graphics	B-Device
cards	I-Device
that	O
can	O
transfer	O
data	O
at	O
a	O
faster	O
rate	O
.	O
</s>
<s>
It	O
consists	O
of	O
multiple	O
memory	B-Architecture
chips	I-Architecture
stacked	O
on	O
top	O
of	O
one	O
another	O
,	O
with	O
a	O
wider	O
data	O
bus	O
.	O
</s>
<s>
PSRAM	O
(	O
Pseudostatic	O
RAM	B-Architecture
)	O
This	O
is	O
DRAM	O
which	O
has	O
circuitry	O
to	O
perform	O
memory	B-General_Concept
refresh	I-General_Concept
on	O
the	O
chip	O
,	O
so	O
that	O
it	O
acts	O
like	O
SRAM	O
,	O
allowing	O
the	O
external	O
memory	O
controller	B-Architecture
to	O
be	O
shut	O
down	O
to	O
save	O
energy	O
.	O
</s>
<s>
It	O
is	O
used	O
in	O
a	O
few	O
game	O
consoles	O
such	O
as	O
the	B-Operating_System
Wii	I-Operating_System
.	O
</s>
<s>
SRAM	O
(	O
Static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
)	O
This	O
stores	O
each	O
bit	O
of	O
data	O
in	O
a	O
circuit	O
called	O
a	O
flip-flop	B-General_Concept
,	O
made	O
of	O
4	O
to	O
6	O
transistors	B-Application
.	O
</s>
<s>
SRAM	O
is	O
less	O
dense	O
and	O
more	O
expensive	O
per	O
bit	O
than	O
DRAM	O
,	O
but	O
faster	O
and	O
does	O
not	O
require	O
memory	B-General_Concept
refresh	I-General_Concept
.	O
</s>
<s>
It	O
is	O
used	O
for	O
smaller	O
cache	B-General_Concept
memories	I-General_Concept
in	O
computers	O
.	O
</s>
<s>
CAM	B-Data_Structure
(	O
Content-addressable	B-Data_Structure
memory	I-Data_Structure
)	O
This	O
is	O
a	O
specialized	O
type	O
in	O
which	O
,	O
instead	O
of	O
accessing	O
data	O
using	O
an	O
address	O
,	O
a	O
data	O
word	O
is	O
applied	O
and	O
the	O
memory	O
returns	O
the	O
location	O
if	O
the	O
word	O
is	O
stored	O
in	O
the	O
memory	O
.	O
</s>
<s>
It	O
is	O
mostly	O
incorporated	O
in	O
other	O
chips	O
such	O
as	O
microprocessors	B-Architecture
where	O
it	O
is	O
used	O
for	O
cache	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Non-volatile	B-General_Concept
memory	I-General_Concept
(	O
NVM	O
)	O
preserves	O
the	O
data	O
stored	O
in	O
it	O
during	O
periods	O
when	O
the	O
power	O
to	O
the	O
chip	O
is	O
turned	O
off	O
.	O
</s>
<s>
Therefore	O
,	O
it	O
is	O
used	O
for	O
the	O
memory	O
in	O
portable	B-Application
devices	I-Application
,	O
which	O
do	O
n't	O
have	O
disks	B-Device
,	O
and	O
for	O
removable	O
memory	B-Device
cards	I-Device
among	O
other	O
uses	O
.	O
</s>
<s>
ROM	B-Device
(	O
Read-only	B-Device
memory	I-Device
)	O
This	O
is	O
designed	O
to	O
hold	O
permanent	O
data	O
,	O
and	O
in	O
normal	O
operation	O
is	O
only	O
read	O
from	O
,	O
not	O
written	O
to	O
.	O
</s>
<s>
It	O
is	O
usually	O
used	O
to	O
store	O
system	B-Application
software	I-Application
which	O
must	O
be	O
immediately	O
accessible	O
to	O
the	O
computer	O
,	O
such	O
as	O
the	O
BIOS	B-Operating_System
program	O
which	O
starts	O
the	O
computer	O
,	O
and	O
the	O
software	O
(	O
microcode	B-Device
)	O
for	O
portable	B-Application
devices	I-Application
and	O
embedded	B-Architecture
computers	I-Architecture
such	O
as	O
microcontrollers	B-Architecture
.	O
</s>
<s>
MROM	B-Device
(	O
Mask	O
programmed	O
ROM	B-Device
or	O
Mask	B-Device
ROM	I-Device
)	O
In	O
this	O
type	O
the	O
data	O
is	O
programmed	O
into	O
the	O
chip	O
when	O
the	O
chip	O
is	O
manufactured	O
,	O
so	O
it	O
is	O
only	O
used	O
for	O
large	O
production	O
runs	O
.	O
</s>
<s>
PROM	O
(	O
Programmable	B-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
)	O
In	O
this	O
type	O
the	O
data	O
is	O
written	O
into	O
an	O
existing	O
PROM	O
chip	O
before	O
it	O
is	O
installed	O
in	O
the	O
circuit	O
,	O
but	O
it	O
can	O
only	O
be	O
written	O
once	O
.	O
</s>
<s>
EPROM	B-General_Concept
(	O
Erasable	B-General_Concept
programmable	I-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
or	O
UVEPROM	O
)	O
In	O
this	O
type	O
the	O
data	O
in	O
it	O
can	O
be	O
rewritten	O
by	O
removing	O
the	O
chip	O
from	O
the	O
circuit	O
board	O
,	O
exposing	O
it	O
to	O
an	O
ultraviolet	O
light	O
to	O
erase	O
the	O
existing	O
data	O
,	O
and	O
plugging	O
it	O
into	O
a	O
PROM	O
programmer	O
.	O
</s>
<s>
EEPROM	B-General_Concept
(	O
Electrically	B-General_Concept
erasable	I-General_Concept
programmable	I-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
)	O
In	O
this	O
type	O
the	O
data	O
can	O
be	O
rewritten	O
electrically	O
,	O
while	O
the	O
chip	O
is	O
on	O
the	O
circuit	O
board	O
,	O
but	O
the	O
writing	O
process	O
is	O
slow	O
.	O
</s>
<s>
This	O
type	O
is	O
used	O
to	O
hold	O
firmware	B-Application
,	O
the	O
low	O
level	O
microcode	B-Device
which	O
runs	O
hardware	O
devices	O
,	O
such	O
as	O
the	O
BIOS	B-Operating_System
program	O
in	O
most	O
computers	O
,	O
so	O
that	O
it	O
can	O
be	O
updated	O
.	O
</s>
<s>
FRAM	O
(	O
Ferroelectric	O
RAM	B-Architecture
)	O
One	O
type	O
of	O
nonvolatile	B-General_Concept
RAM	I-General_Concept
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
In	O
this	O
type	O
the	O
writing	O
process	O
is	O
intermediate	O
in	O
speed	O
between	O
EEPROMS	B-General_Concept
and	O
RAM	B-Architecture
memory	I-Architecture
;	O
it	O
can	O
be	O
written	O
to	O
,	O
but	O
not	O
fast	O
enough	O
to	O
serve	O
as	O
main	O
memory	O
.	O
</s>
<s>
It	O
is	O
often	O
used	O
as	O
a	O
semiconductor	O
version	O
of	O
a	O
hard	B-Device
disk	I-Device
,	O
to	O
store	O
files	O
.	O
</s>
<s>
It	O
is	O
used	O
in	O
portable	B-Application
devices	I-Application
such	O
as	O
PDAs	B-Application
,	O
USB	O
flash	O
drives	O
,	O
and	O
removable	O
memory	B-Device
cards	I-Device
used	O
in	O
digital	B-Device
cameras	I-Device
and	O
cellphones	O
.	O
</s>
<s>
Early	O
computer	B-General_Concept
memory	I-General_Concept
consisted	O
of	O
magnetic-core	O
memory	O
,	O
as	O
early	O
solid-state	O
electronic	O
semiconductors	O
,	O
including	O
transistors	B-Application
such	O
as	O
the	O
bipolar	O
junction	O
transistor	B-Application
(	O
BJT	O
)	O
,	O
were	O
impractical	O
for	O
use	O
as	O
digital	O
storage	B-General_Concept
elements	O
(	O
memory	B-Algorithm
cells	I-Algorithm
)	O
.	O
</s>
<s>
The	O
earliest	O
semiconductor	B-Architecture
memory	I-Architecture
dates	O
back	O
to	O
the	O
early	O
1960s	O
,	O
with	O
bipolar	O
memory	O
,	O
which	O
used	O
bipolar	O
transistors	B-Application
.	O
</s>
<s>
Bipolar	O
semiconductor	B-Architecture
memory	I-Architecture
made	O
from	O
discrete	O
devices	O
was	O
first	O
shipped	O
by	O
Texas	O
Instruments	O
to	O
the	O
United	O
States	O
Air	O
Force	O
in	O
1961	O
.	O
</s>
<s>
Bipolar	O
memory	O
failed	O
to	O
replace	O
magnetic-core	O
memory	O
because	O
bipolar	O
flip-flop	B-General_Concept
circuits	O
were	O
too	O
large	O
and	O
expensive	O
.	O
</s>
<s>
The	O
advent	O
of	O
the	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MOSFET	B-Architecture
)	O
,	O
invented	O
by	O
Mohamed	O
M	O
.	O
Atalla	O
and	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
,	O
enabled	O
the	O
practical	O
use	O
of	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
transistors	B-Application
as	O
memory	B-Algorithm
cell	I-Algorithm
storage	B-General_Concept
elements	O
,	O
a	O
function	O
previously	O
served	O
by	O
magnetic	O
cores	O
in	O
computer	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
MOS	B-Architecture
memory	I-Architecture
was	O
developed	O
by	O
John	O
Schmidt	O
at	O
Fairchild	O
Semiconductor	O
in	O
1964	O
.	O
</s>
<s>
In	O
addition	O
to	O
higher	O
performance	O
,	O
MOS	B-Architecture
memory	I-Architecture
was	O
cheaper	O
and	O
consumed	O
less	O
power	O
than	O
magnetic-core	O
memory	O
.	O
</s>
<s>
This	O
led	O
to	O
MOSFETs	B-Architecture
eventually	O
replacing	O
magnetic	O
cores	O
as	O
the	O
standard	O
storage	B-General_Concept
elements	O
in	O
computer	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Wood	O
and	O
R	O
.	O
Ball	O
of	O
the	O
Royal	O
Radar	O
Establishment	O
proposed	O
digital	O
storage	B-General_Concept
systems	I-General_Concept
that	O
use	O
CMOS	B-Device
(	O
complementary	O
MOS	O
)	O
memory	B-Algorithm
cells	I-Algorithm
,	O
in	O
addition	O
to	O
MOSFET	B-Architecture
power	O
devices	O
for	O
the	O
power	O
supply	O
,	O
switched	O
cross-coupling	O
,	O
switches	B-Device
and	O
delay-line	O
storage	B-General_Concept
.	O
</s>
<s>
The	O
development	O
of	O
silicon-gate	O
MOS	O
integrated	O
circuit	O
(	O
MOS	O
IC	O
)	O
technology	O
by	O
Federico	O
Faggin	O
at	O
Fairchild	O
in	O
1968	O
enabled	O
the	O
production	O
of	O
MOS	B-Architecture
memory	I-Architecture
chips	O
.	O
</s>
<s>
NMOS	B-Algorithm
memory	O
was	O
commercialized	O
by	O
IBM	O
in	O
the	O
early	O
1970s	O
.	O
</s>
<s>
MOS	B-Architecture
memory	I-Architecture
overtook	O
magnetic	O
core	O
memory	O
as	O
the	O
dominant	O
memory	O
technology	O
in	O
the	O
early	O
1970s	O
.	O
</s>
<s>
The	O
term	O
"	O
memory	O
"	O
when	O
used	O
with	O
reference	O
to	O
computers	O
most	O
often	O
refers	O
to	O
volatile	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
.	O
</s>
<s>
The	O
two	O
main	O
types	O
of	O
volatile	O
RAM	B-Architecture
are	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
and	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
.	O
</s>
<s>
SRAM	O
became	O
an	O
alternative	O
to	O
magnetic-core	O
memory	O
,	O
but	O
required	O
six	O
MOS	B-Architecture
transistors	I-Architecture
for	O
each	O
bit	O
of	O
data	O
.	O
</s>
<s>
Commercial	O
use	O
of	O
SRAM	O
began	O
in	O
1965	O
,	O
when	O
IBM	O
introduced	O
their	O
SP95	O
SRAM	O
chip	O
for	O
the	O
System/360	B-Application
Model	I-Application
95	I-Application
.	O
</s>
<s>
Toshiba	O
introduced	O
bipolar	O
DRAM	O
memory	B-Algorithm
cells	I-Algorithm
for	O
its	O
Toscal	O
BC-1411	O
electronic	O
calculator	O
in	O
1965	O
.	O
</s>
<s>
MOS	B-Architecture
technology	I-Architecture
is	O
the	O
basis	O
for	O
modern	O
DRAM	O
.	O
</s>
<s>
In	O
1966	O
,	O
Dr.	O
Robert	O
H	O
.	O
Dennard	O
at	O
the	O
IBM	O
Thomas	O
J	O
.	O
Watson	O
Research	O
Center	O
was	O
working	O
on	O
MOS	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
While	O
examining	O
the	O
characteristics	O
of	O
MOS	B-Architecture
technology	I-Architecture
,	O
he	O
found	O
it	O
was	O
capable	O
of	O
building	O
capacitors	O
,	O
and	O
that	O
storing	O
a	O
charge	O
or	O
no	O
charge	O
on	O
the	O
MOS	O
capacitor	O
could	O
represent	O
the	O
1	O
and	O
0	O
of	O
a	O
bit	O
,	O
while	O
the	O
MOS	B-Architecture
transistor	I-Architecture
could	O
control	O
writing	O
the	O
charge	O
to	O
the	O
capacitor	O
.	O
</s>
<s>
This	O
led	O
to	O
his	O
development	O
of	O
a	O
single-transistor	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
In	O
1967	O
,	O
Dennard	O
filed	O
a	O
patent	O
under	O
IBM	O
for	O
a	O
single-transistor	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
,	O
based	O
on	O
MOS	B-Architecture
technology	I-Architecture
.	O
</s>
<s>
This	O
led	O
to	O
the	O
first	O
commercial	O
DRAM	O
IC	O
chip	O
,	O
the	O
Intel	B-General_Concept
1103	I-General_Concept
,	O
in	O
October	O
1970	O
.	O
</s>
<s>
Synchronous	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
SDRAM	O
)	O
later	O
debuted	O
with	O
the	O
Samsung	B-Application
KM48SL2000	O
chip	O
in	O
1992	O
.	O
</s>
<s>
The	O
term	O
"	O
memory	O
"	O
is	O
also	O
often	O
used	O
to	O
refer	O
to	O
non-volatile	B-General_Concept
memory	I-General_Concept
,	O
specifically	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
It	O
has	O
origins	O
in	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
.	O
</s>
<s>
Programmable	B-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
(	O
PROM	O
)	O
was	O
invented	O
by	O
Wen	O
Tsing	O
Chow	O
in	O
1956	O
,	O
while	O
working	O
for	O
the	O
Arma	O
Division	O
of	O
the	O
American	O
Bosch	O
Arma	O
Corporation	O
.	O
</s>
<s>
In	O
1967	O
,	O
Dawon	O
Kahng	O
and	O
Simon	O
Sze	O
of	O
Bell	O
Labs	O
proposed	O
that	O
the	O
floating	B-Algorithm
gate	I-Algorithm
of	O
a	O
MOS	O
semiconductor	O
device	O
could	O
be	O
used	O
for	O
the	O
cell	O
of	O
a	O
reprogrammable	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
,	O
which	O
led	O
to	O
Dov	O
Frohman	O
of	O
Intel	O
inventing	O
EPROM	B-General_Concept
(	O
erasable	O
PROM	O
)	O
in	O
1971	O
.	O
</s>
<s>
EEPROM	B-General_Concept
(	O
electrically	O
erasable	O
PROM	O
)	O
was	O
developed	O
by	O
Yasuo	O
Tarui	O
,	O
Yutaka	O
Hayashi	O
and	O
Kiyoko	O
Naga	O
at	O
Japan	O
's	O
Ministry	O
of	O
International	O
Trade	O
and	O
Industry	O
(	O
MITI	O
)	O
Electrotechnical	O
Laboratory	O
in	O
1972	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
was	O
invented	O
by	O
Fujio	O
Masuoka	O
at	O
Toshiba	O
in	O
the	O
early	O
1980s	O
.	O
</s>
<s>
Toshiba	O
commercialized	O
NAND	O
flash	B-Device
memory	I-Device
in	O
1987	O
.	O
</s>
