<s>
In	O
electronic	O
design	O
,	O
a	O
semiconductor	B-Architecture
intellectual	I-Architecture
property	I-Architecture
core	I-Architecture
(	O
SIP	O
core	O
)	O
,	O
IP	B-Architecture
core	I-Architecture
,	O
or	O
IP	O
block	O
is	O
a	O
reusable	O
unit	O
of	O
logic	O
,	O
cell	O
,	O
or	O
integrated	O
circuit	O
layout	O
design	O
that	O
is	O
the	O
intellectual	O
property	O
of	O
one	O
party	O
.	O
</s>
<s>
IP	B-Architecture
cores	I-Architecture
can	O
be	O
licensed	O
to	O
another	O
party	O
or	O
owned	O
and	O
used	O
by	O
a	O
single	O
party	O
.	O
</s>
<s>
Designers	O
of	O
application-specific	O
integrated	O
circuits	O
(	O
ASIC	O
)	O
and	O
systems	O
of	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
logic	O
can	O
use	O
IP	B-Architecture
cores	I-Architecture
as	O
building	O
blocks	O
.	O
</s>
<s>
The	O
licensing	O
and	O
use	O
of	O
IP	B-Architecture
cores	I-Architecture
in	O
chip	B-General_Concept
design	I-General_Concept
came	O
into	O
common	O
practice	O
in	O
the	O
1990s	O
.	O
</s>
<s>
There	O
were	O
many	O
licensors	O
and	O
also	O
many	O
foundries	B-Algorithm
competing	O
on	O
the	O
market	O
.	O
</s>
<s>
In	O
2013	O
,	O
the	O
most	O
widely	O
licensed	O
IP	B-Architecture
cores	I-Architecture
are	O
from	O
Arm	O
Holdings	O
(	O
43.2	O
%	O
market	O
share	O
)	O
,	O
Synopsys	O
Inc	O
.	O
(	O
13.9	O
%	O
market	O
share	O
)	O
,	O
Imagination	O
Technologies	O
(	O
9%	O
market	O
share	O
)	O
and	O
Cadence	O
Design	O
Systems	O
(	O
5.1	O
%	O
market	O
share	O
)	O
.	O
</s>
<s>
The	O
use	O
of	O
an	O
IP	B-Architecture
core	I-Architecture
in	O
chip	B-General_Concept
design	I-General_Concept
is	O
comparable	O
to	O
the	O
use	O
of	O
a	O
library	B-Library
for	O
computer	B-General_Concept
programming	I-General_Concept
or	O
a	O
discrete	O
integrated	O
circuit	O
component	O
for	O
printed	O
circuit	O
board	O
design	O
.	O
</s>
<s>
Each	O
is	O
a	O
reusable	O
component	O
of	O
design	O
logic	O
with	O
a	O
defined	O
interface	B-Application
and	O
behavior	O
that	O
has	O
been	O
verified	B-Application
by	O
its	O
creator	O
and	O
is	O
integrated	O
into	O
a	O
larger	O
design	O
.	O
</s>
<s>
IP	B-Architecture
cores	I-Architecture
are	O
commonly	O
offered	O
as	O
synthesizable	O
RTL	O
in	O
a	O
hardware	O
description	O
language	O
such	O
as	O
Verilog	B-Language
or	O
VHDL	B-Language
.	O
</s>
<s>
These	O
are	O
analogous	O
to	O
low-level	B-Language
languages	I-Language
such	O
as	O
C	O
in	O
the	O
field	O
of	O
computer	B-General_Concept
programming	I-General_Concept
.	O
</s>
<s>
IP	B-Architecture
cores	I-Architecture
delivered	O
to	O
chip	O
designers	O
as	O
RTL	O
permit	O
chip	O
designers	O
to	O
modify	O
designs	O
at	O
the	O
functional	O
level	O
,	O
though	O
many	O
IP	O
vendors	O
offer	O
no	O
warranty	O
or	O
support	O
for	O
modified	O
designs	O
.	O
</s>
<s>
IP	B-Architecture
cores	I-Architecture
are	O
also	O
sometimes	O
offered	O
as	O
generic	O
gate-level	O
netlists	O
.	O
</s>
<s>
The	O
netlist	O
is	O
a	O
boolean-algebra	O
representation	O
of	O
the	O
IP	O
's	O
logical	O
function	O
implemented	O
as	O
generic	O
gates	O
or	O
process-specific	O
standard	O
cells	O
.	O
</s>
<s>
An	O
IP	B-Architecture
core	I-Architecture
implemented	O
as	O
generic	O
gates	O
can	O
be	O
compiled	O
for	O
any	O
process	B-Architecture
technology	O
.	O
</s>
<s>
A	O
gate-level	O
netlist	O
is	O
analogous	O
to	O
an	O
assembly	B-Language
code	I-Language
listing	O
in	O
the	O
field	O
of	O
computer	B-General_Concept
programming	I-General_Concept
.	O
</s>
<s>
A	O
netlist	O
gives	O
the	O
IP	B-Architecture
core	I-Architecture
vendor	O
reasonable	O
protection	O
against	O
reverse	O
engineering	O
.	O
</s>
<s>
Hard	O
cores	O
(	O
or	O
hard	O
macros	O
)	O
are	O
analog	O
or	O
digital	O
IP	B-Architecture
cores	I-Architecture
whose	O
function	O
cannot	O
be	O
significantly	O
modified	O
by	O
chip	O
designers	O
.	O
</s>
<s>
These	O
are	O
generally	O
defined	O
as	O
a	O
lower-level	O
physical	O
description	O
that	O
is	O
specific	O
to	O
a	O
particular	O
process	B-Architecture
technology	O
.	O
</s>
<s>
Digital	O
IP	B-Architecture
cores	I-Architecture
are	O
sometimes	O
offered	O
in	O
layout	O
format	O
as	O
well	O
.	O
</s>
<s>
Low-level	O
transistor	O
layouts	O
must	O
obey	O
the	O
target	O
foundry	B-Algorithm
's	O
process	B-Architecture
design	O
rules	O
.	O
</s>
<s>
Therefore	O
,	O
hard	O
cores	O
delivered	O
for	O
one	O
foundry	B-Algorithm
's	O
process	B-Architecture
cannot	O
be	O
easily	O
ported	O
to	O
a	O
different	O
process	B-Architecture
or	O
foundry	B-Algorithm
.	O
</s>
<s>
Merchant	O
foundry	B-Algorithm
operators	O
(	O
such	O
as	O
IBM	O
,	O
Fujitsu	O
,	O
Samsung	B-Application
,	O
TI	O
,	O
etc	O
.	O
)	O
</s>
<s>
offer	O
various	O
hard-macro	O
IP	O
functions	O
built	O
for	O
their	O
own	O
foundry	B-Algorithm
processes	O
,	O
helping	O
to	O
ensure	O
customer	O
lock-in	O
.	O
</s>
<s>
Many	O
of	O
the	O
best	O
known	O
IP	B-Architecture
cores	I-Architecture
are	O
soft	B-Device
microprocessor	I-Device
designs	O
.	O
</s>
<s>
Their	O
instruction	B-General_Concept
sets	I-General_Concept
vary	O
from	O
small	O
8-bit	O
processors	O
,	O
such	O
as	O
the	O
8051	B-Architecture
and	O
PIC	B-Architecture
,	O
to	O
32-bit	O
and	O
64-bit	O
processors	O
such	O
as	O
the	O
ARM	B-Architecture
architectures	I-Architecture
or	O
RISC-V	B-Device
architectures	I-Device
.	O
</s>
<s>
Such	O
processors	O
form	O
the	O
"	O
brains	O
"	O
of	O
many	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
They	O
are	O
usually	O
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
rather	O
than	O
CISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
like	O
x86	B-Operating_System
because	O
less	O
logic	O
is	O
required	O
.	O
</s>
<s>
Further	O
,	O
x86	B-Operating_System
leaders	O
Intel	O
and	O
AMD	O
heavily	O
protect	O
their	O
processor	B-General_Concept
designs	I-General_Concept
 '	O
intellectual	O
property	O
and	O
do	O
n't	O
use	O
this	O
business	O
model	O
for	O
their	O
x86-64	B-Device
lines	O
of	O
microprocessors	B-Architecture
.	O
</s>
<s>
IP	B-Architecture
cores	I-Architecture
are	O
also	O
licensed	O
for	O
various	O
peripheral	O
controllers	O
such	O
as	O
for	O
PCI	O
Express	O
,	O
SDRAM	O
,	O
Ethernet	O
,	O
LCD	B-Device
display	I-Device
,	O
AC'97	O
audio	O
,	O
and	O
USB	B-Protocol
.	O
</s>
<s>
Many	O
of	O
those	O
interfaces	B-Application
require	O
both	O
digital	O
logic	O
and	O
analog	O
IP	B-Architecture
cores	I-Architecture
to	O
drive	O
and	O
receive	O
high	O
speed	O
,	O
high	O
voltage	O
,	O
or	O
high	O
impedance	O
signals	O
outside	O
of	O
the	O
chip	O
.	O
</s>
<s>
"	O
Hardwired	O
"	O
(	O
as	O
opposed	O
to	O
software	O
programmable	O
soft	B-Device
microprocessors	I-Device
described	O
above	O
)	O
digital	O
logic	O
IP	B-Architecture
cores	I-Architecture
are	O
also	O
licensed	O
for	O
fixed	O
functions	O
such	O
as	O
MP3	B-Application
audio	I-Application
decode	O
,	O
3D	O
GPU	B-Architecture
,	O
digital	O
video	O
encode/decode	O
,	O
and	O
other	O
DSP	B-General_Concept
functions	O
such	O
as	O
FFT	O
,	O
DCT	B-General_Concept
,	O
or	O
Viterbi	O
coding	O
.	O
</s>
<s>
IP	B-Architecture
core	I-Architecture
developers	O
and	O
licensors	O
range	O
in	O
size	O
from	O
individuals	O
to	O
multi-billion-dollar	O
corporations	O
.	O
</s>
<s>
A	O
company	O
with	O
such	O
a	O
business	O
model	O
is	O
a	O
fabless	B-Algorithm
semiconductor	I-Algorithm
company	I-Algorithm
,	O
which	O
does	O
n't	O
provide	O
physical	O
chips	O
to	O
its	O
customers	O
but	O
merely	O
facilitates	O
the	O
customer	O
's	O
development	O
of	O
chips	O
by	O
offering	O
certain	O
functional	O
blocks	O
.	O
</s>
<s>
A	O
company	O
wishing	O
to	O
fabricate	O
a	O
complex	O
device	O
may	O
license	O
in	O
the	O
rights	O
to	O
use	O
another	O
company	O
's	O
well-tested	O
functional	O
blocks	O
such	O
as	O
a	O
microprocessor	B-Architecture
,	O
instead	O
of	O
developing	O
their	O
own	O
design	O
,	O
which	O
would	O
require	O
additional	O
time	O
and	O
cost	O
.	O
</s>
<s>
IP	O
hardening	O
is	O
a	O
process	B-Architecture
to	O
re-use	O
proven	O
designs	O
and	O
generate	O
fast	O
time-to-market	O
,	O
low-risk-in-fabrication	O
solutions	O
to	O
provide	O
Intellectual	O
property	O
(	O
IP	O
)	O
(	O
or	O
Silicon	O
intellectual	O
property	O
)	O
of	O
design	O
cores	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	B-General_Concept
)	O
is	O
developed	O
from	O
soft	O
cores	O
of	O
RTL	O
format	O
,	O
and	O
it	O
can	O
be	O
targeted	O
to	O
various	O
technologies	O
or	O
different	O
foundries	B-Algorithm
to	O
yield	O
different	O
implementations	O
.	O
</s>
<s>
The	O
process	B-Architecture
of	O
IP	O
hardening	O
is	O
from	O
soft	O
core	O
to	O
generate	O
re-usable	O
hard	O
(	O
hardware	O
)	O
cores	O
.	O
</s>
<s>
that	O
can	O
pass	O
all	O
the	O
rules	O
required	O
for	O
manufacturing	O
by	O
the	O
specific	O
foundry	B-Algorithm
.	O
</s>
<s>
Since	O
around	O
2000	O
,	O
OpenCores.org	O
has	O
offered	O
various	O
soft	O
cores	O
,	O
mostly	O
written	O
in	O
VHDL	B-Language
and	O
Verilog	B-Language
.	O
</s>
<s>
All	O
of	O
these	O
cores	O
are	O
provided	O
under	O
free	O
and	O
open-source	O
software-license	O
such	O
as	O
GNU	B-License
General	I-License
Public	I-License
License	I-License
or	O
BSD-like	B-Operating_System
licenses	I-Operating_System
.	O
</s>
<s>
Since	O
2010	O
,	O
initiatives	O
such	O
as	O
RISC-V	B-Device
have	O
caused	O
a	O
massive	O
expansion	O
in	O
the	O
number	O
of	O
IP	B-Architecture
cores	I-Architecture
available	O
(	O
almost	O
50	O
by	O
2019	O
)	O
.	O
</s>
