<s>
Scratchpad	B-General_Concept
memory	I-General_Concept
(	O
SPM	O
)	O
,	O
also	O
known	O
as	O
scratchpad	B-General_Concept
,	O
scratchpad	B-General_Concept
RAM	I-General_Concept
or	O
local	O
store	O
in	O
computer	O
terminology	O
,	O
is	O
an	O
internal	O
memory	O
,	O
usually	O
high-speed	O
,	O
used	O
for	O
temporary	O
storage	O
of	O
calculations	O
,	O
data	O
,	O
and	O
other	O
work	O
in	O
progress	O
.	O
</s>
<s>
In	O
reference	O
to	O
a	O
microprocessor	B-Architecture
(	O
or	O
CPU	B-Device
)	O
,	O
scratchpad	B-General_Concept
refers	O
to	O
a	O
special	O
high-speed	O
memory	O
used	O
to	O
hold	O
small	O
items	O
of	O
data	O
for	O
rapid	O
retrieval	O
.	O
</s>
<s>
It	O
is	O
similar	O
to	O
the	O
usage	O
and	O
size	O
of	O
a	O
scratchpad	B-General_Concept
in	O
life	O
:	O
a	O
pad	O
of	O
paper	O
for	O
preliminary	O
notes	O
or	O
sketches	O
or	O
writings	O
,	O
etc	O
.	O
</s>
<s>
When	O
the	O
scratchpad	B-General_Concept
is	O
a	O
hidden	O
portion	O
of	O
the	O
main	O
memory	O
then	O
it	O
is	O
sometimes	O
referred	O
to	O
as	O
bump	O
storage	O
.	O
</s>
<s>
In	O
some	O
systems	O
it	O
can	O
be	O
considered	O
similar	O
to	O
the	O
L1	O
cache	O
in	O
that	O
it	O
is	O
the	O
next	O
closest	O
memory	O
to	O
the	O
ALU	B-General_Concept
after	O
the	O
processor	B-General_Concept
registers	I-General_Concept
,	O
with	O
explicit	O
instructions	O
to	O
move	O
data	O
to	O
and	O
from	O
main	O
memory	O
,	O
often	O
using	O
DMA-based	O
data	O
transfer	O
.	O
</s>
<s>
In	O
contrast	O
to	O
a	O
system	O
that	O
uses	O
caches	O
,	O
a	O
system	O
with	O
scratchpads	B-General_Concept
is	O
a	O
system	O
with	O
non-uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
(	O
NUMA	B-Operating_System
)	O
latencies	O
,	O
because	O
the	O
memory	O
access	O
latencies	O
to	O
the	O
different	O
scratchpads	B-General_Concept
and	O
the	O
main	O
memory	O
vary	O
.	O
</s>
<s>
Another	O
difference	O
from	O
a	O
system	O
that	O
employs	O
caches	O
is	O
that	O
a	O
scratchpad	B-General_Concept
commonly	O
does	O
not	O
contain	O
a	O
copy	O
of	O
data	O
that	O
is	O
also	O
stored	O
in	O
the	O
main	O
memory	O
.	O
</s>
<s>
Scratchpads	B-General_Concept
are	O
employed	O
for	O
simplification	O
of	O
caching	O
logic	O
,	O
and	O
to	O
guarantee	O
a	O
unit	O
can	O
work	O
without	O
main	O
memory	O
contention	O
in	O
a	O
system	O
employing	O
multiple	O
processors	O
,	O
especially	O
in	O
multiprocessor	B-General_Concept
system-on-chip	I-General_Concept
for	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
They	O
are	O
mostly	O
suited	O
for	O
storing	O
temporary	O
results	O
(	O
as	O
it	O
would	O
be	O
found	O
in	O
the	O
CPU	B-Device
stack	O
)	O
that	O
typically	O
would	O
n't	O
need	O
to	O
always	O
be	O
committing	O
to	O
the	O
main	O
memory	O
;	O
however	O
when	O
fed	O
by	O
DMA	B-General_Concept
,	O
they	O
can	O
also	O
be	O
used	O
in	O
place	O
of	O
a	O
cache	O
for	O
mirroring	O
the	O
state	O
of	O
slower	O
main	O
memory	O
.	O
</s>
<s>
The	O
same	O
issues	O
of	O
locality	B-General_Concept
of	I-General_Concept
reference	I-General_Concept
apply	O
in	O
relation	O
to	O
efficiency	O
of	O
use	O
;	O
although	O
some	O
systems	O
allow	O
strided	O
DMA	B-General_Concept
to	O
access	O
rectangular	O
data	O
sets	O
.	O
</s>
<s>
Another	O
difference	O
is	O
that	O
scratchpads	B-General_Concept
are	O
explicitly	O
manipulated	O
by	O
applications	O
.	O
</s>
<s>
They	O
may	O
be	O
useful	O
for	O
realtime	B-General_Concept
applications	I-General_Concept
,	O
where	O
predictable	O
timing	O
is	O
hindered	O
by	O
cache	O
behavior	O
.	O
</s>
<s>
Scratchpads	B-General_Concept
are	O
not	O
used	O
in	O
mainstream	O
desktop	O
processors	O
where	O
generality	O
is	O
required	O
for	O
legacy	B-Device
software	I-Device
to	O
run	O
from	O
generation	O
to	O
generation	O
,	O
in	O
which	O
the	O
available	O
on-chip	O
memory	O
size	O
may	O
change	O
.	O
</s>
<s>
They	O
are	O
better	O
implemented	O
in	O
embedded	B-Architecture
systems	I-Architecture
,	O
special-purpose	O
processors	O
and	O
game	O
consoles	O
,	O
where	O
chips	O
are	O
often	O
manufactured	O
as	O
MPSoC	B-General_Concept
,	O
and	O
where	O
software	O
is	O
often	O
tuned	O
to	O
one	O
hardware	O
configuration	O
.	O
</s>
<s>
Fairchild	B-General_Concept
F8	I-General_Concept
of	O
1975	O
contained	O
64	O
bytes	O
of	O
scratchpad	B-General_Concept
.	O
</s>
<s>
Cyrix	B-General_Concept
6x86	I-General_Concept
is	O
the	O
only	O
x86-compatible	O
desktop	O
processor	O
to	O
incorporate	O
a	O
dedicated	O
scratchpad	B-General_Concept
.	O
</s>
<s>
SuperH	O
,	O
used	O
in	O
Sega	O
's	O
consoles	O
,	O
could	O
lock	O
cachelines	O
to	O
an	O
address	O
outside	O
of	O
main	O
memory	O
for	O
use	O
as	O
a	O
scratchpad	B-General_Concept
.	O
</s>
<s>
Sony	O
's	O
PS1	B-Device
's	O
R3000	B-Device
had	O
a	O
scratchpad	B-General_Concept
instead	O
of	O
an	O
L1	O
cache	O
.	O
</s>
<s>
It	O
was	O
possible	O
to	O
place	O
the	O
CPU	B-Device
stack	O
here	O
,	O
an	O
example	O
of	O
the	O
temporary	O
workspace	O
usage	O
.	O
</s>
<s>
Adapteva	B-Application
's	I-Application
Epiphany	I-Application
parallel	O
coprocessor	B-General_Concept
features	O
local-stores	O
for	O
each	O
core	O
,	O
connected	O
by	O
a	O
network	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
,	O
with	O
DMA	B-General_Concept
possible	O
between	O
them	O
and	O
off-chip	O
links	O
(	O
possibly	O
to	O
DRAM	O
)	O
.	O
</s>
<s>
The	O
architecture	O
is	O
similar	O
to	O
Sony	O
's	O
Cell	B-General_Concept
,	O
except	O
all	O
cores	O
can	O
directly	O
address	O
each	O
other	O
's	O
scratchpads	B-General_Concept
,	O
generating	O
network	O
messages	O
from	O
standard	O
load/store	O
instructions	O
.	O
</s>
<s>
Sony	O
's	O
PS2	B-Device
Emotion	B-Architecture
Engine	I-Architecture
includes	O
a	O
16KB	O
scratchpad	B-General_Concept
,	O
to	O
and	O
from	O
which	O
DMA	B-General_Concept
transfers	O
could	O
be	O
issued	O
to	O
its	O
GS	O
,	O
and	O
main	O
memory	O
.	O
</s>
<s>
Cell	B-General_Concept
's	O
SPEs	O
are	O
restricted	O
purely	O
to	O
working	O
in	O
their	O
"	O
local-store	O
"	O
,	O
relying	O
on	O
DMA	B-General_Concept
for	O
transfers	O
from/to	O
main	O
memory	O
and	O
between	O
local	O
stores	O
,	O
much	O
like	O
a	O
scratchpad	B-General_Concept
.	O
</s>
<s>
Most	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
use	O
a	O
scratchpad	B-General_Concept
.	O
</s>
<s>
Many	O
past	O
3D	B-Architecture
accelerators	I-Architecture
and	O
game	O
consoles	O
(	O
including	O
the	O
PS2	B-Device
)	O
have	O
used	O
DSPs	O
for	O
vertex	O
transformations	O
.	O
</s>
<s>
This	O
differs	O
from	O
the	O
stream-based	O
approach	O
of	O
modern	O
GPUs	B-Architecture
which	O
have	O
more	O
in	O
common	O
with	O
a	O
CPU	B-General_Concept
cache	I-General_Concept
's	O
functions	O
.	O
</s>
<s>
NVIDIA	O
's	O
8800	O
GPU	B-Architecture
running	O
under	O
CUDA	B-Architecture
provides	O
16KB	O
of	O
scratchpad	B-General_Concept
(	O
NVIDIA	O
calls	O
it	O
Shared	O
Memory	O
)	O
per	O
thread-bundle	O
when	O
being	O
used	O
for	O
GPGPU	B-Architecture
tasks	O
.	O
</s>
<s>
Scratchpad	B-General_Concept
also	O
was	O
used	O
in	O
later	O
Fermi	B-General_Concept
GPU	I-General_Concept
(	O
GeForce	O
400	O
Series	O
)	O
.	O
</s>
<s>
Ageia	O
's	O
PhysX	B-Operating_System
chip	O
includes	O
a	O
scratchpad	B-General_Concept
RAM	I-General_Concept
in	O
a	O
manner	O
similar	O
to	O
the	O
Cell	B-General_Concept
;	O
the	O
theory	O
of	O
this	O
specific	O
physics	O
processing	O
unit	O
is	O
that	O
a	O
cache	O
hierarchy	O
is	O
of	O
less	O
use	O
than	O
software	O
managed	O
physics	O
and	O
collision	O
calculations	O
.	O
</s>
<s>
Intel	O
's	O
Knights	O
Landing	O
processor	O
has	O
a	O
16GB	O
MCDRAM	O
that	O
can	O
be	O
configured	O
as	O
either	O
a	O
cache	O
,	O
scratchpad	B-General_Concept
memory	I-General_Concept
,	O
or	O
divided	O
into	O
some	O
cache	O
and	O
some	O
scratchpad	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Movidius	B-General_Concept
Myriad	I-General_Concept
2	I-General_Concept
,	O
a	O
vision	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
,	O
organized	O
as	O
a	O
multicore	O
architecture	O
with	O
a	O
large	O
multiported	O
shared	O
scratchpad	B-General_Concept
.	O
</s>
<s>
Some	O
architectures	O
such	O
as	O
PowerPC	O
attempt	O
to	O
avoid	O
the	O
need	O
for	O
cacheline	O
locking	O
or	O
scratchpads	B-General_Concept
through	O
the	O
use	O
of	O
cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
.	O
</s>
<s>
Marking	O
an	O
area	O
of	O
memory	O
with	O
"	O
Data	B-General_Concept
Cache	I-General_Concept
Block	O
:	O
Zero	O
"	O
(	O
allocating	O
a	O
line	O
but	O
setting	O
its	O
contents	O
to	O
zero	O
instead	O
of	O
loading	O
from	O
main	O
memory	O
)	O
and	O
discarding	O
it	O
after	O
use	O
( 	O
 '	O
Data	B-General_Concept
Cache	I-General_Concept
Block	O
:	O
Invalidate	O
 '	O
,	O
signaling	O
that	O
main	O
memory	O
did	O
n't	O
receive	O
any	O
updated	O
data	O
)	O
the	O
cache	O
is	O
made	O
to	O
behave	O
as	O
a	O
scratchpad	B-General_Concept
.	O
</s>
<s>
Regarding	O
interprocessor	O
communication	O
in	O
a	O
multicore	O
setup	O
,	O
there	O
are	O
similarities	O
between	O
the	O
Cell	B-General_Concept
's	O
inter-localstore	O
DMA	B-General_Concept
and	O
a	O
shared	O
L2	O
cache	O
setup	O
as	O
in	O
the	O
Intel	O
Core	O
2	O
Duo	O
or	O
the	O
Xbox	O
360	O
's	O
custom	O
powerPC	O
:	O
the	O
L2	O
cache	O
allows	O
processors	O
to	O
share	O
results	O
without	O
those	O
results	O
having	O
to	O
be	O
committed	O
to	O
main	O
memory	O
.	O
</s>
<s>
This	O
can	O
be	O
an	O
advantage	O
where	O
the	O
working	B-General_Concept
set	I-General_Concept
for	O
an	O
algorithm	O
encompasses	O
the	O
entirety	O
of	O
the	O
L2	O
cache	O
.	O
</s>
<s>
However	O
,	O
when	O
a	O
program	O
is	O
written	O
to	O
take	O
advantage	O
of	O
inter-localstore	O
DMA	B-General_Concept
,	O
the	O
Cell	B-General_Concept
has	O
the	O
benefit	O
of	O
each-other-Local-Store	O
serving	O
the	O
purpose	O
of	O
BOTH	O
the	O
private	O
workspace	O
for	O
a	O
single	O
processor	O
AND	O
the	O
point	O
of	O
sharing	O
between	O
processors	O
;	O
i.e.	O
,	O
the	O
other	O
Local	O
Stores	O
are	O
on	O
a	O
similar	O
footing	O
viewed	O
from	O
one	O
processor	O
as	O
the	O
shared	O
L2	O
cache	O
in	O
a	O
conventional	O
chip	O
.	O
</s>
