<s>
SciEngines	B-Device
GmbH	I-Device
is	O
a	O
privately	O
owned	O
company	O
founded	O
2007	O
as	O
a	O
spin-off	O
of	O
the	O
COPACOBANA	B-General_Concept
project	O
by	O
the	O
Universities	O
of	O
Bochum	O
and	O
Kiel	O
,	O
both	O
in	O
Germany	O
.	O
</s>
<s>
The	O
project	O
intended	O
to	O
create	O
a	O
platform	O
for	O
an	O
affordable	O
Custom	B-General_Concept
hardware	I-General_Concept
attack	I-General_Concept
.	O
</s>
<s>
COPACOBANA	B-General_Concept
is	O
a	O
massively-parallel	O
reconfigurable	B-Architecture
computer	I-Architecture
.	O
</s>
<s>
It	O
consists	O
of	O
120	O
commercially	O
available	O
,	O
reconfigurable	O
integrated	O
circuits	O
(	O
FPGAs	B-Architecture
)	O
.	O
</s>
<s>
Since	O
2007	O
,	O
SciEngines	B-Device
GmbH	I-Device
has	O
enhanced	O
and	O
developed	O
successors	O
of	O
COPACOBANA	B-General_Concept
.	O
</s>
<s>
Furthermore	O
,	O
the	O
COPACOBANA	B-General_Concept
has	O
become	O
a	O
well	O
known	O
reference	O
platform	O
for	O
cryptanalysis	O
and	O
custom	B-General_Concept
hardware	I-General_Concept
based	O
attacks	O
to	O
symmetric	O
,	O
asymmetric	O
cyphers	O
and	O
stream	B-Algorithm
ciphers	I-Algorithm
.	O
</s>
<s>
2008	O
attacks	O
against	O
A5/1	B-Algorithm
stream	I-Algorithm
cipher	I-Algorithm
an	O
encryption	O
system	O
been	O
used	O
to	O
encrypt	O
voice	O
streams	O
in	O
GSM	O
have	O
been	O
published	O
as	O
the	O
first	O
known	O
real	O
world	O
attack	O
utilizing	O
off-the-shelf	O
custom	B-General_Concept
hardware	I-General_Concept
.	O
</s>
<s>
Currently	O
SciEngines	O
RIVYERA	O
holds	O
the	O
record	O
in	O
brute-force	O
breaking	O
DES	O
utilizing	O
128	O
Spartan-3	O
5000	O
FPGAs	B-Architecture
.	O
</s>
<s>
Current	O
systems	O
provide	O
a	O
unique	O
density	O
of	O
up	O
to	O
256	O
Spartan-6	O
FPGAs	B-Architecture
per	O
single	O
system	O
enabling	O
scientific	O
utilization	O
beyond	O
the	O
field	O
of	O
cryptanalysis	O
,	O
like	O
bioinformatics	O
.	O
</s>
<s>
2008	O
they	O
introduced	O
RIVYERA	O
S3-5000	O
,	O
the	O
direct	O
successor	O
of	O
COPACOBANA	B-General_Concept
5000	O
and	O
COPACOBANA	B-General_Concept
.	O
</s>
<s>
The	O
RIVYERA	O
architecture	O
introduced	O
a	O
new	O
high	O
performance	O
optimized	O
bus	O
system	O
and	O
a	O
fully	O
API	B-Application
encapsulated	O
communication	O
framework	O
.	O
</s>
<s>
2011	O
they	O
introduced	O
256	O
User	O
usable	O
FPGAs	B-Architecture
per	O
RIVYERA	O
S6-LX150	O
computer	O
.	O
</s>
<s>
Providing	O
a	O
standard	O
off-the-shelf	O
Intel	O
CPU	O
and	O
mainboard	O
integrated	O
into	O
the	O
FPGA	B-Architecture
computer	O
RIVYERA	O
systems	O
allow	O
to	O
execute	O
most	O
standard	O
code	O
without	O
modifications	O
.	O
</s>
<s>
SciEngines	O
aims	O
that	O
programmers	O
only	O
have	O
to	O
focus	O
on	O
porting	O
the	O
most	O
time-consuming	O
5%	O
of	O
their	O
code	O
to	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
Therefore	O
,	O
they	O
bundle	O
an	O
Eclipse	B-Application
like	O
development	O
environment	O
which	O
allows	O
code	O
implementation	O
in	O
hardware	O
based	O
implementation	O
languages	O
e.g.	O
</s>
<s>
VHDL	B-Language
,	O
Verilog	B-Language
as	O
well	O
as	O
in	O
C	B-Language
based	O
languages	O
.	O
</s>
<s>
An	O
Application	B-Application
Programming	I-Application
Interface	I-Application
in	O
C	B-Language
,	O
C++	B-Language
,	O
Java	B-Language
and	O
Fortran	B-Application
allow	O
scientists	O
and	O
programmers	O
to	O
adopt	O
their	O
code	O
to	O
benefit	O
from	O
an	O
application-specific	O
hardware	O
architecture	O
.	O
</s>
