<s>
Sapphire	B-Device
Rapids	I-Device
is	O
a	O
codename	B-Architecture
for	O
Intel	O
's	O
server	O
(	O
fourth	O
generation	O
Xeon	B-Device
Scalable	O
)	O
and	O
workstation	O
processors	O
based	O
on	O
Intel	B-Algorithm
7	I-Algorithm
.	O
</s>
<s>
Server	O
Sapphire	B-Device
Rapids	I-Device
is	O
part	O
of	O
the	O
Eagle	O
Stream	O
platform	O
and	O
will	O
be	O
powering	O
Aurora	B-Device
,	O
an	O
exascale	B-General_Concept
supercomputer	B-Architecture
in	O
the	O
United	O
States	O
,	O
at	O
Argonne	O
National	O
Laboratory	O
.	O
</s>
<s>
Sapphire	B-Device
Rapids	I-Device
has	O
been	O
a	O
long-standing	O
Intel	O
project	O
in	O
development	O
for	O
over	O
five	O
years	O
and	O
has	O
been	O
subjected	O
to	O
many	O
delays	O
.	O
</s>
<s>
Sapphire	B-Device
Rapids	I-Device
was	O
first	O
announced	O
by	O
Intel	O
at	O
their	O
Investor	O
Meeting	O
in	O
May	O
2019	O
with	O
the	O
intention	O
of	O
Sapphire	B-Device
Rapids	I-Device
succeeding	O
Ice	B-Device
Lake	I-Device
in	O
2021	O
.	O
</s>
<s>
Intel	O
again	O
announced	O
details	O
on	O
Sapphire	B-Device
Rapids	I-Device
in	O
their	O
August	O
2021	O
Architecture	O
Day	O
presentation	O
with	O
no	O
mention	O
of	O
a	O
launch	O
date	O
.	O
</s>
<s>
Sapphire	B-Device
Rapids	I-Device
was	O
originally	O
scheduled	O
for	O
a	O
launch	O
in	O
the	O
first	O
half	O
of	O
2022	O
.	O
</s>
<s>
Processors	O
designated	O
as	O
MCC	O
(	O
Medium	O
Core	B-Device
Count	O
)	O
are	O
built	O
using	O
large	O
monolithic	O
dies	O
that	O
contains	O
up	O
to	O
32	O
cores	B-Architecture
.	O
</s>
<s>
Processors	O
designated	O
as	O
XCC	O
(	O
Extreme	O
Core	B-Device
Count	O
)	O
feature	O
multi-die	B-Algorithm
packaging	O
with	O
four	O
tiles	O
linked	O
by	O
2.5D	O
Embedded	O
Multi-die	B-Algorithm
Interconnect	O
Bridges	O
.	O
</s>
<s>
Each	O
tile	O
is	O
a	O
400mm2	O
SoC	B-Architecture
,	O
providing	O
both	O
compute	O
cores	B-Architecture
and	O
I/O	O
.	O
</s>
<s>
Select	O
Xeon	B-Device
Gold	O
and	O
all	O
Xeon	B-Device
Platinum	I-Device
and	O
Xeon	B-Device
Max	O
processors	O
are	O
designated	O
as	O
XCC	O
.	O
</s>
<s>
A	O
tile	O
provides	O
up	O
to	O
32	O
PCIe	O
5.0	O
lanes	O
,	O
but	O
one	O
of	O
the	O
eight	O
PCIe	O
controllers	O
of	O
a	O
CPU	O
is	O
usually	O
reserved	O
for	O
DMI	B-Architecture
,	O
resulting	O
in	O
a	O
maximum	O
of	O
112	O
non-chipset	O
lanes	O
.	O
</s>
<s>
With	O
its	O
maximum	O
of	O
60	O
cores	B-Architecture
,	O
Sapphire	O
Rapids-SP	O
competes	O
with	O
AMD	O
's	O
EPYC	O
Genoa	O
with	O
up	O
to	O
96	O
cores	B-Architecture
.	O
</s>
<s>
Sapphire	B-Device
Rapids	I-Device
Xeon	B-Device
server	O
products	O
are	O
scalable	O
from	O
single-socket	O
configurations	O
up	O
to	O
8	O
socket	O
configurations	O
.	O
</s>
<s>
With	O
its	O
maximum	O
of	O
56	O
cores	B-Architecture
,	O
Sapphire	O
Rapids-WS	O
competes	O
with	O
AMD	O
's	O
Threadripper	O
Pro	O
5000WX	O
with	O
up	O
to	O
64	O
cores	B-Architecture
.	O
</s>
<s>
Like	O
Intel	O
's	O
Core	B-Device
product	O
segmentation	O
into	O
i3	O
,	O
i5	O
,	O
i7	O
and	O
i9	O
,	O
Sapphire	O
Rapids-WS	O
is	O
labeled	O
Xeon	B-Device
w3	O
,	O
w5	O
,	O
w7	O
and	O
w9	O
.	O
</s>
<s>
CPUs	O
with	O
"	O
X	O
"	O
suffix	O
have	O
its	O
multiplier	O
unlocked	O
for	O
overclocking	B-Application
.	O
</s>
