<s>
The	O
ST6	B-Device
and	I-Device
ST7	I-Device
are	O
8-bit	O
microcontroller	B-Architecture
product	O
lines	O
from	O
STMicroelectronics	O
.	O
</s>
<s>
Both	O
have	O
an	O
8-bit	O
accumulator	B-General_Concept
used	O
for	O
most	O
operations	O
,	O
plus	O
two	O
8-bit	O
index	O
registers	O
(	O
X	O
and	O
Y	O
)	O
used	O
for	O
memory	O
addressing	O
.	O
</s>
<s>
The	O
ST6	O
is	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
with	O
an	O
8-bit	O
(	O
256	O
byte	O
)	O
data	O
address	O
space	O
and	O
a	O
separate	O
12-bit	O
(	O
4096	O
byte	O
)	O
program	O
space	O
.	O
</s>
<s>
The	O
ST6	O
's	O
addressing	B-Language
modes	I-Language
are	O
limited	O
to	O
immediate	O
,	O
8-bit	O
absolute	O
memory	O
address	O
,	O
and	O
register	O
indirect	O
modes	O
(	O
X	O
)	O
and	O
(	O
Y	O
)	O
.	O
</s>
<s>
The	O
ST7	O
is	O
a	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
with	O
a	O
single	O
16-bit	O
(	O
64	O
kiB	O
)	O
address	O
space	O
.	O
</s>
<s>
The	O
first	O
256	O
bytes	O
of	O
RAM	B-Architecture
(	O
the	O
zero	B-General_Concept
page	I-General_Concept
)	O
have	O
extra	O
flexibility	O
.	O
</s>
<s>
Its	O
registers	O
are	O
not	O
memory-mapped	O
,	O
and	O
it	O
uses	O
general-purpose	O
RAM	B-Architecture
(	O
plus	O
a	O
stack	O
pointer	O
register	O
)	O
for	O
subroutine	O
calls	O
.	O
</s>
<s>
The	O
ST7	O
supports	O
a	O
wide	O
variety	O
of	O
addressing	B-Language
modes	I-Language
,	O
including	O
base+index	O
and	O
double-indirect	O
.	O
</s>
<s>
The	O
ST6	O
has	O
64	O
bytes	O
of	O
RAM	B-Architecture
and	O
4096	O
bytes	O
of	O
program	O
ROM	B-Device
.	O
</s>
<s>
Larger	O
amounts	O
are	O
accessed	O
by	O
bank-switching	B-General_Concept
the	O
low	O
2K	O
section	O
of	O
the	O
ROM	B-Device
.	O
</s>
<s>
The	O
RAM	B-Architecture
address	O
space	O
is	O
actually	O
256	O
bytes	O
,	O
divided	O
as	O
follows	O
:	O
</s>
<s>
64127	O
:	O
Bank-switchable	O
window	O
into	O
program	O
ROM	B-Device
and	O
data	O
EPROM	B-General_Concept
.	O
</s>
<s>
The	O
accumulator	B-General_Concept
is	O
mapped	O
at	O
address	O
255	O
,	O
but	O
is	O
more	O
commonly	O
addressed	O
implicitly	O
.	O
</s>
<s>
There	O
are	O
only	O
two	O
status	O
bits	O
(	O
carry	B-Algorithm
and	O
zero	B-Algorithm
)	O
,	O
and	O
they	O
are	O
banked	O
based	O
on	O
processor	O
mode	O
,	O
with	O
separate	O
status	O
bits	O
for	O
normal	O
,	O
interrupt	O
and	O
non-maskable	B-General_Concept
interrupt	I-General_Concept
operation	O
.	O
</s>
<s>
The	O
first	O
four	O
general-purpose	O
RAM	B-Architecture
locations	O
are	O
also	O
known	O
as	O
the	O
X	O
,	O
Y	O
,	O
V	O
and	O
W	O
registers	O
,	O
and	O
some	O
instructions	O
can	O
access	O
them	O
using	O
special	O
short	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
The	O
X	O
and	O
Y	O
registers	O
serve	O
as	O
index	O
registers	O
,	O
and	O
can	O
use	O
indirect	B-Language
addressing	I-Language
modes	O
(	O
X	O
)	O
and	O
(	O
Y	O
)	O
.	O
</s>
<s>
reg	O
1	O
1	O
1	O
1	O
0	O
1	O
—	O
—	O
LD	O
reg	O
,	O
A	O
Z	O
{	O
X	O
,	O
Y	O
,	O
V	O
or	O
W}	O
:=	O
A	O
opcode	O
0	O
1	O
1	O
0	O
1	O
—	O
—	O
Miscellaneous	O
operations	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
1	O
addr	O
imm8	O
LDI	O
addr	O
,	O
imm8	O
Set	O
RAM	B-Architecture
to	O
8-bit	O
immediate	O
value	O
1	O
0	O
0	O
0	O
1	O
1	O
0	O
1	O
—	O
—	O
(	O
reserved	O
)	O
0	O
1	O
0	O
0	O
1	O
1	O
0	O
1	O
—	O
—	O
RETI	O
Return	O
from	O
interrupt	O
.	O
</s>
<s>
—	O
ALU	O
operations	O
with	O
RAM	B-Architecture
or	O
immediate	O
opcode	O
0	O
0	O
1	O
1	O
1	O
—	O
—	O
(	O
X	O
)	O
Operand	O
is	O
(	O
X	O
)	O
opcode	O
0	O
1	O
1	O
1	O
1	O
—	O
—	O
(	O
Y	O
)	O
Operand	O
is	O
(	O
Y	O
)	O
opcode	O
1	O
0	O
1	O
1	O
1	O
imm8	O
—	O
imm8	O
Operand	O
is	O
8-bit	O
immediate	O
(	O
source	O
only	O
)	O
opcode	O
1	O
1	O
1	O
1	O
1	O
addr	O
—	O
addr	O
Operand	O
is	O
8-bit	O
RAM	B-Architecture
address	O
0	O
0	O
0	O
src	O
1	O
1	O
1	O
?	O
</s>
<s>
†	O
:	O
^	O
a	O
b	O
Confusingly	O
,	O
different	O
models	O
of	O
the	O
ST6	O
family	O
use	O
different	O
conventions	O
for	O
the	O
value	O
of	O
the	O
carry	B-Algorithm
bit	I-Algorithm
after	O
a	O
subtraction	O
.	O
</s>
<s>
ST60	O
processors	O
use	O
the	O
"	O
carry	B-Algorithm
"	O
convention	O
,	O
which	O
clears	O
the	O
bit	O
if	O
the	O
subtract	O
underflows	O
,	O
while	O
the	O
ST62	O
and	O
ST63	O
processors	O
use	O
the	O
"	O
borrow	O
"	O
convention	O
,	O
which	O
sets	O
the	O
bit	O
in	O
that	O
case	O
.	O
</s>
<s>
The	O
ST7	O
has	O
six	O
registers	O
:	O
the	O
accumulator	B-General_Concept
,	O
X	O
and	O
Y	O
index	O
registers	O
,	O
stack	O
pointer	O
,	O
program	O
counter	O
,	O
and	O
condition	O
code	O
register	O
.	O
</s>
<s>
Also	O
,	O
double-indirect	O
addressing	O
allows	O
the	O
zero	B-General_Concept
page	I-General_Concept
of	O
RAM	B-Architecture
to	O
serve	O
as	O
additional	O
registers	O
.	O
</s>
<s>
Two-operand	O
instructions	O
use	O
the	O
accumulator	B-General_Concept
as	O
the	O
first	O
source	O
.	O
</s>
<s>
The	O
addressing	B-Language
mode	I-Language
specifies	O
the	O
second	O
source	O
,	O
which	O
may	O
be	O
:	O
</s>
<s>
The	O
destination	O
is	O
usually	O
the	O
accumulator	B-General_Concept
,	O
but	O
a	O
few	O
instructions	O
modify	O
the	O
second	O
source	O
.	O
</s>
<s>
This	O
allows	O
(	O
Y	O
)	O
,	O
(	O
address8	O
,	O
Y	O
)	O
and	O
(	O
address16	O
,	O
Y	O
)	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
A	O
consequence	O
of	O
this	O
is	O
that	O
load	O
X	O
can	O
only	O
use	O
the	O
X-relative	O
addressing	B-Language
modes	I-Language
,	O
and	O
load	O
Y	O
can	O
only	O
use	O
the	O
Y-relative	O
ones	O
.	O
</s>
<s>
This	O
allows	O
(	O
address8	O
)	O
,	O
(	O
address16	O
)	O
,	O
( [	O
address8 ]	O
,	O
X	O
)	O
and	O
( [	O
address8.w	O
]	O
,	O
X	O
)	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
This	O
allows	O
the	O
( [	O
address8 ]	O
,	O
Y	O
)	O
and	O
( [	O
address8.w	O
]	O
,	O
Y	O
)	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
Bit	O
operations	O
0	O
0	O
0	O
0	O
bit	O
0	O
addr8	O
soff8	O
BTJT	O
addr8	O
,	O
#bit	O
,	O
label	O
Jump	O
to	O
PC	O
+	O
soff8	O
if	O
source	O
bit	O
is	O
true	O
(	O
set	O
)	O
0	O
0	O
0	O
0	O
bit	O
1	O
addr8	O
soff8	O
BTJF	O
addr8	O
,	O
#bit	O
,	O
label	O
Jump	O
to	O
PC	O
+	O
soff8	O
if	O
source	O
bit	O
is	O
false	O
(	O
clear	O
)	O
0	O
0	O
0	O
1	O
bit	O
0	O
addr8	O
—	O
BSET	O
addr8	O
,	O
#bit	O
Set	O
specified	O
bit	O
to	O
1	O
0	O
0	O
0	O
1	O
bit	O
1	O
addr8	O
—	O
BRES	O
addr8	O
,	O
#bit	O
Reset	O
(	O
clear	O
)	O
specified	O
bit	O
to	O
0	O
0	O
0	O
1	O
0	O
condition	O
soff8	O
—	O
Conditional	O
branches	O
(	O
8-bit	O
relative	O
offset	O
)	O
0	O
0	O
1	O
0	O
0	O
0	O
0	O
0	O
soff8	O
—	O
JRA	O
label	O
Branch	O
always	O
(	O
true	O
)	O
0	O
0	O
1	O
0	O
0	O
0	O
0	O
1	O
soff8	O
—	O
JRF	O
label	O
Branch	O
never	O
(	O
false	O
)	O
0	O
0	O
1	O
0	O
0	O
0	O
1	O
0	O
soff8	O
—	O
JRUGT	O
label	O
Branch	O
if	O
unsigned	O
greater	O
than	O
(	O
C	O
=	O
0	O
and	O
Z	O
=	O
0	O
)	O
0	O
0	O
1	O
0	O
0	O
0	O
1	O
1	O
soff8	O
—	O
JRULE	O
label	O
Branch	O
if	O
unsigned	O
less	O
than	O
or	O
equal	O
(	O
C	O
=	O
1	O
or	O
Z	O
=	O
1	O
)	O
0	O
0	O
1	O
0	O
0	O
1	O
0	O
0	O
soff8	O
—	O
JRNC	O
label	O
Branch	O
if	O
no	O
carry	B-Algorithm
(	O
C	O
=	O
0	O
)	O
0	O
0	O
1	O
0	O
0	O
1	O
0	O
1	O
soff8	O
—	O
JRC	O
label	O
Branch	O
if	O
carry	B-Algorithm
(	O
C	O
=	O
1	O
)	O
0	O
0	O
1	O
0	O
0	O
1	O
1	O
0	O
soff8	O
—	O
JRNE	O
label	O
Branch	O
if	O
not	O
equal	O
(	O
Z	O
=	O
0	O
)	O
0	O
0	O
1	O
0	O
0	O
1	O
1	O
1	O
soff8	O
—	O
JREQ	O
label	O
Branch	O
if	O
equal	O
(	O
Z	O
=	O
1	O
)	O
0	O
0	O
1	O
0	O
1	O
0	O
0	O
0	O
soff8	O
—	O
JRNH	O
label	O
Branch	O
if	O
not	O
half-carry	O
(	O
H	O
=	O
0	O
)	O
0	O
0	O
1	O
0	O
1	O
0	O
0	O
1	O
soff8	O
—	O
JRH	O
label	O
Branch	O
if	O
half-carry	O
(	O
H	O
=	O
1	O
)	O
0	O
0	O
1	O
0	O
1	O
0	O
1	O
0	O
soff8	O
—	O
JRPL	O
label	O
Branch	O
if	O
plus	O
(	O
N	O
=	O
0	O
)	O
0	O
0	O
1	O
0	O
1	O
0	O
1	O
1	O
soff8	O
—	O
JRMI	O
label	O
Branch	O
if	O
minus	O
(	O
N	O
=	O
1	O
)	O
0	O
0	O
1	O
0	O
1	O
1	O
0	O
0	O
soff8	O
—	O
JRNM	O
label	O
Branch	O
if	O
not	O
interrupt	O
mask	O
(	O
M	O
=	O
0	O
)	O
0	O
0	O
1	O
0	O
1	O
1	O
0	O
1	O
soff8	O
—	O
JRM	O
label	O
Branch	O
if	O
interrupts	O
masked	O
(	O
M	O
=	O
1	O
)	O
0	O
0	O
1	O
0	O
1	O
1	O
1	O
0	O
soff8	O
—	O
JRIL	O
label	O
Branch	O
if	O
interrupt	O
line	O
is	O
low	O
0	O
0	O
1	O
0	O
1	O
1	O
1	O
1	O
soff8	O
—	O
JRIH	O
label	O
Branch	O
if	O
interrupt	O
line	O
is	O
high	O
0	O
mode	O
opcode	O
?	O
</s>
<s>
—	O
One-operand	O
instructions	O
0	O
0	O
1	O
1	O
opcode	O
addr8	O
—	O
OP	O
addr8	O
8-bit	O
absolute	O
address	O
0	O
1	O
0	O
0	O
opcode	O
—	O
—	O
OP	O
A	O
Accumulator	B-General_Concept
0	O
1	O
0	O
1	O
opcode	O
—	O
—	O
OP	O
X	O
X	O
register	O
(	O
Y	O
register	O
with	O
prefix	O
)	O
0	O
1	O
1	O
0	O
opcode	O
addr8	O
—	O
OP	O
(	O
addr8	O
,	O
X	O
)	O
8-bit	O
address	O
plus	O
X	O
0	O
1	O
1	O
1	O
opcode	O
—	O
—	O
OP	O
(	O
X	O
)	O
Indexed	O
with	O
no	O
offset	O
0	O
mode	O
0	O
0	O
0	O
0	O
?	O
</s>
<s>
Msbit	O
cleared	O
,	O
lsbit	O
to	O
carry	B-Algorithm
.	O
</s>
<s>
—	O
RRC	O
operand	O
Rotate	O
right	O
through	O
carry	B-Algorithm
,	O
(	O
operand:C	O
)	O
:=	O
(	O
C:operand	O
)	O
0	O
mode	O
0	O
1	O
1	O
1	O
?	O
</s>
<s>
Msbit	O
preserved	O
,	O
lebit	O
to	O
carry	B-Algorithm
.	O
</s>
<s>
Msbit	O
to	O
carry	B-Algorithm
.	O
</s>
<s>
—	O
RLC	O
operand	O
Rotate	O
left	O
through	O
carry	B-Algorithm
.	O
</s>
<s>
(	O
N	O
and	O
Z	O
set	O
,	O
carry	B-Algorithm
unaffected	O
)	O
0	O
mode	O
1	O
0	O
1	O
1	O
?	O
</s>
<s>
(	O
N	O
and	O
Z	O
set	O
,	O
carry	B-Algorithm
unaffected	O
)	O
0	O
mode	O
1	O
1	O
0	O
1	O
?	O
</s>
<s>
—	O
TNZ	O
operand	O
Test	O
non-zero	O
.	O
</s>
<s>
1	O
0	O
0	O
1	O
1	O
0	O
0	O
0	O
—	O
—	O
RCF	O
Reset	O
(	O
clear	O
)	O
carry	B-Algorithm
flag	I-Algorithm
1	O
0	O
0	O
1	O
1	O
0	O
0	O
1	O
—	O
—	O
SCF	O
Set	O
carry	B-Algorithm
flag	I-Algorithm
1	O
0	O
0	O
1	O
1	O
0	O
1	O
0	O
—	O
—	O
RIM	O
Reset	O
interrupt	O
mask	O
(	O
enable	O
interrupts	O
)	O
1	O
0	O
0	O
1	O
1	O
0	O
1	O
1	O
—	O
—	O
SIM	O
Set	O
interrupt	O
mask	O
(	O
disable	O
interrupts	O
)	O
1	O
0	O
0	O
1	O
1	O
1	O
0	O
0	O
—	O
—	O
RSP	O
Reset	O
stack	O
pointer	O
(	O
to	O
top	O
of	O
RAM	B-Architecture
)	O
1	O
0	O
0	O
1	O
1	O
1	O
0	O
1	O
—	O
—	O
NOP	O
No	O
operation	O
.	O
</s>
<s>
ADC	O
A	O
,	O
operand	O
A	O
:=	O
A	O
+	O
operand	O
+	O
C	O
,	O
add	O
with	O
carry	B-Algorithm
1	O
mode	O
1	O
0	O
1	O
0	O
value	O
?	O
</s>
