<s>
The	O
SSE5	B-General_Concept
(	O
short	O
for	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
version	I-General_Concept
5	I-General_Concept
)	O
was	O
a	O
SIMD	B-Device
instruction	O
set	O
extension	O
proposed	O
by	O
AMD	O
on	O
August	O
30	O
,	O
2007	O
as	O
a	O
supplement	O
to	O
the	O
128-bit	O
SSE	B-General_Concept
core	O
instructions	O
in	O
the	O
AMD64	B-Device
architecture	O
.	O
</s>
<s>
AMD	O
chose	O
not	O
to	O
implement	O
SSE5	B-General_Concept
as	O
originally	O
proposed	O
.	O
</s>
<s>
In	O
May	O
2009	O
,	O
AMD	O
replaced	O
SSE5	B-General_Concept
with	O
three	O
smaller	O
instruction	O
set	O
extensions	O
named	O
as	O
XOP	B-General_Concept
,	O
FMA4	B-General_Concept
,	O
and	O
F16C	B-Device
,	O
which	O
retain	O
the	O
proposed	O
functionality	O
of	O
SSE5	B-General_Concept
,	O
but	O
encode	O
the	O
instructions	O
differently	O
for	O
better	O
compatibility	O
with	O
Intel	O
's	O
proposed	O
AVX	B-General_Concept
instruction	O
set	O
.	O
</s>
<s>
The	O
three	O
SSE5-derived	O
instruction	O
sets	O
were	O
introduced	O
in	O
the	O
Bulldozer	O
processor	O
core	O
,	O
released	O
in	O
October	O
2011	O
on	O
a	O
32	O
nm	O
process	O
.	O
</s>
<s>
AMD	O
's	O
SSE5	B-General_Concept
extension	O
bundle	O
does	O
not	O
include	O
the	O
full	O
set	O
of	O
Intel	O
's	O
SSE4	B-General_Concept
instructions	O
,	O
making	O
it	O
a	O
competitor	O
to	O
SSE4	B-General_Concept
rather	O
than	O
a	O
successor	O
.	O
</s>
<s>
The	O
proposed	O
SSE5	B-General_Concept
instruction	O
set	O
consisted	O
of	O
170	O
instructions	O
(	O
including	O
46	O
base	O
instructions	O
)	O
,	O
many	O
of	O
which	O
are	O
designed	O
to	O
improve	O
single-threaded	O
performance	O
.	O
</s>
<s>
Some	O
SSE5	B-General_Concept
instructions	O
are	O
3-operand	O
instructions	O
,	O
the	O
use	O
of	O
which	O
will	O
increase	O
the	O
average	O
number	O
of	O
instructions	O
per	O
cycle	O
achievable	O
by	O
x86	B-Operating_System
code	O
.	O
</s>
<s>
AMD	O
claims	O
SSE5	B-General_Concept
will	O
provide	O
dramatic	O
performance	O
improvements	O
,	O
particularly	O
in	O
high-performance	B-Architecture
computing	I-Architecture
(	O
HPC	O
)	O
,	O
multimedia	O
,	O
and	O
computer	O
security	O
applications	O
,	O
including	O
a	O
5x	O
performance	O
gain	O
for	O
Advanced	B-Algorithm
Encryption	I-Algorithm
Standard	I-Algorithm
(	O
AES	B-Algorithm
)	O
encryption	O
and	O
a	O
30%	O
performance	O
gain	O
for	O
discrete	B-General_Concept
cosine	I-General_Concept
transform	I-General_Concept
(	O
DCT	B-General_Concept
)	O
used	O
to	O
process	O
video	O
streams	O
.	O
</s>
<s>
FMA3	B-General_Concept
:	O
Floating-point	O
vector	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
.	O
</s>
<s>
F16C	B-Device
:	O
Half-precision	O
floating-point	O
conversion	O
.	O
</s>
<s>
The	O
SSE5	B-General_Concept
specification	O
included	O
a	O
proposed	O
extension	O
to	O
the	O
general	O
coding	O
scheme	O
of	O
x86	B-Device
instructions	I-Device
in	O
order	O
to	O
allow	O
instructions	O
to	O
have	O
more	O
than	O
two	O
operands	O
.	O
</s>
<s>
In	O
2008	O
,	O
Intel	O
announced	O
their	O
planned	O
AVX	B-General_Concept
instruction	O
set	O
which	O
proposed	O
a	O
different	O
way	O
of	O
coding	O
instructions	O
with	O
more	O
than	O
two	O
operands	O
.	O
</s>
<s>
The	O
two	O
proposed	O
coding	O
schemes	O
,	O
SSE5	B-General_Concept
and	O
AVX	B-General_Concept
,	O
are	O
mutually	O
incompatible	O
,	O
although	O
the	O
AVX	B-General_Concept
scheme	O
has	O
certain	O
advantages	O
over	O
the	O
SSE5	B-General_Concept
scheme	O
:	O
most	O
importantly	O
,	O
AVX	B-General_Concept
has	O
plenty	O
of	O
space	O
for	O
future	O
extensions	O
,	O
including	O
larger	O
vector	O
sizes	O
.	O
</s>
<s>
This	O
revision	O
changes	O
the	O
coding	O
scheme	O
to	O
make	O
it	O
compatible	O
with	O
the	O
AVX	B-General_Concept
scheme	O
,	O
but	O
with	O
a	O
differing	O
prefix	O
byte	O
in	O
order	O
to	O
avoid	O
overlap	O
between	O
instructions	O
introduced	O
by	O
AMD	O
and	O
instructions	O
introduced	O
by	O
Intel	O
.	O
</s>
<s>
The	O
revised	O
instruction	O
set	O
no	O
longer	O
carries	O
the	O
name	O
SSE5	B-General_Concept
,	O
which	O
has	O
been	O
criticized	O
for	O
being	O
misleading	O
,	O
but	O
most	O
of	O
the	O
instructions	O
in	O
the	O
new	O
revision	O
are	O
functionally	O
identical	O
to	O
the	O
original	O
SSE5	B-General_Concept
specification	O
—	O
only	O
the	O
way	O
the	O
instructions	O
are	O
coded	O
differs	O
.	O
</s>
<s>
XOP	B-General_Concept
:	O
Integer	O
vector	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
instructions	O
,	O
integer	O
vector	O
horizontal	O
addition	O
,	O
integer	O
vector	O
compare	O
,	O
shift	O
and	O
rotate	O
instructions	O
,	O
byte	O
permutation	O
and	O
conditional	O
move	O
instructions	O
,	O
floating	O
point	O
fraction	O
extraction	O
.	O
</s>
<s>
FMA4	B-General_Concept
:	O
Floating-point	O
vector	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
.	O
</s>
<s>
F16C	B-Device
:	O
Half-precision	O
floating-point	O
conversion	O
.	O
</s>
