<s>
SSE4	B-General_Concept
(	O
Streaming	O
SIMD	B-Device
Extensions	O
4	O
)	O
is	O
a	O
SIMD	B-Device
CPU	O
instruction	B-General_Concept
set	I-General_Concept
used	O
in	O
the	O
Intel	B-Device
Core	I-Device
microarchitecture	I-Device
and	O
AMD	O
K10	O
(	O
K8L	O
)	O
.	O
</s>
<s>
SSE4	B-General_Concept
is	O
fully	O
compatible	O
with	O
software	O
written	O
for	O
previous	O
generations	O
of	O
Intel	O
64	O
and	O
IA-32	O
architecture	O
microprocessors	O
.	O
</s>
<s>
All	O
existing	O
software	O
continues	O
to	O
run	O
correctly	O
without	O
modification	O
on	O
microprocessors	O
that	O
incorporate	O
SSE4	B-General_Concept
,	O
as	O
well	O
as	O
in	O
the	O
presence	O
of	O
existing	O
and	O
new	O
applications	O
that	O
incorporate	O
SSE4	B-General_Concept
.	O
</s>
<s>
Intel	O
SSE4	B-General_Concept
consists	O
of	O
54	O
instructions	O
.	O
</s>
<s>
A	O
subset	O
consisting	O
of	O
47	O
instructions	O
,	O
referred	O
to	O
as	O
SSE4.1	O
in	O
some	O
Intel	O
documentation	O
,	O
is	O
available	O
in	O
Penryn	B-Device
.	O
</s>
<s>
Additionally	O
,	O
SSE4.2	O
,	O
a	O
second	O
subset	O
consisting	O
of	O
the	O
7	O
remaining	O
instructions	O
,	O
is	O
first	O
available	O
in	O
Nehalem-based	O
Core	B-Device
i7	I-Device
.	O
</s>
<s>
Intel	O
credits	O
feedback	O
from	O
developers	O
as	O
playing	O
an	O
important	O
role	O
in	O
the	O
development	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Starting	O
with	O
Barcelona-based	O
processors	O
,	O
AMD	O
introduced	O
the	O
SSE4a	O
instruction	B-General_Concept
set	I-General_Concept
,	O
which	O
has	O
4	O
SSE4	B-General_Concept
instructions	O
and	O
4	O
new	O
SSE	O
instructions	O
.	O
</s>
<s>
These	O
instructions	O
are	O
not	O
found	O
in	O
Intel	O
's	O
processors	O
supporting	O
SSE4.1	O
and	O
AMD	O
processors	O
only	O
started	O
supporting	O
Intel	O
's	O
SSE4.1	O
and	O
SSE4.2	O
(	O
the	O
full	O
SSE4	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
)	O
in	O
the	O
Bulldozer-based	O
FX	O
processors	O
.	O
</s>
<s>
Intel	O
later	O
introduced	O
similar	O
speed	O
improvements	O
to	O
unaligned	O
SSE	O
in	O
their	O
Nehalem	B-Device
processors	O
,	O
but	O
did	O
not	O
introduce	O
misaligned	O
access	O
by	O
non-load	O
SSE	O
instructions	O
until	O
AVX	B-General_Concept
.	O
</s>
<s>
What	O
is	O
now	O
known	O
as	O
SSSE3	B-General_Concept
(	O
Supplemental	O
Streaming	O
SIMD	B-Device
Extensions	O
3	O
)	O
,	O
introduced	O
in	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
processor	O
line	O
,	O
was	O
referred	O
to	O
as	O
SSE4	B-General_Concept
by	O
some	O
media	O
until	O
Intel	O
came	O
up	O
with	O
the	O
SSSE3	B-General_Concept
moniker	O
.	O
</s>
<s>
Internally	O
dubbed	O
Merom	B-General_Concept
New	I-General_Concept
Instructions	I-General_Concept
,	O
Intel	O
originally	O
did	O
not	O
plan	O
to	O
assign	O
a	O
special	O
name	O
to	O
them	O
,	O
which	O
was	O
criticized	O
by	O
some	O
journalists	O
.	O
</s>
<s>
Intel	O
eventually	O
cleared	O
up	O
the	O
confusion	O
and	O
reserved	O
the	O
SSE4	B-General_Concept
name	O
for	O
their	O
next	O
instruction	B-General_Concept
set	I-General_Concept
extension	O
.	O
</s>
<s>
Intel	O
is	O
using	O
the	O
marketing	O
term	O
HD	B-General_Concept
Boost	I-General_Concept
to	O
refer	O
to	O
SSE4	B-General_Concept
.	O
</s>
<s>
Unlike	O
all	O
previous	O
iterations	O
of	O
SSE	O
,	O
SSE4	B-General_Concept
contains	O
instructions	O
that	O
execute	O
operations	O
which	O
are	O
not	O
specific	O
to	O
multimedia	O
applications	O
.	O
</s>
<s>
Several	O
of	O
these	O
instructions	O
are	O
enabled	O
by	O
the	O
single-cycle	O
shuffle	O
engine	O
in	O
Penryn	B-Device
.	O
</s>
<s>
These	O
instructions	O
were	O
introduced	O
with	O
Penryn	B-Device
microarchitecture	I-Device
,	O
the	O
45nm	O
shrink	O
of	O
Intel	O
's	O
Core	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Instruction	O
Description	O
MPSADBW	O
Compute	O
eight	O
offset	O
sums	O
of	O
absolute	O
differences	O
,	O
four	O
at	O
a	O
time	O
(	O
i.e.	O
,	O
|x0−y0|+|x1−y1|+|x2−y2|+|x3−y3|	O
,	O
|x0−y1|+|x1−y2|+|x2−y3|+|x3−y4|	O
,	O
...	O
,	O
|x0−y7|+|x1−y8|+|x2−y9|+|x3−y10|	O
)	O
;	O
this	O
operation	O
is	O
important	O
for	O
some	O
HD	O
codecs	B-General_Concept
,	O
and	O
allows	O
an	O
8×8	O
block	O
difference	O
to	O
be	O
computed	O
in	O
fewer	O
than	O
seven	O
cycles.Motion	O
Estimation	O
with	O
Intel	O
Streaming	O
SIMD	B-Device
Extensions	O
4	O
(	O
Intel	O
SSE4	B-General_Concept
)	O
,	O
Intel	O
.	O
</s>
<s>
PMOVSXBW	O
,	O
PMOVZXBW	O
,	O
PMOVSXBD	O
,	O
PMOVZXBD	O
,	O
PMOVSXBQ	O
,	O
PMOVZXBQ	O
,	O
PMOVSXWD	O
,	O
PMOVZXWD	O
,	O
PMOVSXWQ	O
,	O
PMOVZXWQ	O
,	O
PMOVSXDQ	O
,	O
PMOVZXDQ	O
Packed	O
sign/zero	O
extension	O
to	O
wider	O
types	O
PTEST	O
This	O
is	O
similar	O
to	O
the	O
TEST	O
instruction	O
,	O
in	O
that	O
it	O
sets	O
the	O
Z	B-Algorithm
flag	I-Algorithm
to	O
the	O
result	O
of	O
an	O
AND	O
between	O
its	O
operands	O
:	O
ZF	O
is	O
set	O
,	O
if	O
DEST	O
AND	O
SRC	O
is	O
equal	O
to	O
0	O
.	O
</s>
<s>
This	O
is	O
equivalent	O
to	O
setting	O
the	O
Z	B-Algorithm
flag	I-Algorithm
if	O
none	O
of	O
the	O
bits	O
masked	O
by	O
SRC	O
are	O
set	O
,	O
and	O
the	O
C	O
flag	O
if	O
all	O
of	O
the	O
bits	O
masked	O
by	O
SRC	O
are	O
set	O
.	O
</s>
<s>
SSE4.2	O
added	O
STTNI	O
(	O
String	O
and	O
Text	O
New	O
Instructions	O
)	O
,	O
several	O
new	O
instructions	O
that	O
perform	O
character	O
searches	O
and	O
comparison	O
on	O
two	O
operands	O
of	O
16	O
bytes	O
at	O
a	O
time	O
.	O
</s>
<s>
These	O
were	O
designed	O
(	O
among	O
other	O
things	O
)	O
to	O
speed	O
up	O
the	O
parsing	O
of	O
XML	B-Protocol
documents	I-Protocol
.	O
</s>
<s>
These	O
instructions	O
were	O
first	O
implemented	O
in	O
the	O
Nehalem-based	O
Intel	B-Device
Core	I-Device
i7	I-Device
product	O
line	O
and	O
complete	O
the	O
SSE4	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Instruction	O
Description	O
CRC32	O
Accumulate	O
CRC32C	O
value	O
using	O
the	O
polynomial	O
0x11EDC6F41	O
(	O
or	O
,	O
without	O
the	O
high	O
order	O
bit	O
,	O
0x1EDC6F41	O
)	O
.Intel	O
SSE4	B-General_Concept
Programming	O
Reference	O
p	O
.	O
61	O
.	O
</s>
<s>
These	O
instructions	O
operate	O
on	O
integer	O
rather	O
than	O
SSE	O
registers	O
,	O
because	O
they	O
are	O
not	O
SIMD	B-Device
instructions	O
,	O
but	O
appear	O
at	O
the	O
same	O
time	O
and	O
although	O
introduced	O
by	O
AMD	O
with	O
the	O
SSE4a	O
instruction	B-General_Concept
set	I-General_Concept
,	O
they	O
are	O
counted	O
as	O
separate	O
extensions	O
with	O
their	O
own	O
dedicated	O
CPUID	O
bits	O
to	O
indicate	O
support	O
.	O
</s>
<s>
Intel	O
implements	O
POPCNT	O
beginning	O
with	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
and	O
LZCNT	B-Algorithm
beginning	O
with	O
the	O
Haswell	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Support	O
is	O
indicated	O
via	O
the	O
CPUID.01H:ECX.POPCNT	O
[ Bit	O
23 ]	O
flag.Intel	O
®	O
64	O
and	O
IA-32	O
Architectures	O
Software	O
Developer	O
's	O
Manual	O
,	O
Volume	O
2B	O
:	O
Instruction	B-General_Concept
Set	I-General_Concept
Reference	O
,	O
N	O
–	O
Z	O
.	O
</s>
<s>
LZCNT	B-Algorithm
Leading	B-Algorithm
zero	I-Algorithm
count	I-Algorithm
.	O
</s>
<s>
The	O
encoding	O
of	O
LZCNT	B-Algorithm
takes	O
the	O
same	O
encoding	O
path	O
as	O
the	O
encoding	O
of	O
the	O
BSR	O
(	O
bit	B-Algorithm
scan	I-Algorithm
reverse	I-Algorithm
)	O
instruction	O
.	O
</s>
<s>
This	O
results	O
in	O
an	O
issue	O
where	O
LZCNT	B-Algorithm
called	O
on	O
some	O
CPUs	O
not	O
supporting	O
it	O
,	O
such	O
as	O
Intel	O
CPUs	O
prior	O
to	O
Haswell	B-Device
,	O
may	O
incorrectly	O
execute	O
the	O
BSR	O
operation	O
instead	O
of	O
raising	O
an	O
invalid	O
instruction	O
exception	O
.	O
</s>
<s>
This	O
is	O
an	O
issue	O
as	O
the	O
result	O
values	O
of	O
LZCNT	B-Algorithm
and	O
BSR	O
are	O
different	O
.	O
</s>
<s>
Trailing	O
zeros	O
can	O
be	O
counted	O
using	O
the	O
BSF	O
(	O
bit	B-Algorithm
scan	I-Algorithm
forward	I-Algorithm
)	O
or	O
TZCNT	O
instructions	O
.	O
</s>
