<s>
SSE3	B-General_Concept
,	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
3	O
,	O
also	O
known	O
by	O
its	O
Intel	O
code	O
name	O
Prescott	B-General_Concept
New	I-General_Concept
Instructions	I-General_Concept
(	O
PNI	O
)	O
,	O
is	O
the	O
third	O
iteration	O
of	O
the	O
SSE	B-General_Concept
instruction	O
set	O
for	O
the	O
IA-32	B-Device
(	O
x86	B-Operating_System
)	O
architecture	O
.	O
</s>
<s>
Intel	O
introduced	O
SSE3	B-General_Concept
in	O
early	O
2004	O
with	O
the	O
Prescott	O
revision	O
of	O
their	O
Pentium	B-General_Concept
4	I-General_Concept
CPU	O
.	O
</s>
<s>
In	O
April	O
2005	O
,	O
AMD	O
introduced	O
a	O
subset	O
of	O
SSE3	B-General_Concept
in	O
revision	O
E	O
(	O
Venice	O
and	O
San	O
Diego	O
)	O
of	O
their	O
Athlon	O
64	O
CPUs	O
.	O
</s>
<s>
The	O
earlier	O
SIMD	B-Device
instruction	O
sets	O
on	O
the	O
x86	B-Operating_System
platform	O
,	O
from	O
oldest	O
to	O
newest	O
,	O
are	O
MMX	B-Architecture
,	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
(	O
developed	O
by	O
AMD	O
,	O
no	O
longer	O
supported	O
on	O
newer	O
CPUs	O
)	O
,	O
SSE	B-General_Concept
,	O
and	O
SSE2	B-General_Concept
.	O
</s>
<s>
SSE3	B-General_Concept
contains	O
13	O
new	O
instructions	O
over	O
SSE2	B-General_Concept
.	O
</s>
<s>
The	O
most	O
notable	O
change	O
is	O
the	O
capability	O
to	O
work	O
horizontally	O
in	O
a	O
register	O
,	O
as	O
opposed	O
to	O
the	O
more	O
or	O
less	O
strictly	O
vertical	O
operation	O
of	O
all	O
previous	O
SSE	B-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
These	O
instructions	O
can	O
be	O
used	O
to	O
speed	O
up	O
the	O
implementation	O
of	O
a	O
number	O
of	O
DSP	B-General_Concept
and	O
3D	O
operations	O
.	O
</s>
<s>
There	O
is	O
also	O
a	O
new	O
instruction	O
to	O
convert	O
floating	O
point	O
values	O
to	O
integers	O
without	O
having	O
to	O
change	O
the	O
global	O
rounding	O
mode	O
,	O
thus	O
avoiding	O
costly	O
pipeline	B-General_Concept
stalls	O
.	O
</s>
<s>
Finally	O
,	O
the	O
extension	O
adds	O
LDDQU	O
,	O
an	O
alternative	O
misaligned	O
integer	O
vector	O
load	O
that	O
has	O
better	O
performance	O
on	O
NetBurst	B-Device
based	O
platforms	O
for	O
loads	O
that	O
cross	O
cacheline	O
boundaries	O
.	O
</s>
