<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
(	O
Sun	O
4/40	O
,	O
code-named	O
Phoenix	O
)	O
is	O
a	O
workstation	B-Device
sold	O
by	O
Sun	O
Microsystems	O
,	O
introduced	O
July	O
1990	O
.	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
incorporates	O
a	O
25MHz	O
Fujitsu	O
MB86901A	O
or	O
LSI	O
L64801	O
processor	O
.	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
is	O
limited	O
to	O
use	O
as	O
a	O
single-processor	O
machine	O
.	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
has	O
twelve	O
SIMM	O
memory	O
slots	O
,	O
in	O
three	O
4-slot	O
groups	O
.	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
can	O
hold	O
one	O
internal	O
3.5	O
"	O
,	O
50-pin	O
,	O
single	O
ended	O
,	O
fast-narrow	O
SE	O
SCSI	B-Architecture
disk	O
drive	O
and	O
a	O
3.5	O
"	O
1.44	O
MB	O
floppy	O
drive	O
.	O
</s>
<s>
It	O
also	O
supports	O
external	O
SCSI	B-Architecture
devices	O
.	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
has	O
the	O
following	O
interfaces	O
:	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
comes	O
with	O
an	O
on-board	O
AMD	O
Lance	O
Ethernet	O
chipset	O
and	O
a	O
15-pin	O
AUI	B-Protocol
connector	O
,	O
which	O
can	O
connect	O
to	O
10BASE2	O
,	O
10BASE5	O
or	O
10BASE-T	B-Protocol
via	O
an	O
appropriate	O
transceiver	B-Protocol
.	O
</s>
<s>
Like	O
all	O
other	O
SPARCstation	B-Device
systems	O
,	O
the	O
IPC	O
holds	O
system	O
information	O
such	O
as	O
MAC	O
address	O
and	O
serial	O
number	O
in	O
NVRAM	O
.	O
</s>
<s>
The	O
SPARCstation	B-Architecture
IPC	I-Architecture
uses	O
an	O
M48T02	O
battery-backed	O
RTC	O
with	O
RAM	O
chip	O
which	O
handles	O
the	O
real	O
time	O
clock	O
and	O
boot	O
parameter	O
storage	O
.	O
</s>
<s>
As	O
all	O
SPARCstation	B-Architecture
IPCs	I-Architecture
made	O
are	O
now	O
older	O
than	O
the	O
battery	O
life	O
of	O
this	O
chip	O
,	O
a	O
substantial	O
number	O
of	O
these	O
systems	O
now	O
refuse	O
to	O
boot	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
SPARCstation	B-Architecture
IPC	I-Architecture
design	O
used	O
the	O
reserved	O
bits	O
in	O
the	O
M48T02	O
's	O
NVRAM	O
in	O
a	O
non-standard	O
way	O
;	O
since	O
later	O
revisions	O
of	O
the	O
M48T02	O
chip	O
exert	O
stricter	O
control	O
over	O
these	O
bits	O
,	O
a	O
current	O
M48T02	O
will	O
store	O
the	O
NVRAM	O
data	O
,	O
but	O
the	O
RTC	O
will	O
not	O
function	O
correctly	O
and	O
the	O
system	O
may	O
fail	O
to	O
auto-boot	O
.	O
</s>
<s>
The	O
following	O
operating	O
systems	O
will	O
run	O
on	O
a	O
SPARCstation	B-Architecture
IPC	I-Architecture
:	O
</s>
<s>
The	O
SPARCstation	B-Architecture
1+	I-Architecture
(	O
Sun	O
4/65	O
)	O
is	O
architecturally	O
very	O
similar	O
but	O
housed	O
in	O
a	O
pizza	B-General_Concept
box	I-General_Concept
form	I-General_Concept
factor	I-General_Concept
.	O
</s>
<s>
The	O
SPARCstation	B-Operating_System
IPX	I-Operating_System
(	O
Sun	O
4/50	O
)	O
is	O
a	O
later	O
lunchbox	O
form	O
factor	O
system	O
.	O
</s>
