<s>
The	O
SPARC	B-Device
T4	I-Device
is	O
a	O
SPARC	B-Architecture
multicore	B-Architecture
microprocessor	I-Architecture
introduced	O
in	O
2011	O
by	O
Oracle	B-Application
Corporation	I-Application
.	O
</s>
<s>
The	O
processor	O
is	O
designed	O
to	O
offer	O
high	O
multithreaded	B-General_Concept
performance	O
(	O
8	O
threads	O
per	O
core	O
,	O
with	O
8	O
cores	O
per	O
chip	O
)	O
,	O
as	O
well	O
as	O
high	O
single	O
threaded	O
performance	O
from	O
the	O
same	O
chip	O
.	O
</s>
<s>
Sun	O
Microsystems	O
brought	O
the	O
first	O
T-Series	O
processor	O
(	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
)	O
to	O
market	O
in	O
2005	O
.	O
</s>
<s>
The	O
chip	O
is	O
the	O
first	O
Sun/Oracle	O
SPARC	B-Architecture
chip	O
to	O
use	O
dynamic	O
threading	O
and	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
It	O
incorporates	O
one	O
floating	B-Algorithm
point	I-Algorithm
unit	O
and	O
one	O
dedicated	O
cryptographic	O
unit	O
per	O
core	O
.	O
</s>
<s>
The	O
cores	O
use	O
the	O
64-bit	O
SPARC	B-Architecture
Version	O
9	O
architecture	O
running	O
at	O
frequencies	O
between	O
2.85GHz	O
and	O
3.0GHz	O
,	O
and	O
are	O
built	O
in	O
a	O
40nm	O
process	O
with	O
a	O
die	O
size	O
of	O
.	O
</s>
<s>
The	O
online	O
technology	O
website	O
The	O
Register	O
speculated	O
that	O
this	O
chip	O
would	O
be	O
named	O
"	O
T4	O
"	O
,	O
being	O
the	O
successor	O
to	O
the	O
SPARC	B-Device
T3	I-Device
.	O
</s>
<s>
The	O
Yosemite	O
Falls	O
CPU	O
product	O
remained	O
on	O
Oracle	B-Application
Corporation	I-Application
's	O
processor	O
roadmap	O
after	O
the	O
company	O
took	O
over	O
Sun	O
in	O
early	O
2010	O
.	O
</s>
<s>
In	O
December	O
2010	O
the	O
T4	O
processor	O
was	O
confirmed	O
by	O
Oracle	B-Application
's	O
VP	O
of	O
hardware	O
development	O
to	O
be	O
designed	O
for	O
improved	O
per-thread	O
performance	O
,	O
with	O
eight	O
cores	O
,	O
and	O
with	O
an	O
expected	O
release	O
within	O
one	O
year	O
.	O
</s>
<s>
The	O
cores	O
(	O
renamed	O
"	O
S3	O
"	O
from	O
"	O
VT	O
"	O
)	O
included	O
a	O
dual-issue	O
16	O
stage	O
integer	O
pipeline	B-General_Concept
,	O
and	O
11-cycle	O
floating	B-Algorithm
point	I-Algorithm
pipeline	B-General_Concept
,	O
both	O
giving	O
improvements	O
over	O
the	O
previous	O
(	O
"	O
S2	O
"	O
)	O
core	O
used	O
in	O
the	O
SPARC	B-Device
T3	I-Device
processor	O
.	O
</s>
<s>
The	O
design	O
was	O
the	O
first	O
Sun/Oracle	O
SPARC	B-Architecture
processor	O
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
and	O
was	O
the	O
first	O
processor	O
in	O
the	O
SPARC	B-Architecture
T-Series	I-Architecture
family	O
to	O
include	O
the	O
ability	O
to	O
issue	O
more	O
than	O
one	O
instruction	O
per	O
cycle	O
to	O
a	O
core	O
's	O
execution	O
units	O
.	O
</s>
<s>
The	O
T4	O
processor	O
was	O
officially	O
introduced	O
as	O
part	O
of	O
Oracle	B-Architecture
's	I-Architecture
SPARC	I-Architecture
T4	I-Architecture
servers	I-Architecture
in	O
September	O
2011	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
S3	O
core	O
also	O
include	O
a	O
thread	O
priority	O
mechanism	O
(	O
called	O
"	O
dynamic	O
threading	O
"	O
)	O
whereby	O
each	O
thread	O
is	O
allocated	O
resources	O
based	O
on	O
need	O
,	O
giving	O
increased	O
performance	O
.	O
</s>
<s>
Shared	O
resources	O
include	O
branch	B-General_Concept
prediction	I-General_Concept
structures	O
,	O
various	O
buffer	O
entries	O
,	O
and	O
out-of-order	B-General_Concept
execution	I-General_Concept
resources	O
.	O
</s>
<s>
The	O
implementation	O
is	O
designed	O
to	O
achieve	O
wire	O
speed	O
encryption	O
and	O
decryption	O
on	O
the	O
SPARC	B-Device
T4	I-Device
's	O
10-Gbit/s	O
Ethernet	O
ports	O
.	O
</s>
