<s>
The	O
SPARC64	B-Device
V	I-Device
(	O
Zeus	O
)	O
is	O
a	O
SPARC	B-Architecture
V9	I-Architecture
microprocessor	B-Architecture
designed	O
by	O
Fujitsu	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
was	O
the	O
basis	O
for	O
a	O
series	O
of	O
successive	O
processors	O
designed	O
for	O
servers	O
,	O
and	O
later	O
,	O
supercomputers	B-Architecture
.	O
</s>
<s>
The	O
servers	O
series	O
are	O
the	O
SPARC64	B-General_Concept
V+	I-General_Concept
,	O
VI	O
,	O
VI+	O
,	O
VII	O
,	O
VII+	O
,	O
X	O
,	O
X+	O
and	O
XII	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VI	I-Device
and	O
its	O
successors	O
up	O
to	O
the	O
VII+	O
were	O
used	O
in	O
the	O
Fujitsu	O
and	O
Sun	O
(	O
later	O
Oracle	B-Application
)	O
SPARC	B-Application
Enterprise	I-Application
M-Series	I-Application
servers	O
.	O
</s>
<s>
In	O
addition	O
to	O
servers	O
,	O
a	O
version	O
of	O
the	O
SPARC64	B-Device
VII	I-Device
was	O
also	O
used	O
in	O
the	O
commercially	O
available	O
Fujitsu	O
FX1	O
supercomputer	B-Architecture
.	O
</s>
<s>
As	O
of	O
October	O
2017	O
,	O
the	O
SPARC64	O
XII	O
is	O
the	O
latest	O
server	O
processor	O
,	O
and	O
it	O
is	O
used	O
in	O
the	O
Fujitsu	O
and	O
Oracle	B-Application
M12	O
servers	O
.	O
</s>
<s>
The	O
supercomputer	B-Architecture
series	O
was	O
based	O
on	O
the	O
SPARC64	B-Device
VII	I-Device
,	O
and	O
are	O
the	O
SPARC64	O
VIIfx	O
,	O
IXfx	O
,	O
and	O
XIfx	O
.	O
</s>
<s>
The	O
SPARC64	O
VIIIfx	O
was	O
used	O
in	O
the	O
K	B-Device
computer	I-Device
,	O
and	O
the	O
SPARC64	O
IXfx	O
in	O
the	O
commercially	O
available	O
PRIMEHPC	O
FX10	O
.	O
</s>
<s>
As	O
of	O
July	O
2016	O
,	O
the	O
SPARC64	O
XIfx	O
is	O
the	O
latest	O
supercomputer	B-Architecture
processor	O
,	O
and	O
it	O
is	O
used	O
in	O
the	O
Fujitsu	O
PRIMEHPC	O
FX100	O
supercomputer	B-Architecture
.	O
</s>
<s>
In	O
the	O
late	O
1990s	O
,	O
HAL	O
Computer	O
Systems	O
,	O
a	O
subsidiary	O
of	O
Fujitsu	O
,	O
was	O
designing	O
a	O
successor	O
to	O
the	O
SPARC64	O
GP	O
as	O
the	O
SPARC64	B-Device
V	I-Device
.	O
First	O
announced	O
at	O
Microprocessor	B-Architecture
Forum	O
1999	O
,	O
the	O
HAL	O
SPARC64	B-Device
V	I-Device
would	O
have	O
operated	O
1GHz	O
and	O
had	O
a	O
wide	O
superscalar	B-General_Concept
organization	O
with	O
superspeculation	B-General_Concept
,	O
an	O
L1	O
instruction	O
trace	B-General_Concept
cache	I-General_Concept
,	O
a	O
small	O
but	O
very	O
fast	O
8KB	O
L1	O
data	O
cache	O
,	O
and	O
separate	O
L2	O
caches	O
for	O
instructions	O
and	O
data	O
.	O
</s>
<s>
The	O
first	O
Fujitsu	O
SPARC64	B-Device
Vs	I-Device
were	O
fabricated	B-Architecture
in	O
December	O
2001	O
.	O
</s>
<s>
Fujitsu	O
's	O
2003	O
SPARC64	O
roadmap	O
showed	O
that	O
the	O
company	O
planned	O
a	O
1.62GHz	O
version	O
for	O
release	O
in	O
late	O
2003	O
or	O
early	O
2004	O
,	O
but	O
it	O
was	O
canceled	O
in	O
favor	O
of	O
the	O
SPARC64	B-General_Concept
V+	I-General_Concept
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
was	O
used	O
by	O
Fujitsu	O
in	O
their	O
PRIMEPOWER	O
servers	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
was	O
first	O
presented	O
at	O
Microprocessor	B-Architecture
Forum	O
2002	O
.	O
</s>
<s>
At	O
introduction	O
,	O
it	O
had	O
the	O
highest	O
clock	O
frequency	O
of	O
both	O
SPARC	B-Architecture
and	O
64-bit	O
server	O
processors	O
in	O
production	O
;	O
and	O
the	O
highest	O
SPEC	O
rating	O
of	O
any	O
SPARC	B-Architecture
processor	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
is	O
a	O
four-issue	O
superscalar	B-General_Concept
microprocessor	B-Architecture
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
It	O
was	O
based	O
on	O
the	O
Fujitsu	O
GS8900	O
mainframe	B-Architecture
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
fetches	O
up	O
to	O
eight	O
instructions	O
from	O
the	O
instruction	O
cache	O
during	O
the	O
first	O
stage	O
and	O
places	O
them	O
into	O
a	O
48-entry	O
instruction	O
buffer	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
has	O
six	O
reserve	O
stations	O
,	O
two	O
that	O
serve	O
the	O
integer	O
units	O
,	O
one	O
for	O
the	O
address	O
generators	O
,	O
two	O
for	O
the	O
floating-point	O
units	O
,	O
and	O
one	O
for	O
branch	O
instructions	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
architecture	O
has	O
separate	O
register	O
files	O
for	O
integer	O
and	O
floating-point	O
instructions	O
.	O
</s>
<s>
The	O
integer	O
register	O
file	O
has	O
eight	O
register	B-General_Concept
windows	I-General_Concept
.	O
</s>
<s>
The	O
JWR	O
contains	O
a	O
subset	O
of	O
the	O
eight	O
register	B-General_Concept
windows	I-General_Concept
,	O
the	O
previous	O
,	O
current	O
and	O
next	O
register	B-General_Concept
windows	I-General_Concept
.	O
</s>
<s>
Its	O
purpose	O
is	O
reduce	O
the	O
size	O
of	O
register	O
file	O
so	O
that	O
the	O
microprocessor	B-Architecture
can	O
operate	O
at	O
higher	O
clock	O
frequencies	O
.	O
</s>
<s>
Both	O
have	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
and	O
a	O
shift	O
unit	O
,	O
but	O
only	O
EXA	O
has	O
multiply	O
and	O
divide	O
units	O
.	O
</s>
<s>
They	O
execute	O
add	O
,	O
subtract	O
,	O
multiply	O
,	O
divide	O
,	O
square	O
root	O
and	O
multiply	B-Algorithm
–	I-Algorithm
add	I-Algorithm
instructions	O
.	O
</s>
<s>
Unlike	O
its	O
successor	O
SPARC64	B-Device
VI	I-Device
,	O
the	O
SPARC64	B-Device
V	I-Device
performs	O
the	O
multiply	B-Algorithm
–	I-Algorithm
add	I-Algorithm
with	O
separate	O
multiplication	O
and	O
addition	O
operations	O
,	O
thus	O
with	O
up	O
to	O
two	O
rounding	O
errors	O
.	O
</s>
<s>
The	O
graphics	O
unit	O
executes	O
Visual	B-General_Concept
Instruction	I-General_Concept
Set	I-General_Concept
(	O
VIS	O
)	O
instructions	O
,	O
a	O
set	O
of	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
instructions	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
has	O
separate	O
update	O
buffers	O
for	O
integer	O
and	O
floating-point	O
units	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
can	O
commit	O
up	O
to	O
four	O
instructions	O
per	O
cycle	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
has	O
two-level	O
cache	O
hierarchy	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
has	O
a	O
128-bit	O
system	O
bus	O
that	O
operates	O
at	O
260MHz	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
V	I-Device
consisted	O
of	O
191	O
million	O
transistors	O
,	O
of	O
which	O
19	O
million	O
are	O
contained	O
in	O
logic	O
circuits	O
.	O
</s>
<s>
It	O
was	O
fabricated	B-Architecture
in	O
a	O
0.13	O
μm	O
,	O
eight-layer	O
copper	O
metallization	O
,	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	O
)	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
process	O
.	O
</s>
<s>
At	O
1.3GHz	O
,	O
the	O
SPARC64	B-Device
V	I-Device
has	O
a	O
power	O
dissipation	O
of	O
34.7	O
W	O
.	O
The	O
Fujitsu	O
PrimePower	O
servers	O
that	O
use	O
the	O
SPARC64	B-Device
V	I-Device
supply	O
a	O
slightly	O
higher	O
voltage	O
the	O
microprocessor	B-Architecture
to	O
enable	O
it	O
to	O
operate	O
at	O
1.35GHz	O
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
V+	I-General_Concept
,	O
code-named	O
"	O
Olympus-B	O
"	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
SPARC64	B-Device
V	I-Device
.	O
Improvements	O
over	O
the	O
SPARC64	B-Device
V	I-Device
included	O
higher	O
clock	O
frequencies	O
of	O
1.822.16GHz	O
and	O
a	O
larger	O
3	O
or	O
4MB	O
L2	O
cache	O
.	O
</s>
<s>
The	O
first	O
SPARC64	B-General_Concept
V+	I-General_Concept
,	O
a	O
1.89GHz	O
version	O
,	O
was	O
shipped	O
in	O
September	O
2004	O
in	O
the	O
Fujitsu	O
PrimePower	O
650	O
and	O
850	O
.	O
</s>
<s>
It	O
was	O
fabricated	B-Architecture
in	O
a	O
90	O
nm	O
CMOS	O
process	O
with	O
ten	O
levels	O
of	O
copper	O
interconnect	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VI	I-Device
,	O
code-named	O
Olympus-C	O
,	O
is	O
a	O
two-core	O
processor	O
(	O
the	O
first	O
multi-core	O
SPARC64	O
processor	O
)	O
which	O
succeeded	O
the	O
SPARC64	B-General_Concept
V+	I-General_Concept
.	O
</s>
<s>
It	O
is	O
fabricated	B-Architecture
by	O
Fujitsu	O
in	O
a	O
90nm	O
,	O
10-layer	O
copper	O
,	O
CMOS	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
process	O
,	O
which	O
enabled	O
two	O
cores	O
and	O
an	O
L2	O
cache	O
to	O
be	O
integrated	O
on	O
a	O
die	O
.	O
</s>
<s>
Each	O
core	O
is	O
a	O
modified	O
SPARC64	B-General_Concept
V+	I-General_Concept
processor	O
.	O
</s>
<s>
One	O
of	O
the	O
main	O
improvements	O
is	O
the	O
addition	O
of	O
two-way	O
coarse-grained	B-General_Concept
multi-threading	I-General_Concept
(	O
CMT	O
)	O
,	O
which	O
Fujitsu	O
called	O
vertical	O
multi-threading	O
(	O
VMT	O
)	O
.	O
</s>
<s>
A	O
floating-point	O
fused	O
multiply-add	B-Algorithm
(	O
FMA	O
)	O
instruction	O
was	O
also	O
added	O
,	O
the	O
first	O
SPARC	B-Architecture
processor	O
to	O
do	O
so	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VI	I-Device
has	O
a	O
new	O
system	O
bus	O
,	O
the	O
Jupiter	O
Bus	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VI	I-Device
consisted	O
of	O
540	O
million	O
transistors	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VI	I-Device
was	O
originally	O
to	O
have	O
been	O
introduced	O
in	O
mid-2004	O
in	O
Fujitsu	O
's	O
PrimePower	O
servers	O
.	O
</s>
<s>
These	O
servers	O
were	O
scheduled	O
to	O
be	O
introduced	O
in	O
mid-2006	O
,	O
but	O
were	O
delayed	O
until	O
April	O
2007	O
,	O
when	O
they	O
were	O
introduced	O
as	O
the	O
SPARC	B-Application
Enterprise	I-Application
.	O
</s>
<s>
The	O
SPARC64	B-Device
VI	I-Device
processors	O
featured	O
in	O
the	O
SPARC	B-Application
Enterprise	I-Application
at	O
its	O
announcement	O
were	O
a	O
2.15GHz	O
version	O
with	O
a	O
5MB	O
L2	O
cache	O
,	O
and	O
2.28	O
and	O
2.4GHz	O
versions	O
with	O
6MB	O
L2	O
caches	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VII	I-Device
(	O
previously	O
called	O
the	O
SPARC64	O
VI+	O
)	O
,	O
code-named	O
Jupiter	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
SPARC64	B-Device
VI	I-Device
announced	O
in	O
July	O
2008	O
.	O
</s>
<s>
It	O
is	O
a	O
quad-core	O
microprocessor	B-Architecture
.	O
</s>
<s>
Each	O
core	O
is	O
capable	O
of	O
two-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
which	O
replaces	O
two-way	O
coarse-grained	B-General_Concept
multithreading	I-General_Concept
,	O
termed	O
vertical	O
multithreading	B-General_Concept
(	O
VMT	O
)	O
by	O
Fujitsu	O
.	O
</s>
<s>
Other	O
changes	O
include	O
more	O
RAS	B-General_Concept
features	O
;	O
the	O
integer	O
register	O
file	O
is	O
now	O
protected	O
by	O
ECC	O
,	O
and	O
the	O
number	O
of	O
error	O
checkers	O
has	O
been	O
increased	O
to	O
around	O
3,400	O
.	O
</s>
<s>
It	O
consists	O
of	O
600	O
million	O
transistors	O
,	O
is	O
21.31mm	O
×	O
20.86mm	O
(	O
444.63mm2	O
)	O
large	O
,	O
and	O
is	O
fabricated	B-Architecture
by	O
Fujitsu	O
in	O
its	O
65	O
nm	O
CMOS	O
,	O
copper	O
interconnect	O
process	O
.	O
</s>
<s>
The	O
SPARC64	B-Device
VII	I-Device
was	O
featured	O
in	O
the	O
SPARC	B-Application
Enterprise	I-Application
.	O
</s>
<s>
It	O
is	O
socket-compatible	O
with	O
its	O
predecessor	O
,	O
the	O
SPARC64	B-Device
VI	I-Device
,	O
and	O
is	O
field-upgradeable	O
.	O
</s>
<s>
SPARC64	B-Device
VIIs	I-Device
could	O
coexist	O
,	O
whilst	O
operating	O
at	O
their	O
native	O
clock	O
frequency	O
,	O
alongside	O
SPARC64	B-Device
VIs	I-Device
.	O
</s>
<s>
The	O
first	O
versions	O
of	O
the	O
SPARC64	B-Device
VII	I-Device
were	O
a	O
2.4GHz	O
version	O
with	O
a	O
5MB	O
L2	O
cache	O
used	O
in	O
the	O
SPARC	B-Application
Enterprise	I-Application
M4000	O
and	O
M5000	O
,	O
and	O
a	O
2.52GHz	O
version	O
with	O
a	O
6MB	O
L2	O
cache	O
.	O
</s>
<s>
On	O
28	O
October	O
2008	O
,	O
a	O
2.52GHz	O
version	O
with	O
a	O
5MB	O
L2	O
cache	O
was	O
introduced	O
in	O
the	O
SPARC	B-Application
Enterprise	I-Application
M3000	O
.	O
</s>
<s>
On	O
13	O
October	O
2009	O
,	O
Fujitsu	O
and	O
Sun	O
introduced	O
new	O
versions	O
of	O
the	O
SPARC64	B-Device
VII	I-Device
(	O
code-named	O
Jupiter+	O
)	O
,	O
a	O
2.53GHz	O
version	O
with	O
a	O
5.5MB	O
L2	O
cache	O
for	O
the	O
M4000	O
and	O
M5000	O
,	O
and	O
a	O
2.88GHz	O
version	O
with	O
a	O
6MB	O
L2	O
cache	O
for	O
the	O
M8000	O
and	O
M9000	O
.	O
</s>
<s>
The	O
SPARC64	O
VII+	O
(	O
Jupiter-E	O
)	O
,	O
referred	O
to	O
as	O
the	O
M3	O
by	O
Oracle	B-Application
,	O
is	O
a	O
further	O
development	O
of	O
the	O
SPARC64	B-Device
VII	I-Device
.	O
</s>
<s>
This	O
version	O
was	O
announced	O
on	O
2	O
December	O
2010	O
for	O
the	O
high-end	O
SPARC	B-Application
Enterprise	I-Application
M8000	O
and	O
M9000	O
servers	O
.	O
</s>
<s>
Existing	O
high-end	O
SPARC	B-Application
Enterprise	I-Application
M-Series	I-Application
servers	O
are	O
able	O
to	O
upgrade	O
to	O
the	O
VII+	O
processors	O
in	O
the	O
field	O
.	O
</s>
<s>
The	O
SPARC64	O
VIIIfx	O
(	O
Venus	O
)	O
is	O
an	O
eight-core	O
processor	O
based	O
on	O
the	O
SPARC64	B-Device
VII	I-Device
designed	O
for	O
high-performance	B-Architecture
computing	I-Architecture
(	O
HPC	O
)	O
.	O
</s>
<s>
It	O
consists	O
of	O
760	O
million	O
transistors	O
,	O
measures	O
22.7mm	O
by	O
22.6	O
(	O
513.02mm2	O
;	O
)	O
,	O
is	O
fabricated	B-Architecture
in	O
Fujitu	O
's	O
45	O
nm	O
CMOS	O
process	O
with	O
copper	O
interconnects	O
,	O
and	O
has	O
1,271	O
I/O	O
pins	O
.	O
</s>
<s>
The	O
VIIIfx	O
has	O
four	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
for	O
a	O
total	O
of	O
eight	O
memory	O
channels	O
.	O
</s>
<s>
The	O
VIIIfx	O
was	O
developed	O
for	O
the	O
Next-Generation	O
Supercomputer	B-Architecture
Project	O
(	O
also	O
called	O
Kei	O
Soku	O
Keisenki	O
and	O
Project	O
Keisoku	O
)	O
initiated	O
by	O
Japan	O
's	O
Ministry	O
of	O
Education	O
,	O
Culture	O
,	O
Sports	O
,	O
Science	O
and	O
Technology	O
in	O
January	O
2006	O
.	O
</s>
<s>
The	O
project	O
aimed	O
to	O
produce	O
the	O
world	O
's	O
fastest	B-Operating_System
supercomputer	I-Operating_System
with	O
performance	O
of	O
over	O
10PFLOPS	O
by	O
March	O
2011	O
.	O
</s>
<s>
The	O
companies	O
contracted	O
to	O
develop	O
the	O
supercomputer	B-Architecture
were	O
Fujitsu	O
,	O
Hitachi	O
,	O
and	O
NEC	O
.	O
</s>
<s>
The	O
supercomputer	B-Architecture
was	O
originally	O
envisioned	O
to	O
have	O
a	O
hybrid	O
architecture	O
containing	O
scalar	B-General_Concept
and	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
The	O
Fujitsu-designed	O
VIIIfx	O
was	O
to	O
have	O
been	O
the	O
scalar	B-General_Concept
processor	I-General_Concept
,	O
with	O
the	O
vector	B-Operating_System
processor	I-Operating_System
to	O
have	O
been	O
jointly	O
designed	O
by	O
Hitachi	O
and	O
NEC	O
.	O
</s>
<s>
Afterwards	O
,	O
Fujitsu	O
redesigned	O
the	O
supercomputer	B-Architecture
to	O
use	O
the	O
VIIIfx	O
as	O
its	O
only	O
processor	O
type	O
.	O
</s>
<s>
By	O
2010	O
,	O
the	O
supercomputer	B-Architecture
that	O
would	O
be	O
built	O
by	O
the	O
project	O
was	O
named	O
the	O
K	B-Device
computer	I-Device
.	O
</s>
<s>
In	O
June	O
2011	O
,	O
the	O
TOP500	B-Operating_System
Project	O
Committee	O
announced	O
that	O
the	O
K	B-Device
computer	I-Device
(	O
still	O
incomplete	O
with	O
only	O
68,544	O
processors	O
)	O
topped	O
the	O
LINPACK	B-Device
benchmark	I-Device
at	O
8.162PFLOPS	O
,	O
realizing	O
93%	O
of	O
its	O
peak	O
performance	O
,	O
making	O
it	O
the	O
fastest	B-Operating_System
supercomputer	I-Operating_System
in	O
the	O
world	O
at	O
that	O
time	O
.	O
</s>
<s>
The	O
VIIIfx	O
core	O
is	O
based	O
on	O
that	O
of	O
the	O
SPARC64	B-Device
VII	I-Device
with	O
numerous	O
modifications	O
for	O
HPC	O
,	O
namely	O
High	O
Performance	O
Computing-Arithmetic	O
Computational	O
Extensions	O
(	O
HPC-ACE	O
)	O
a	O
Fujitsu-designed	O
extension	O
to	O
the	O
SPARC	B-Architecture
V9	I-Architecture
architecture	O
.	O
</s>
<s>
The	O
front-end	O
had	O
coarse-grained	B-General_Concept
multi-threading	I-General_Concept
removed	O
,	O
the	O
L1	O
instruction	O
cache	O
halved	O
in	O
size	O
to	O
32KB	O
;	O
and	O
the	O
number	O
of	O
branch	O
target	O
address	O
cache	O
(	O
BTAC	O
)	O
entries	O
reduced	O
to	O
1,024	O
from	O
8	O
,	O
192	O
,	O
and	O
its	O
associativity	O
reduced	O
to	O
two	O
from	O
eight	O
;	O
and	O
an	O
extra	O
pipeline	O
stage	O
was	O
inserted	O
before	O
the	O
instruction	O
decoder	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
V9	I-Architecture
architecture	O
was	O
designed	O
to	O
have	O
only	O
32	O
integer	O
and	O
32	O
floating-point	O
number	O
registers	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
V9	I-Architecture
instruction	O
encoding	O
limited	O
the	O
number	O
of	O
registers	O
specifiable	O
to	O
32	O
.	O
</s>
<s>
To	O
specify	O
the	O
extra	O
registers	O
,	O
HPC-ACE	O
has	O
a	O
"	O
prefix	O
"	O
instruction	O
that	O
would	O
immediately	O
follow	O
one	O
or	O
two	O
SPARC	B-Architecture
V9	I-Architecture
instructions	O
.	O
</s>
<s>
The	O
prefix	O
instruction	O
contained	O
(	O
primarily	O
)	O
the	O
portions	O
of	O
the	O
register	O
numbers	O
that	O
could	O
not	O
fit	O
within	O
a	O
SPARC	B-Architecture
V9	I-Architecture
instruction	O
.	O
</s>
<s>
This	O
extra	O
pipeline	O
stage	O
was	O
where	O
up	O
to	O
four	O
SPARC	B-Architecture
V9	I-Architecture
instructions	O
were	O
combined	O
with	O
up	O
to	O
two	O
prefix	O
instructions	O
in	O
the	O
preceding	O
stage	O
.	O
</s>
<s>
The	O
extra	O
integer	O
registers	O
are	O
not	O
part	O
of	O
the	O
register	B-General_Concept
windows	I-General_Concept
defined	O
by	O
SPARC	B-Architecture
V9	I-Architecture
,	O
but	O
are	O
always	O
accessible	O
via	O
the	O
prefix	O
instruction	O
;	O
and	O
the	O
256	O
floating-point	O
registers	O
could	O
be	O
used	O
by	O
both	O
scalar	B-General_Concept
floating-point	O
instructions	O
and	O
by	O
both	O
integer	O
and	O
floating-point	O
SIMD	B-Device
instructions	O
.	O
</s>
<s>
The	O
128-bit	O
SIMD	B-Device
instructions	O
from	O
HPC-ACE	O
were	O
implemented	O
by	O
adding	O
two	O
extra	O
floating-point	O
units	O
for	O
a	O
total	O
of	O
four	O
.	O
</s>
<s>
SIMD	B-Device
execution	O
can	O
perform	O
up	O
four	O
single	O
-	O
or	O
double-precision	O
fused-multiply-add	O
operations	O
(	O
eight	O
FLOPs	O
)	O
per	O
cycle	O
.	O
</s>
<s>
Translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
:	O
</s>
<s>
The	O
SPARC64	O
IXfx	O
is	O
an	O
improved	O
version	O
of	O
the	O
SPARC64	O
VIIIfx	O
designed	O
by	O
Fujitsu	O
and	O
LSI	O
first	O
revealed	O
in	O
the	O
announcement	O
of	O
the	O
PRIMEHPC	O
FX10	O
supercomputer	B-Architecture
on	O
7	O
November	O
2011	O
.	O
</s>
<s>
It	O
,	O
along	O
with	O
the	O
PRIMEHPC	O
FX10	O
,	O
is	O
a	O
commercialization	O
of	O
the	O
technologies	O
that	O
first	O
appeared	O
in	O
the	O
VIIIfx	O
and	O
K	B-Device
computer	I-Device
.	O
</s>
<s>
The	O
SPARC64	O
X	O
is	O
a	O
16-core	O
server	O
microprocessor	B-Architecture
announced	O
in	O
2012	O
and	O
used	O
in	O
Fujitsu	O
's	O
M10	O
servers	O
(	O
which	O
are	O
also	O
marketed	O
by	O
Oracle	B-Application
)	O
.	O
</s>
<s>
The	O
cores	O
were	O
improved	O
by	O
the	O
inclusion	O
of	O
a	O
pattern	O
history	O
table	O
for	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
speculative	B-Architecture
execution	I-Architecture
of	I-Architecture
loads	I-Architecture
,	O
more	O
execution	O
units	O
,	O
support	O
for	O
the	O
HPC-ACE	O
extension	O
(	O
originally	O
from	O
the	O
SPARC64	O
VIIIfx	O
)	O
,	O
deeper	O
pipeline	O
for	O
a	O
3.0GHz	O
clock	O
frequency	O
,	O
and	O
accelerators	O
for	O
cryptography	O
,	O
database	O
,	O
and	O
decimal	O
floating-point	O
number	O
arithmetic	O
and	O
conversion	O
functions	O
.	O
</s>
<s>
Chip	O
organization	O
improvements	O
include	O
four	O
integrated	O
DDR3	O
SDRAM	O
memory	B-General_Concept
controllers	I-General_Concept
,	O
glueless	O
four-way	O
symmetrical	O
multiprocessing	O
,	O
ten	O
SERDES	O
channels	O
for	O
symmetrical	O
multiprocessing	O
scalability	O
to	O
64	O
sockets	O
,	O
and	O
two	O
integrated	O
PCI	O
Express	O
3.0	O
controllers	O
.	O
</s>
<s>
The	O
SPARC64	O
X	O
contains	O
2.95	O
billion	O
transistors	O
,	O
measures	O
23.5mm	O
by	O
25mm	O
(	O
637.5mm2	O
)	O
,	O
and	O
is	O
fabricated	B-Architecture
in	O
a	O
28nm	O
CMOS	O
process	O
with	O
copper	O
interconnects	O
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
X+	I-General_Concept
is	O
an	O
enhanced	O
SPARC64	O
X	O
processor	O
announced	O
in	O
2013	O
.	O
</s>
<s>
It	O
contained	O
2.99	O
billion	O
transistors	O
,	O
measured	O
24mm	O
by	O
25mm	O
(	O
600mm2	O
)	O
,	O
and	O
is	O
fabricated	B-Architecture
in	O
the	O
same	O
process	O
as	O
the	O
SPARC64	O
X	O
.	O
</s>
<s>
On	O
8	O
April	O
2014	O
,	O
3.7GHz	O
speed-binned	B-Architecture
parts	O
became	O
available	O
in	O
response	O
to	O
the	O
introduction	O
of	O
new	O
Xeon	B-Device
E5	O
and	O
E7	O
models	O
by	O
Intel	O
;	O
and	O
the	O
impending	O
introduction	O
of	O
the	O
POWER8	B-Device
by	O
IBM	O
.	O
</s>
<s>
It	O
is	O
used	O
in	O
the	O
Fujitsu	O
PRIMEHPC	O
FX100	O
supercomputer	B-Architecture
,	O
which	O
succeeded	O
the	O
PRIMEHPC	O
FX10	O
.	O
</s>
<s>
It	O
consists	O
of	O
3.75	O
billion	O
transistors	O
and	O
is	O
fabricated	B-Architecture
by	O
the	O
Taiwan	O
Semiconductor	B-Architecture
Manufacturing	I-Architecture
Company	O
in	O
its	O
20	O
nm	O
high-κ	B-Algorithm
metal	I-Algorithm
gate	I-Algorithm
(	O
HKMG	B-Algorithm
)	O
process	O
.	O
</s>
<s>
The	O
Microprocessor	B-Architecture
Report	O
estimated	O
the	O
die	O
to	O
have	O
an	O
area	O
of	O
500mm2	O
;	O
and	O
a	O
typical	O
power	O
consumption	O
of	O
200W	O
.	O
</s>
<s>
The	O
XIfx	O
core	O
was	O
based	O
on	O
the	O
SPARC64	B-General_Concept
X+	I-General_Concept
with	O
organizational	O
improvements	O
.	O
</s>
<s>
The	O
XIfx	O
implements	O
an	O
improved	O
version	O
of	O
the	O
HPC-ACE	O
extensions	O
(	O
HPC-ACE2	O
)	O
,	O
which	O
doubled	O
the	O
width	O
of	O
the	O
SIMD	B-Device
units	O
to	O
256	O
bits	O
and	O
added	O
new	O
SIMD	B-Device
instructions	O
.	O
</s>
<s>
To	O
complement	O
the	O
increased	O
width	O
of	O
the	O
SIMD	B-Device
units	O
,	O
the	O
L1	O
cache	O
bandwidth	O
was	O
increased	O
to	O
4.4TB/s	O
.	O
</s>
<s>
The	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
were	O
replaced	O
with	O
four	O
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
(	O
HMC	O
)	O
interfaces	O
for	O
decreased	O
memory	O
latency	O
and	O
improved	O
memory	O
bandwidth	O
.	O
</s>
<s>
According	O
to	O
the	O
Microprocessor	B-Architecture
Report	O
,	O
the	O
IXfx	O
was	O
the	O
first	O
processor	O
to	O
use	O
HMCs	O
.	O
</s>
<s>
Fujitsu	O
announced	O
at	O
the	O
International	O
Supercomputing	B-Architecture
Conference	O
in	O
June	O
2016	O
that	O
its	O
future	O
exascale	B-General_Concept
supercomputer	B-Architecture
will	O
feature	O
processors	O
of	O
its	O
own	O
design	O
that	O
implement	O
the	O
ARMv8	O
architecture	O
.	O
</s>
<s>
The	O
A64FX	B-Device
will	O
implement	O
extensions	O
to	O
the	O
ARMv8	O
architecture	O
,	O
equivalent	O
to	O
HPC-ACE2	O
,	O
that	O
Fujitsu	O
is	O
developing	O
with	O
ARM	O
Holdings	O
.	O
</s>
