<s>
SHAKTI	B-General_Concept
is	O
an	O
open-source	O
initiative	O
by	O
the	O
Reconfigurable	O
Intelligent	O
Systems	O
Engineering	O
(	O
RISE	O
)	O
group	O
at	O
Indian	O
Institute	O
of	O
Technology	O
,	O
Madras	O
to	O
develop	O
the	O
first	O
indigenous	O
Indian	O
industrial-grade	O
processor	O
.	O
</s>
<s>
The	O
aim	O
of	O
SHAKTI	B-General_Concept
initiative	O
includes	O
building	O
an	O
opensource	O
production-grade	O
processor	O
,	O
complete	O
System	O
on	O
Chips	O
(	O
SoCs	O
)	O
,	O
development	O
boards	O
and	O
SHAKTI	B-General_Concept
based	O
software	O
platform	O
.	O
</s>
<s>
All	O
the	O
source	O
codes	O
for	O
SHAKTI	B-General_Concept
are	O
open-sourced	O
under	O
the	O
Modified	O
BSD	O
License	O
.	O
</s>
<s>
processors	O
are	O
based	O
on	O
the	O
RISC-V	B-Device
ISA	O
.	O
</s>
<s>
The	O
processors	O
are	O
designed	O
to	O
have	O
either	O
22	O
nm	O
FinFET	O
or	O
180	O
nm	O
CMOS	O
technology	O
nodes	O
depending	O
on	O
the	O
manufacturing	O
foundry	B-Algorithm
.	O
</s>
<s>
SHAKTI	B-General_Concept
has	O
envisioned	O
a	O
family	O
of	O
processors	O
as	O
part	O
of	O
its	O
road-map	O
,	O
catering	O
to	O
different	O
segments	O
of	O
the	O
market	O
.	O
</s>
<s>
The	O
SHAKTI	B-General_Concept
project	O
aims	O
to	O
build	O
6	O
variants	O
of	O
processors	O
based	O
on	O
the	O
RISC-V	B-Device
ISA	O
.	O
</s>
<s>
The	O
E-class	O
are	O
32/64	O
bit	O
microcontrollers	B-Architecture
capable	O
of	O
supporting	O
all	O
extensions	O
of	O
the	O
RISC-V	B-Device
ISA	O
,	O
aimed	O
at	O
low-power	O
and	O
low	O
computer	O
applications	O
.	O
</s>
<s>
It	O
is	O
positioned	O
against	O
ARM	B-Architecture
’s	O
M-class	O
(	O
Cortex-M	O
series	O
)	O
cores	O
.	O
</s>
<s>
It	O
is	O
capable	O
of	O
running	O
real-time	O
operating	O
systems	O
like	O
FreeRTOS	B-Operating_System
,	O
Zephyr	B-Application
and	O
eChronos	O
.	O
</s>
<s>
The	O
E-arty35T	O
SoC	O
is	O
a	O
single-chip	O
32-bit	O
E-class	O
microcontroller	B-Architecture
with	O
128kB	O
RAM	O
.	O
</s>
<s>
It	O
is	O
positioned	O
against	O
ARM	B-Architecture
's	O
Cortex	O
A35/A55	O
.	O
</s>
<s>
The	O
C-arty100T	O
SoC	O
is	O
a	O
single-chip	O
64-bit	O
C-class	O
microcontroller	B-Architecture
with	O
128MB	O
DDR3	O
RAM	O
,	O
16	O
General	O
Purpose	O
Input	O
Output	O
(	O
GPIO	O
)	O
pins	O
,	O
a	O
Platform	O
Level	O
Interrupt	O
Controller	O
(	O
PLIC	O
)	O
,	O
a	O
Counter	O
,	O
1	O
Universal	O
Asynchronous	O
Receiver	O
Transmitter	O
(	O
UART	O
)	O
and	O
1	O
Inter-Integrated	O
Circuit	O
(	O
I2C	O
)	O
.	O
</s>
<s>
Its	O
features	O
include	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
multithreading	B-Operating_System
,	O
aggressive	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
non-blocking	B-General_Concept
caches	I-General_Concept
and	O
deep	B-General_Concept
pipeline	I-General_Concept
stages	O
.	O
</s>
<s>
The	O
team	O
is	O
currently	O
working	O
on	O
implementing	O
atomics	O
,	O
Memory	O
dependence	O
prediction	O
,	O
Instruction	O
Window/Scheduler	O
optimizations	O
,	O
Implementation	O
of	O
some	O
functional	O
units	O
,	O
Performance	O
analysis/projections	O
,	O
Optimizations	O
to	O
meet	O
first-cut	O
target	O
frequency	O
on	O
1GHz	O
on	O
22nm	B-Algorithm
processor	O
.	O
</s>
<s>
The	O
S-Class	O
is	O
a	O
64-bit	O
superscalar	B-General_Concept
,	O
multi-threaded	B-Operating_System
variant	O
aimed	O
at	O
Desktop	O
and	O
Enterprise	O
server	O
Application	O
.	O
</s>
<s>
The	O
cores	O
can	O
be	O
a	O
combination	O
of	O
C	O
or	O
I	O
class	O
,	O
single-thread	B-Operating_System
performance	O
driving	O
the	O
core	O
choice	O
.	O
</s>
<s>
RIMO	O
is	O
the	O
code	O
name	O
of	O
the	O
SHAKTI	B-General_Concept
C-class	O
based	O
SoC	O
that	O
has	O
been	O
taped-out	O
at	O
Semi-Conductor	O
Laboratory	O
(	O
SCL	O
)	O
at	O
Mohali	O
using	O
180nm	B-Algorithm
process	O
technology	O
.	O
</s>
<s>
CREEK	O
is	O
the	O
code	O
name	O
of	O
the	O
SHAKTI	B-General_Concept
C-class	O
based	O
SoC	O
that	O
has	O
been	O
taped-out	O
at	O
Intel	O
's	O
Oregon	O
fab	B-Algorithm
using	O
a	O
22nm	B-Algorithm
FinFET	O
process	O
.	O
</s>
<s>
Moushik	O
is	O
the	O
code	O
name	O
of	O
the	O
SHAKTI	B-General_Concept
E-class	O
based	O
SoC	O
that	O
has	O
been	O
taped-out	O
at	O
SCL	O
using	O
180nm	B-Algorithm
process	O
technology	O
.	O
</s>
<s>
In-order	O
5	O
stage	O
64-bit	O
microcontroller	B-Architecture
supporting	O
the	O
entire	O
stable	O
RISC-V	B-Device
ISA(RV64IMAFD )	O
.	O
</s>
<s>
Compatible	O
with	O
privilege	O
spec	O
(	O
v1.10	O
)	O
of	O
RISC-V	B-Device
ISA	O
and	O
supports	O
the	O
sv39	O
virtualisation	O
scheme	O
.	O
</s>
<s>
Includes	O
a	O
branch	B-General_Concept
predictor	I-General_Concept
with	O
a	O
Return-Address-Stack	O
.	O
</s>
<s>
Pipelined	O
IEEE-754	O
compliant	O
single	O
and	O
double-precision	O
floating	O
point	O
units	O
and	O
Multi-channel	O
Direct	B-General_Concept
Memory	I-General_Concept
Access	I-General_Concept
(	O
DMA	O
)	O
support	O
.	O
</s>
<s>
Peripherals	O
like	O
2	O
x	O
I2C	O
,	O
2	O
x	O
UART	O
,	O
2	O
x	O
QSPI	B-Architecture
,	O
a	O
Debugger	B-Application
,	O
a	O
256KB	O
tightly	O
coupled	O
memory	O
,	O
32-bit	O
GPIOs	O
and	O
an	O
expansion	O
bus	O
that	O
can	O
be	O
connected	O
to	O
an	O
FPGA	B-Architecture
.	O
</s>
<s>
E-arty35Tis	O
a	O
SoC	O
based	O
on	O
SHAKTI	B-General_Concept
E	O
class	O
 [ 14 ] 	O
.	O
</s>
<s>
C-arty100Tis	O
a	O
SoC	O
based	O
on	O
SHAKTI	B-General_Concept
C	O
class	O
.	O
</s>
