<s>
SBus	B-Architecture
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
system	O
that	O
was	O
used	O
in	O
most	O
SPARC-based	O
computers	O
(	O
including	O
all	O
SPARCstations	B-Device
)	O
from	O
Sun	O
Microsystems	O
and	O
others	O
during	O
the	O
1990s	O
.	O
</s>
<s>
It	O
was	O
introduced	O
by	O
Sun	O
in	O
1989	O
to	O
be	O
a	O
high-speed	O
bus	O
counterpart	O
to	O
their	O
high-speed	O
SPARC	B-Architecture
processors	O
,	O
replacing	O
the	O
earlier	O
(	O
and	O
by	O
this	O
time	O
,	O
outdated	O
)	O
VMEbus	B-Architecture
used	O
in	O
their	O
Motorola	B-Device
68020	I-Device
-	O
and	O
68030-based	O
systems	O
and	O
early	O
SPARC	B-Architecture
boxes	O
.	O
</s>
<s>
When	O
Sun	O
moved	O
to	O
open	O
the	O
SPARC	B-Architecture
definition	O
in	O
the	O
early	O
1990s	O
,	O
SBus	B-Architecture
was	O
likewise	O
standardized	O
and	O
became	O
IEEE-1496	O
.	O
</s>
<s>
In	O
1997	O
Sun	O
started	O
to	O
migrate	O
away	O
from	O
SBus	B-Architecture
to	O
the	O
Peripheral	B-Protocol
Component	I-Protocol
Interconnect	I-Protocol
(	O
PCI	B-Protocol
)	O
bus	O
,	O
and	O
today	O
SBus	B-Architecture
is	O
no	O
longer	O
used	O
.	O
</s>
<s>
The	O
industry	O
's	O
first	O
third-party	O
SBus	B-Architecture
cards	O
were	O
announced	O
in	O
1989	O
by	O
Antares	O
Microsystems	O
;	O
these	O
were	O
a	O
10BASE2	O
Ethernet	O
controller	O
,	O
a	O
SCSI-SNS	O
host	O
adapter	O
,	O
a	O
parallel	O
port	O
,	O
and	O
an	O
8-channel	O
serial	O
controller	O
.	O
</s>
<s>
At	O
the	O
peak	O
of	O
the	O
market	O
over	O
250	O
manufacturers	O
were	O
listed	O
in	O
the	O
SBus	B-Architecture
Product	O
Directory	O
,	O
which	O
was	O
renamed	O
to	O
the	O
SPARC	B-Architecture
Product	O
Directory	O
in	O
1996	O
.	O
</s>
<s>
SBus	B-Architecture
is	O
in	O
many	O
ways	O
a	O
"	O
clean	O
"	O
design	O
.	O
</s>
<s>
It	O
was	O
targeted	O
only	O
to	O
be	O
used	O
with	O
SPARC	B-Architecture
processors	O
,	O
so	O
most	O
cross-platform	O
issues	O
were	O
not	O
a	O
consideration	O
.	O
</s>
<s>
SBus	B-Architecture
is	O
based	O
on	O
a	O
big-endian	O
32-bit	O
address	O
and	O
data	B-General_Concept
bus	I-General_Concept
,	O
can	O
run	O
at	O
speeds	O
ranging	O
from	O
16.67MHz	O
to	O
25MHz	O
,	O
and	O
is	O
capable	O
of	O
transferring	O
up	O
to	O
100	O
MB/s	O
.	O
</s>
<s>
When	O
the	O
64-bit	B-Device
UltraSPARC	B-General_Concept
was	O
introduced	O
,	O
SBus	B-Architecture
was	O
modified	O
to	O
support	O
extended	O
transfers	O
of	O
a	O
64	B-Device
bits	I-Device
doubleword	O
per	O
cycle	O
to	O
produce	O
a	O
200	O
MB/s	O
64-bit	B-Device
bus	O
.	O
</s>
<s>
This	O
variant	O
of	O
the	O
SBus	B-Architecture
architecture	O
used	O
the	O
same	O
form	O
factor	O
and	O
was	O
backward-compatible	O
with	O
existing	O
devices	O
,	O
as	O
extended	O
transfers	O
are	O
an	O
optional	O
feature	O
.	O
</s>
<s>
SBus	B-Architecture
cards	O
had	O
a	O
very	O
compact	O
form	O
factor	O
for	O
the	O
time	O
.	O
</s>
<s>
This	O
allowed	O
for	O
three	O
expansion	O
slots	O
in	O
the	O
slim	O
"	O
pizza	B-General_Concept
box	I-General_Concept
"	O
enclosure	O
of	O
the	O
SPARCstation	B-Architecture
1	I-Architecture
.	O
</s>
<s>
SBus	B-Architecture
was	O
originally	O
announced	O
as	O
both	O
a	O
system	B-Architecture
bus	I-Architecture
and	O
a	O
peripheral	O
interconnect	B-General_Concept
that	O
allowed	O
input	O
and	O
output	O
devices	O
relatively	O
low	O
latency	O
access	O
to	O
memory	O
.	O
</s>
<s>
However	O
,	O
soon	O
memory	O
and	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
speeds	O
outpaced	O
I/O	O
performance	O
.	O
</s>
<s>
Within	O
a	O
year	O
some	O
Sun	O
systems	O
used	O
MBus	B-Architecture
,	O
another	O
interconnection	O
standard	O
,	O
as	O
a	O
CPU	O
—	O
memory	O
bus	O
.	O
</s>
<s>
The	O
SBus	B-Architecture
served	O
as	O
an	O
input/output	O
bus	O
for	O
the	O
rest	O
of	O
its	O
lifetime	O
.	O
</s>
