<s>
SATA	B-Architecture
Express	I-Architecture
(	O
sometimes	O
unofficially	O
shortened	O
to	O
SATAe	B-Architecture
)	O
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
interface	B-Application
that	O
supports	O
both	O
Serial	O
ATA	O
(	O
SATA	O
)	O
and	O
PCI	O
Express	O
(	O
PCIe	O
)	O
storage	O
devices	O
,	O
initially	O
standardized	O
in	O
the	O
SATA	O
3.2	O
specification	O
.	O
</s>
<s>
The	O
SATA	B-Architecture
Express	I-Architecture
connector	O
used	O
on	O
the	O
host	O
side	O
is	O
backward	B-General_Concept
compatible	I-General_Concept
with	O
the	O
standard	O
SATA	O
data	O
connector	O
,	O
while	O
it	O
also	O
provides	O
two	O
PCI	O
Express	O
lanes	O
as	O
a	O
pure	O
PCI	O
Express	O
connection	O
to	O
the	O
storage	O
device	O
.	O
</s>
<s>
Instead	O
of	O
continuing	O
with	O
the	O
SATA	O
interface	B-Application
's	O
usual	O
approach	O
of	O
doubling	O
its	O
native	O
speed	O
with	O
each	O
major	O
version	O
,	O
SATA3.2	O
specification	O
included	O
the	O
PCI	O
Express	O
bus	B-General_Concept
for	O
achieving	O
data	O
transfer	B-Device
speeds	I-Device
greater	O
than	O
the	O
SATA	O
3.0	O
speed	O
limit	O
of	O
6Gbit/s	O
.	O
</s>
<s>
Designers	O
of	O
the	O
SATA	O
interface	B-Application
concluded	O
that	O
doubling	O
the	O
native	O
SATA	O
speed	O
would	O
take	O
too	O
much	O
time	O
to	O
catch	O
up	O
with	O
the	O
advancements	O
in	O
solid-state	B-Device
drive	I-Device
(	O
SSD	B-Device
)	O
technology	O
,	O
would	O
require	O
too	O
many	O
changes	O
to	O
the	O
SATA	O
standard	O
,	O
and	O
would	O
result	O
in	O
a	O
much	O
greater	O
power	O
consumption	O
compared	O
with	O
the	O
existing	O
PCI	O
Express	O
bus	B-General_Concept
.	O
</s>
<s>
As	O
a	O
widely	O
adopted	O
computer	B-General_Concept
bus	I-General_Concept
,	O
PCI	O
Express	O
provides	O
sufficient	O
bandwidth	O
while	O
allowing	O
easy	O
scaling	O
up	O
by	O
using	O
faster	O
or	O
additional	O
lanes	O
.	O
</s>
<s>
In	O
addition	O
to	O
supporting	O
legacy	O
Advanced	O
Host	B-Application
Controller	I-Application
Interface	I-Application
(	O
AHCI	O
)	O
at	O
the	O
logical	O
interface	B-Application
level	O
,	O
SATA	B-Architecture
Express	I-Architecture
also	O
supports	O
NVM	B-Application
Express	I-Application
(	O
NVMe	B-Application
)	O
as	O
the	O
logical	O
device	O
interface	B-Application
for	O
attached	O
PCI	O
Express	O
storage	O
devices	O
.	O
</s>
<s>
While	O
the	O
support	O
for	O
AHCI	O
ensures	O
software-level	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
legacy	O
SATA	O
devices	O
and	O
legacy	O
operating	B-General_Concept
systems	I-General_Concept
,	O
NVM	B-Application
Express	I-Application
is	O
designed	O
to	O
fully	O
utilize	O
high-speed	O
PCI	O
Express	O
storage	O
devices	O
by	O
leveraging	O
their	O
capability	O
of	O
executing	O
many	O
I/O	B-General_Concept
operations	I-General_Concept
in	B-Operating_System
parallel	I-Operating_System
.	O
</s>
<s>
The	O
Serial	O
ATA	O
(	O
SATA	O
)	O
interface	B-Application
was	O
designed	O
primarily	O
for	O
interfacing	O
with	O
hard	B-Device
disk	I-Device
drives	I-Device
(	O
HDDs	O
)	O
,	O
doubling	O
its	O
native	O
speed	O
with	O
each	O
major	O
revision	O
:	O
maximum	O
SATA	O
transfer	B-Device
speeds	I-Device
went	O
from	O
1.5Gbit/s	O
in	O
SATA	O
1.0	O
(	O
standardized	O
in	O
2003	O
)	O
,	O
through	O
3Gbit/s	O
in	O
SATA	O
2.0	O
(	O
standardized	O
in	O
2004	O
)	O
,	O
to	O
6Gbit/s	O
as	O
provided	O
by	O
SATA	O
3.0	O
(	O
standardized	O
in	O
2009	O
)	O
.	O
</s>
<s>
SATA	O
has	O
also	O
been	O
selected	O
as	O
the	O
interface	B-Application
for	O
gradually	O
more	O
adopted	O
solid-state	B-Device
drives	I-Device
(	O
SSDs	B-Device
)	O
,	O
but	O
the	O
need	O
for	O
a	O
faster	O
interface	B-Application
became	O
apparent	O
as	O
the	O
speed	O
of	O
SSDs	B-Device
and	O
hybrid	B-Device
drives	I-Device
increased	O
over	O
time	O
.	O
</s>
<s>
As	O
an	O
example	O
,	O
some	O
SSDs	B-Device
available	O
in	O
early	O
2009	O
were	O
already	O
well	O
over	O
the	O
capabilities	O
of	O
SATA1.0	O
and	O
close	O
to	O
the	O
SATA2.0	O
maximum	O
transfer	B-Device
speed	I-Device
,	O
while	O
in	O
the	O
second	O
half	O
of	O
2013	O
high-end	O
consumer	O
SSDs	B-Device
had	O
already	O
reached	O
the	O
SATA3.0	O
speed	O
limit	O
,	O
requiring	O
an	O
even	O
faster	O
interface	B-Application
.	O
</s>
<s>
While	O
evaluating	O
different	O
approaches	O
to	O
the	O
required	O
speed	O
increase	O
,	O
designers	O
of	O
the	O
SATA	O
interface	B-Application
concluded	O
that	O
extending	O
the	O
SATA	O
interface	B-Application
so	O
it	O
doubles	O
its	O
native	O
speed	O
to	O
12Gbit/s	O
would	O
require	O
more	O
than	O
two	O
years	O
,	O
making	O
that	O
approach	O
unsuitable	O
for	O
catching	O
up	O
with	O
advancements	O
in	O
SSD	B-Device
technology	O
.	O
</s>
<s>
At	O
the	O
same	O
time	O
,	O
increasing	O
the	O
native	O
SATA	O
speed	O
to	O
12Gbit/s	O
would	O
require	O
too	O
many	O
changes	O
to	O
the	O
SATA	O
standard	O
,	O
ending	O
up	O
in	O
a	O
more	O
costly	O
and	O
less	O
power	O
efficient	O
solution	O
compared	O
with	O
the	O
already	O
available	O
and	O
widely	O
adopted	O
PCI	O
Express	O
bus	B-General_Concept
.	O
</s>
<s>
Thus	O
,	O
PCI	O
Express	O
was	O
selected	O
by	O
the	O
designers	O
of	O
SATA	O
interface	B-Application
,	O
as	O
part	O
of	O
the	O
SATA	O
3.2	O
revision	O
that	O
was	O
standardized	O
in	O
2013	O
;	O
extending	O
the	O
SATA	O
specification	O
to	O
also	O
provide	O
a	O
PCI	O
Express	O
interface	B-Application
within	O
the	O
same	O
backward-compatible	B-General_Concept
connector	O
allowed	O
much	O
faster	O
speeds	O
by	O
reusing	O
already	O
existing	O
technology	O
.	O
</s>
<s>
Some	O
vendors	O
also	O
use	O
proprietary	B-Application
logical	O
interfaces	B-Application
for	O
their	O
flash-based	O
storage	B-General_Concept
products	I-General_Concept
,	O
connected	O
through	O
the	O
PCI	O
Express	O
bus	B-General_Concept
.	O
</s>
<s>
Such	O
storage	B-General_Concept
products	I-General_Concept
can	O
use	O
a	O
multi-lane	O
PCI	O
Express	O
link	O
,	O
while	O
interfacing	O
with	O
the	O
operating	B-General_Concept
system	I-General_Concept
through	O
proprietary	B-Application
drivers	O
and	O
host	O
interfaces	B-Application
.	O
</s>
<s>
Moreover	O
,	O
there	O
are	O
similar	O
storage	B-General_Concept
products	I-General_Concept
using	O
NVM	B-Application
Express	I-Application
as	O
the	O
non-proprietary	O
logical	O
interface	B-Application
for	O
a	O
PCI	O
Express	O
add-on	B-Device
card	I-Device
.	O
</s>
<s>
Support	O
for	O
SATA	B-Architecture
Express	I-Architecture
was	O
initially	O
announced	O
for	O
the	O
Intel	O
9	O
Series	O
chipsets	O
,	O
Z97	B-Device
and	O
H97	B-Device
Platform	B-Device
Controller	I-Device
Hubs	I-Device
(	O
PCHs	O
)	O
,	O
with	O
both	O
of	O
them	O
supporting	O
Intel	B-Device
Haswell	I-Device
and	O
Haswell	B-Device
Refresh	O
processors	O
;	O
availability	O
of	O
these	O
two	O
chipsets	O
was	O
planned	O
for	O
2014	O
.	O
</s>
<s>
In	O
December	O
2013	O
,	O
Asus	O
unveiled	O
a	O
prototype	O
"	O
Z87-Deluxe/SATA	O
Express	O
"	O
motherboard	B-Device
based	O
on	O
the	O
Intel	O
Z87	B-Device
chipset	O
,	O
supporting	O
Haswell	B-Device
processors	O
and	O
using	O
additional	O
ASMedia	O
controller	O
to	O
provide	O
SATA	B-Architecture
Express	I-Architecture
connectivity	O
;	O
this	O
motherboard	B-Device
was	O
also	O
showcased	O
at	O
CES	O
2014	O
although	O
no	O
launch	O
date	O
was	O
announced	O
.	O
</s>
<s>
In	O
April	O
2014	O
,	O
Asus	O
also	O
demonstrated	O
support	O
for	O
the	O
so-called	O
separate	O
reference	O
clock	O
with	O
independent	O
spread	B-Architecture
spectrum	I-Architecture
clocking	O
(	O
SRIS	O
)	O
with	O
some	O
of	O
its	O
pre-production	O
SATA	B-Architecture
Express	I-Architecture
hardware	O
.	O
</s>
<s>
SRIS	O
eliminates	O
the	O
need	O
for	O
complex	O
and	O
costly	O
shielding	O
on	O
SATA	B-Architecture
Express	I-Architecture
cables	O
required	O
for	O
transmitting	O
PCI	O
Express	O
synchronization	O
signals	O
,	O
by	O
providing	O
a	O
separate	O
clock	O
generator	O
on	O
the	O
storage	O
device	O
with	O
additional	O
support	O
from	O
the	O
motherboard	B-Device
firmware	B-Application
.	O
</s>
<s>
In	O
May	O
2014	O
,	O
Intel	O
Z97	B-Device
and	O
H97	B-Device
chipsets	O
became	O
available	O
,	O
bringing	O
support	O
for	O
both	O
SATA	B-Architecture
Express	I-Architecture
and	O
M.2	B-Protocol
,	O
which	O
is	O
a	O
specification	O
for	O
flash-based	O
storage	O
devices	O
in	O
form	O
of	O
internally	O
mounted	O
computer	O
expansion	B-Device
cards	I-Device
.	O
</s>
<s>
Z97	B-Device
and	O
H97	B-Device
chipsets	O
use	O
two	O
PCI	O
Express	O
2.0	O
lanes	O
for	O
each	O
of	O
their	O
SATA	B-Architecture
Express	I-Architecture
ports	O
,	O
providing	O
1GB/s	O
of	O
bandwidth	O
to	O
PCI	O
Express	O
storage	O
devices	O
.	O
</s>
<s>
The	O
release	O
of	O
these	O
two	O
new	O
chipsets	O
,	O
intended	O
primarily	O
for	O
high-end	O
desktops	O
,	O
was	O
soon	O
followed	O
by	O
the	O
availability	O
of	O
Z97	B-Device
-	O
and	O
H97-based	O
motherboards	B-Device
.	O
</s>
<s>
In	O
late	O
August	O
2014	O
,	O
Intel	B-Device
X99	I-Device
chipset	O
became	O
available	O
,	O
bringing	O
support	O
for	O
both	O
SATA	B-Architecture
Express	I-Architecture
and	O
M.2	B-Protocol
to	O
the	O
Intel	O
's	O
enthusiast	O
platform	O
.	O
</s>
<s>
Each	O
of	O
the	O
X99	B-Device
's	O
SATA	B-Architecture
Express	I-Architecture
ports	O
requires	O
two	O
PCI	O
Express2.0	O
lanes	O
provided	O
by	O
the	O
chipset	O
,	O
while	O
the	O
M.2	B-Protocol
slots	I-Protocol
can	O
use	O
either	O
two	O
2.0	O
lanes	O
from	O
the	O
chipset	O
itself	O
,	O
or	O
up	O
to	O
four	O
3.0	O
lanes	O
taken	O
directly	O
from	O
the	O
LGA	O
2011-v3	O
CPU	B-Device
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
X99	B-Device
provides	O
bandwidths	O
of	O
up	O
to	O
3.94GB/s	O
for	O
connected	O
PCI	O
Express	O
storage	O
devices	O
.	O
</s>
<s>
Following	O
the	O
release	O
of	O
X99	B-Device
chipset	O
,	O
numerous	O
X99-based	O
motherboards	B-Device
became	O
available	O
.	O
</s>
<s>
In	O
early	O
March	O
2017	O
,	O
AMD	O
Ryzen	O
became	O
available	O
,	O
bringing	O
native	O
support	O
for	O
SATA	B-Architecture
Express	I-Architecture
to	O
the	O
AMD	O
Socket	O
AM4	O
platform	O
,	O
through	O
use	O
of	O
its	O
accompanying	O
X370	O
,	O
X300	O
,	O
B350	O
,	O
A320	O
and	O
A300	O
chipsets	O
.	O
</s>
<s>
Ryzen	O
also	O
supports	O
M.2	B-Protocol
and	O
other	O
forms	O
of	O
PCI	O
Express	O
storage	O
devices	O
,	O
using	O
up	O
to	O
the	O
total	O
of	O
eight	O
PCI	O
Express3.0	O
lanes	O
provided	O
by	O
the	O
chipset	O
and	O
the	O
AM4	O
CPU	B-Device
.	O
</s>
<s>
SATA	B-Architecture
Express	I-Architecture
is	O
considered	O
a	O
failed	O
standard	O
,	O
because	O
when	O
SATA	B-Architecture
Express	I-Architecture
was	O
introduced	O
,	O
the	O
M.2	B-Protocol
form	O
factor	O
and	O
NVMe	B-Application
standards	O
were	O
also	O
launched	O
,	O
gaining	O
much	O
larger	O
popularity	O
than	O
Serial	O
ATA	O
and	O
SATA	B-Architecture
Express	I-Architecture
.	O
</s>
<s>
Not	O
many	O
storage	O
devices	O
utilizing	O
the	O
SATA	B-Architecture
Express	I-Architecture
interface	B-Application
were	O
released	O
for	O
consumers	O
,	O
and	O
SATA	B-Architecture
Express	I-Architecture
ports	O
quickly	O
disappeared	O
from	O
new	O
motherboards	B-Device
.	O
</s>
<s>
SATA	B-Architecture
Express	I-Architecture
interface	B-Application
supports	O
both	O
PCI	O
Express	O
and	O
SATA	O
storage	O
devices	O
by	O
exposing	O
two	O
PCI	O
Express2.0	O
or	O
3.0	O
lanes	O
and	O
two	O
SATA3.0	O
(	O
6Gbit/s	O
)	O
ports	O
through	O
the	O
same	O
host-side	O
SATA	B-Architecture
Express	I-Architecture
connector	O
(	O
but	O
not	O
both	O
at	O
the	O
same	O
time	O
)	O
.	O
</s>
<s>
Exposed	O
PCI	O
Express	O
lanes	O
provide	O
a	O
pure	O
PCI	O
Express	O
connection	O
between	O
the	O
host	O
and	O
storage	O
device	O
,	O
with	O
no	O
additional	O
layers	O
of	O
bus	B-General_Concept
abstraction	O
.	O
</s>
<s>
The	O
SATA	O
revision	O
3.2	O
specification	O
,	O
in	O
its	O
gold	O
revision	O
,	O
standardizes	O
the	O
SATA	B-Architecture
Express	I-Architecture
and	O
specifies	O
its	O
hardware	O
layout	O
and	O
electrical	O
parameters	O
.	O
</s>
<s>
The	O
choice	O
of	O
PCI	O
Express	O
also	O
enables	O
scaling	O
up	O
the	O
performance	O
of	O
SATA	B-Architecture
Express	I-Architecture
interface	B-Application
by	O
using	O
multiple	O
lanes	O
and	O
different	O
versions	O
of	O
PCI	O
Express	O
.	O
</s>
<s>
In	O
more	O
detail	O
,	O
using	O
two	O
PCI	O
Express2.0	O
lanes	O
provides	O
a	O
total	O
bandwidth	O
of	O
1000MB/s	O
(	O
2×	O
5GT/s	O
raw	O
data	O
rate	O
and	O
8b/10b	B-Protocol
encoding	I-Protocol
)	O
,	O
while	O
using	O
two	O
PCI	O
Express	O
3.0	O
lanes	O
provides	O
1969MB/s	O
(	O
2×	O
8GT/s	O
raw	O
data	O
rate	O
and	O
128b/130b	O
encoding	O
)	O
.	O
</s>
<s>
In	O
comparison	O
,	O
the	O
6Gbit/s	O
raw	O
bandwidth	O
of	O
SATA3.0	O
equates	O
effectively	O
to	O
600MB/s	O
(	O
6	O
GT/s	O
raw	O
data	O
rate	O
and	O
8b/10b	B-Protocol
encoding	I-Protocol
)	O
.	O
</s>
<s>
There	O
are	O
three	O
options	O
available	O
for	O
the	O
logical	O
device	O
interfaces	B-Application
and	O
command	O
sets	O
used	O
for	O
interfacing	O
with	O
storage	O
devices	O
connected	O
to	O
a	O
SATA	B-Architecture
Express	I-Architecture
controller	O
:	O
</s>
<s>
Used	O
for	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
legacy	O
SATA	O
devices	O
,	O
and	O
interfaced	O
through	O
the	O
AHCI	O
driver	O
and	O
legacy	O
SATA3.0	O
(	O
6Gbit/s	O
)	O
ports	O
provided	O
by	O
a	O
SATA	B-Architecture
Express	I-Architecture
controller	O
.	O
</s>
<s>
Used	O
for	O
PCI	O
Express	O
SSDs	B-Device
and	O
interfaced	O
through	O
the	O
AHCI	O
driver	O
and	O
provided	O
PCI	O
Express	O
lanes	O
,	O
providing	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
widespread	O
SATA	O
support	O
in	O
operating	B-General_Concept
systems	I-General_Concept
at	O
the	O
cost	O
of	O
not	O
delivering	O
optimal	O
performance	O
by	O
using	O
AHCI	O
for	O
accessing	O
PCI	O
Express	O
SSDs	B-Device
.	O
</s>
<s>
AHCI	O
was	O
developed	O
back	O
at	O
the	O
time	O
when	O
the	O
purpose	O
of	O
a	O
host	B-Architecture
bus	I-Architecture
adapter	I-Architecture
(	O
HBA	O
)	O
in	O
a	O
system	O
was	O
to	O
connect	O
the	O
CPU/memory	O
subsystem	O
with	O
a	O
much	O
slower	O
storage	O
subsystem	O
based	O
on	O
rotating	O
magnetic	B-Architecture
media	I-Architecture
;	O
as	O
a	O
result	O
,	O
AHCI	O
has	O
some	O
inherent	O
inefficiencies	O
when	O
applied	O
to	O
SSD	B-Device
devices	O
,	O
which	O
behave	O
much	O
more	O
like	O
DRAM	O
than	O
like	O
spinning	O
media	O
.	O
</s>
<s>
Used	O
for	O
PCI	O
Express	O
SSDs	B-Device
and	O
interfaced	O
through	O
the	O
NVMe	B-Application
driver	O
and	O
provided	O
PCI	O
Express	O
lanes	O
,	O
as	O
a	O
high-performance	O
and	O
scalable	O
host	B-Application
controller	I-Application
interface	I-Application
designed	O
and	O
optimized	O
especially	O
for	O
interfacing	O
with	O
PCI	O
Express	O
SSDs	B-Device
.	O
</s>
<s>
NVMe	B-Application
has	O
been	O
designed	O
from	O
the	O
ground	O
up	O
,	O
capitalizing	O
on	O
the	O
low	O
latency	O
and	O
parallelism	B-Operating_System
of	O
PCI	O
Express	O
SSDs	B-Device
,	O
and	O
complementing	O
the	O
parallelism	B-Operating_System
of	O
contemporary	O
CPUs	B-Device
,	O
platforms	O
and	O
applications	O
.	O
</s>
<s>
At	O
a	O
high	O
level	O
,	O
primary	O
advantages	O
of	O
NVMe	B-Application
over	O
AHCI	O
relate	O
to	O
NVMe	B-Application
's	O
ability	O
to	O
exploit	O
parallelism	B-Operating_System
in	O
host	O
hardware	O
and	O
software	O
,	O
based	O
on	O
its	O
design	O
advantages	O
that	O
include	O
data	O
transfers	O
with	O
fewer	O
stages	O
,	O
greater	O
depth	O
of	O
command	B-General_Concept
queues	I-General_Concept
,	O
and	O
more	O
efficient	O
interrupt	B-Application
processing	O
.	O
</s>
<s>
Connectors	O
used	O
for	O
SATA	B-Architecture
Express	I-Architecture
were	O
selected	O
specifically	O
to	O
ensure	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
legacy	O
SATA	O
devices	O
where	O
possible	O
,	O
without	O
the	O
need	O
for	O
additional	O
adapters	O
or	O
converters	O
.	O
</s>
<s>
The	O
connector	O
on	O
the	O
host	O
side	O
accepts	O
either	O
one	O
PCI	O
Express	O
SSD	B-Device
or	O
up	O
to	O
two	O
legacy	O
SATA	O
devices	O
,	O
by	O
providing	O
either	O
PCI	O
Express	O
lanes	O
or	O
SATA3.0	O
ports	O
depending	O
on	O
the	O
type	O
of	O
connected	O
storage	O
device	O
.	O
</s>
<s>
There	O
are	O
five	O
types	O
of	O
SATA	B-Architecture
Express	I-Architecture
connectors	O
,	O
differing	O
by	O
their	O
position	O
and	O
purpose	O
:	O
</s>
<s>
Host	O
plug	O
is	O
used	O
on	O
motherboards	B-Device
and	O
add-on	O
controllers	O
.	O
</s>
<s>
This	O
connector	O
is	O
backward	B-General_Concept
compatible	I-General_Concept
by	O
accepting	O
legacy	O
standard	O
SATA	O
data	O
cables	O
,	O
resulting	O
in	O
the	O
host	O
plug	O
providing	O
connectivity	O
for	O
up	O
to	O
two	O
SATA	O
devices	O
.	O
</s>
<s>
Host	O
cable	O
receptacle	O
is	O
the	O
host-side	O
connector	O
on	O
SATA	B-Architecture
Express	I-Architecture
cables	O
.	O
</s>
<s>
This	O
connector	O
is	O
not	O
backward	B-General_Concept
compatible	I-General_Concept
.	O
</s>
<s>
Device	O
cable	O
receptacle	O
is	O
the	O
device-side	O
connector	O
on	O
SATA	B-Architecture
Express	I-Architecture
cables	O
,	O
backward	B-General_Concept
compatible	I-General_Concept
by	O
accepting	O
one	O
SATA	O
device	O
.	O
</s>
<s>
Device	O
plug	O
is	O
used	O
on	O
SATA	B-Architecture
Express	I-Architecture
devices	O
.	O
</s>
<s>
This	O
connector	O
is	O
partially	O
backward	B-General_Concept
compatible	I-General_Concept
by	O
allowing	O
SATA	B-Architecture
Express	I-Architecture
devices	O
to	O
be	O
plugged	O
into	O
U.2	B-Protocol
backplanes	O
or	O
MultiLink	O
SAS	O
receptacles	O
;	O
however	O
,	O
a	O
SATA	B-Architecture
Express	I-Architecture
device	O
connected	O
that	O
way	O
will	O
be	O
functional	O
only	O
if	O
the	O
host	O
supports	O
PCI	O
Express	O
devices	O
.	O
</s>
<s>
Host	O
receptacle	O
is	O
used	O
on	O
backplanes	O
for	O
mating	O
directly	O
with	O
SATA	B-Architecture
Express	I-Architecture
devices	O
,	O
resulting	O
in	O
cableless	O
connections	O
.	O
</s>
<s>
This	O
connector	O
is	O
backward	B-General_Concept
compatible	I-General_Concept
by	O
accepting	O
one	O
SATA	O
device	O
.	O
</s>
<s>
The	O
above	O
listed	O
SATA	B-Architecture
Express	I-Architecture
connectors	O
provide	O
only	O
two	O
PCI	O
Express	O
lanes	O
,	O
as	O
the	O
result	O
of	O
overall	O
design	O
focusing	O
on	O
a	O
rapid	O
low-cost	O
platform	O
transition	O
.	O
</s>
<s>
That	O
choice	O
allowed	O
easier	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
legacy	O
SATA	O
devices	O
,	O
together	O
with	O
making	O
it	O
possible	O
to	O
use	O
cheaper	O
unshielded	O
cables	O
.	O
</s>
<s>
,	O
some	O
NVM	B-Application
Express	I-Application
devices	O
in	O
form	O
of	O
2.5-inch	O
drives	O
use	O
the	O
U.2	B-Protocol
connector	O
(	O
originally	O
known	O
as	O
SFF-8639	O
,	O
with	O
the	O
renaming	O
taking	O
place	O
in	O
June	O
2015	O
)	O
,	O
which	O
is	O
expected	O
to	O
gain	O
broader	O
acceptance	O
.	O
</s>
<s>
The	O
U.2	B-Protocol
connector	O
is	O
mechanically	O
identical	O
to	O
the	O
SATA	B-Architecture
Express	I-Architecture
device	O
plug	O
,	O
but	O
provides	O
four	O
PCI	O
Express	O
lanes	O
through	O
a	O
different	O
usage	O
of	O
available	O
pins	O
.	O
</s>
<s>
Device-level	O
backward	B-General_Concept
compatibility	I-General_Concept
for	O
SATA	B-Architecture
Express	I-Architecture
is	O
ensured	O
by	O
fully	O
supporting	O
legacy	O
SATA3.0	O
(	O
6Gbit/s	O
)	O
storage	O
devices	O
,	O
both	O
on	O
the	O
electrical	O
level	O
and	O
through	O
the	O
required	O
operating	B-General_Concept
system	I-General_Concept
support	O
.	O
</s>
<s>
Mechanically	O
,	O
connectors	O
on	O
the	O
host	O
side	O
retain	O
their	O
backward	B-General_Concept
compatibility	I-General_Concept
in	O
a	O
way	O
similar	O
to	O
how	O
USB	O
3.0	O
does	O
it	O
the	O
new	O
host-side	O
SATA	B-Architecture
Express	I-Architecture
connector	O
is	O
made	O
by	O
"	O
stacking	O
"	O
an	O
additional	O
connector	O
on	O
top	O
of	O
two	O
legacy	O
standard	O
SATA	O
data	O
connectors	O
,	O
which	O
are	O
regular	O
SATA3.0	O
(	O
6Gbit/s	O
)	O
ports	O
that	O
can	O
accept	O
legacy	O
SATA	O
devices	O
.	O
</s>
<s>
This	O
backward	B-General_Concept
compatibility	I-General_Concept
of	O
the	O
host-side	O
SATA	B-Architecture
Express	I-Architecture
connector	O
,	O
which	O
is	O
formally	O
known	O
as	O
the	O
host	O
plug	O
,	O
ensures	O
the	O
possibility	O
for	O
attaching	O
legacy	O
SATA	O
devices	O
to	O
hosts	O
equipped	O
with	O
SATA	B-Architecture
Express	I-Architecture
controllers	O
.	O
</s>
<s>
Backward	B-General_Concept
compatibility	I-General_Concept
on	O
the	O
software	O
level	O
,	O
provided	O
for	O
legacy	O
operating	B-General_Concept
systems	I-General_Concept
and	O
associated	O
device	B-Application
drivers	I-Application
that	O
can	O
access	O
only	O
SATA	O
storage	O
devices	O
,	O
is	O
achieved	O
by	O
retaining	O
support	O
for	O
the	O
AHCI	O
controller	B-Architecture
interface	I-Architecture
as	O
a	O
legacy	O
logical	O
device	O
interface	B-Application
,	O
as	O
visible	O
from	O
the	O
operating	B-General_Concept
system	I-General_Concept
perspective	O
.	O
</s>
<s>
Access	O
to	O
storage	O
devices	O
using	O
AHCI	O
as	O
a	O
logical	O
device	O
interface	B-Application
is	O
possible	O
for	O
both	O
SATA	O
SSDs	B-Device
and	O
PCI	O
Express	O
SSDs	B-Device
,	O
so	O
operating	B-General_Concept
systems	I-General_Concept
that	O
do	O
not	O
provide	O
support	O
for	O
NVMe	B-Application
can	O
optionally	O
be	O
configured	O
to	O
interact	O
with	O
PCI	O
Express	O
storage	O
devices	O
as	O
if	O
they	O
were	O
legacy	O
AHCI	O
devices	O
.	O
</s>
<s>
However	O
,	O
because	O
NVMe	B-Application
is	O
far	O
more	O
efficient	O
than	O
AHCI	O
when	O
used	O
with	O
PCI	O
Express	O
SSDs	B-Device
,	O
SATA	B-Architecture
Express	I-Architecture
interface	B-Application
is	O
unable	O
to	O
deliver	O
its	O
maximum	O
performance	O
when	O
AHCI	O
is	O
used	O
to	O
access	O
PCI	O
Express	O
storage	O
devices	O
;	O
see	O
above	O
for	O
more	O
details	O
.	O
</s>
