<s>
The	O
MOS	B-Architecture
Technology	I-Architecture
6502	O
(	O
typically	O
pronounced	O
"	O
sixty-five-oh-two	O
"	O
or	O
"	O
six-five-oh-two	O
"	O
)	O
is	O
an	O
8-bit	O
microprocessor	B-Architecture
that	O
was	O
designed	O
by	O
a	O
small	O
team	O
led	O
by	O
Chuck	O
Peddle	O
for	O
MOS	B-Architecture
Technology	I-Architecture
.	O
</s>
<s>
The	O
design	O
team	O
had	O
formerly	O
worked	O
at	O
Motorola	O
on	O
the	O
Motorola	B-Device
6800	I-Device
project	O
;	O
the	O
6502	O
is	O
essentially	O
a	O
simplified	O
,	O
less	O
expensive	O
and	O
faster	O
version	O
of	O
that	O
design	O
.	O
</s>
<s>
When	O
it	O
was	O
introduced	O
in	O
1975	O
,	O
the	O
6502	O
was	O
the	O
least	O
expensive	O
microprocessor	B-Architecture
on	O
the	O
market	O
by	O
a	O
considerable	O
margin	O
.	O
</s>
<s>
It	O
initially	O
sold	O
for	O
less	O
than	O
one-sixth	O
the	O
cost	O
of	O
competing	O
designs	O
from	O
larger	O
companies	O
,	O
such	O
as	O
the	O
6800	O
or	O
Intel	B-General_Concept
8080	I-General_Concept
.	O
</s>
<s>
Along	O
with	O
the	O
Zilog	B-General_Concept
Z80	I-General_Concept
,	O
it	O
sparked	O
a	O
series	O
of	O
projects	O
that	O
resulted	O
in	O
the	O
home	O
computer	O
revolution	O
of	O
the	O
early	O
1980s	O
.	O
</s>
<s>
Popular	O
video	B-Device
game	I-Device
consoles	I-Device
and	O
home	O
computers	O
of	O
the	O
1980s	O
and	O
early	O
1990s	O
,	O
such	O
as	O
the	O
Atari	B-General_Concept
2600	I-General_Concept
,	O
Atari	B-Device
8-bit	I-Device
family	I-Device
,	O
Apple	B-Device
II	I-Device
,	O
Nintendo	O
Entertainment	O
System	O
,	O
Commodore	O
64	O
,	O
Atari	B-General_Concept
Lynx	I-General_Concept
,	O
BBC	B-Device
Micro	I-Device
and	O
others	O
,	O
use	O
the	O
6502	O
or	O
variations	O
of	O
the	O
basic	O
design	O
.	O
</s>
<s>
Soon	O
after	O
the	O
6502	O
's	O
introduction	O
,	O
MOS	B-Architecture
Technology	I-Architecture
was	O
purchased	O
outright	O
by	O
Commodore	O
International	O
,	O
who	O
continued	O
to	O
sell	O
the	O
microprocessor	B-Architecture
and	O
licenses	O
to	O
other	O
manufacturers	O
.	O
</s>
<s>
In	O
1981	O
,	O
the	O
Western	O
Design	O
Center	O
started	O
development	O
of	O
a	O
CMOS	B-Device
version	O
,	O
the	O
65C02	B-General_Concept
.	O
</s>
<s>
This	O
continues	O
to	O
be	O
widely	O
used	O
in	O
embedded	B-Architecture
systems	I-Architecture
,	O
with	O
estimated	O
production	O
volumes	O
in	O
the	O
hundreds	O
of	O
millions	O
.	O
</s>
<s>
The	O
6502	O
was	O
designed	O
by	O
many	O
of	O
the	O
same	O
engineers	O
that	O
had	O
designed	O
the	O
Motorola	B-Device
6800	I-Device
microprocessor	B-Architecture
family	O
.	O
</s>
<s>
Motorola	O
started	O
the	O
6800	O
microprocessor	B-Architecture
project	O
in	O
1971	O
with	O
Tom	O
Bennett	O
as	O
the	O
main	O
architect	O
.	O
</s>
<s>
His	O
first	O
assignment	O
was	O
helping	O
define	O
the	O
peripheral	O
ICs	O
for	O
the	O
6800	O
family	O
and	O
later	O
he	O
was	O
the	O
principal	O
designer	O
of	O
the	O
6820	O
Peripheral	B-General_Concept
Interface	I-General_Concept
Adapter	I-General_Concept
(	O
PIA	O
)	O
.	O
</s>
<s>
Motorola	O
's	O
engineers	O
could	O
run	O
analog	O
and	O
digital	O
simulations	O
on	O
an	O
IBM	B-Device
370-165	I-Device
mainframe	O
computer	O
.	O
</s>
<s>
In	O
May	O
1972	O
,	O
Motorola	O
's	O
engineers	O
began	O
visiting	O
select	O
customers	O
and	O
sharing	O
the	O
details	O
of	O
their	O
proposed	O
8-bit	O
microprocessor	B-Architecture
system	O
with	O
ROM	O
,	O
RAM	O
,	O
parallel	O
and	O
serial	O
interfaces	O
.	O
</s>
<s>
Motorola	O
's	O
"	O
total	O
product	O
family	O
"	O
strategy	O
did	O
not	O
focus	O
on	O
the	O
price	O
of	O
the	O
microprocessor	B-Architecture
,	O
but	O
on	O
reducing	O
the	O
customer	O
's	O
total	O
design	O
cost	O
.	O
</s>
<s>
Both	O
Intel	O
and	O
Motorola	O
had	O
initially	O
announced	O
a	O
$360	O
price	O
for	O
a	O
single	O
microprocessor	B-Architecture
.	O
</s>
<s>
Peddle	O
,	O
who	O
would	O
accompany	O
the	O
salespeople	O
on	O
customer	O
visits	O
,	O
found	O
that	O
customers	O
were	O
put	O
off	O
by	O
the	O
high	O
cost	O
of	O
the	O
microprocessor	B-Architecture
chips	O
.	O
</s>
<s>
Peddle	O
and	O
other	O
team	O
members	O
started	O
outlining	O
the	O
design	O
of	O
an	O
improved	O
feature	O
,	O
reduced	O
size	O
microprocessor	B-Architecture
.	O
</s>
<s>
Motorola	O
's	O
Semiconductor	O
Products	O
Division	O
management	O
was	O
overwhelmed	O
with	O
problems	O
and	O
showed	O
no	O
interest	O
in	O
Peddle	O
's	O
low-cost	O
microprocessor	B-Architecture
proposal	O
.	O
</s>
<s>
Paivinen	O
then	O
formed	O
MOS	B-Architecture
Technology	I-Architecture
in	O
Valley	O
Forge	O
,	O
Pennsylvania	O
in	O
1969	O
with	O
two	O
other	O
executives	O
from	O
General	O
Instrument	O
,	O
Mort	O
Jaffe	O
and	O
Don	O
McLaughlin	O
.	O
</s>
<s>
The	O
goal	O
of	O
the	O
team	O
was	O
to	O
design	O
and	O
produce	O
a	O
low-cost	O
microprocessor	B-Architecture
for	O
embedded	O
applications	O
and	O
to	O
target	O
as	O
wide	O
as	O
possible	O
a	O
customer	O
base	O
.	O
</s>
<s>
This	O
would	O
be	O
possible	O
only	O
if	O
the	O
microprocessor	B-Architecture
was	O
low	O
cost	O
,	O
and	O
the	O
team	O
set	O
the	O
price	O
goal	O
at	O
in	O
volume	O
.	O
</s>
<s>
Mensch	O
later	O
stated	O
the	O
goal	O
was	O
not	O
the	O
processor	O
price	O
itself	O
,	O
but	O
to	O
create	O
a	O
set	O
of	O
chips	O
that	O
could	O
sell	O
at	O
to	O
compete	O
with	O
the	O
recently-introduced	O
Intel	B-General_Concept
4040	I-General_Concept
that	O
sold	O
for	O
in	O
a	O
similar	O
complete	O
chipset	O
.	O
</s>
<s>
Chips	O
are	O
produced	O
by	O
printing	O
multiple	O
copies	O
of	O
the	O
chip	O
design	O
on	O
the	O
surface	O
of	O
a	O
"	B-Architecture
wafer	I-Architecture
"	I-Architecture
,	O
a	O
thin	O
disk	B-Device
of	O
highly	O
pure	O
silicon	O
.	O
</s>
<s>
Smaller	O
chips	O
can	O
be	O
printed	O
in	O
greater	O
numbers	O
on	O
the	O
same	O
wafer	B-Architecture
,	O
decreasing	O
their	O
relative	O
price	O
.	O
</s>
<s>
Additionally	O
,	O
wafers	B-Architecture
always	O
include	O
some	O
number	O
of	O
tiny	O
physical	O
defects	O
that	O
are	O
scattered	O
across	O
the	O
surface	O
.	O
</s>
<s>
The	O
first	O
was	O
the	O
move	O
to	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
.	O
</s>
<s>
The	O
6800	O
used	O
an	O
early	O
NMOS	B-Algorithm
process	O
that	O
required	O
three	O
supply	O
voltages	O
,	O
but	O
one	O
of	O
the	O
chip	O
's	O
features	O
was	O
an	O
onboard	O
voltage	O
doubler	O
that	O
allowed	O
a	O
single	O
+5V	O
supply	O
be	O
used	O
for	O
+5	O
,	O
−5	O
and	O
+12V	O
internally	O
,	O
as	O
opposed	O
to	O
other	O
chips	O
of	O
the	O
era	O
like	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
that	O
required	O
three	O
separate	O
supply	O
pins	O
.	O
</s>
<s>
With	O
the	O
reduced	O
power	O
requirements	O
of	O
NMOS	B-Algorithm
,	O
the	O
clock	O
could	O
be	O
moved	O
onto	O
the	O
chip	O
,	O
simplifying	O
the	O
overall	O
computer	O
design	O
.	O
</s>
<s>
Previously	O
,	O
chips	O
were	O
patterned	O
onto	O
the	O
surface	O
of	O
the	O
wafer	B-Architecture
by	O
placing	O
a	O
mask	B-Algorithm
on	O
the	O
surface	O
of	O
the	O
wafer	B-Architecture
and	O
then	O
shining	O
a	O
bright	O
light	O
on	O
it	O
.	O
</s>
<s>
In	O
1973	O
,	O
Perkin-Elmer	O
introduced	O
the	O
Micralign	B-Algorithm
system	O
,	O
which	O
projected	O
an	O
image	O
of	O
the	O
mask	B-Algorithm
on	O
the	O
wafer	B-Architecture
instead	O
of	O
requiring	O
direct	O
contact	O
.	O
</s>
<s>
Masks	O
no	O
longer	O
picked	O
up	O
dirt	O
from	O
the	O
wafers	B-Architecture
and	O
lasted	O
on	O
the	O
order	O
of	O
100,000	O
uses	O
rather	O
than	O
10	O
.	O
</s>
<s>
This	O
meant	O
the	O
price	O
of	O
the	O
CPU	B-General_Concept
declined	O
roughly	O
the	O
same	O
amount	O
and	O
the	O
microprocessor	B-Architecture
suddenly	O
became	O
a	O
commodity	O
device	O
.	O
</s>
<s>
MOS	B-Architecture
Technology	I-Architecture
's	O
existing	O
fabrication	O
lines	O
were	O
based	O
on	O
the	O
older	O
PMOS	O
technology	O
,	O
they	O
had	O
not	O
yet	O
begun	O
to	O
work	O
with	O
NMOS	B-Algorithm
when	O
the	O
team	O
arrived	O
.	O
</s>
<s>
Paivinen	O
promised	O
to	O
have	O
an	O
NMOS	B-Algorithm
line	O
up	O
and	O
running	O
in	O
time	O
to	O
begin	O
the	O
production	O
of	O
the	O
new	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
MOS	B-Architecture
Technology	I-Architecture
650X	O
family	O
represents	O
a	O
conscious	O
attempt	O
of	O
eight	O
former	O
Motorola	O
employees	O
who	O
worked	O
on	O
the	O
development	O
of	O
the	O
6800	O
system	O
to	O
put	O
out	O
a	O
part	O
that	O
would	O
replace	O
and	O
outperform	O
the	O
6800	O
,	O
yet	O
undersell	O
it	O
.	O
</s>
<s>
With	O
the	O
benefit	O
of	O
hindsight	O
gained	O
on	O
the	O
6800	O
project	O
,	O
the	O
MOS	B-Architecture
Technology	I-Architecture
team	O
headed	O
by	O
Chuck	O
Peddle	O
,	O
made	O
the	O
following	O
architectural	O
changes	O
in	O
the	O
Motorola	O
CPU	B-General_Concept
…	O
</s>
<s>
The	O
main	O
change	O
in	O
terms	O
of	O
chip	O
size	O
was	O
the	O
elimination	O
of	O
the	O
tri-state	B-Device
drivers	I-Device
from	O
the	O
address	B-Architecture
bus	I-Architecture
outputs	O
.	O
</s>
<s>
A	O
three-state	B-Device
bus	O
has	O
states	O
for	O
"	O
1	O
"	O
,	O
"	O
0	O
"	O
and	O
"	O
high	O
impedance	O
"	O
.	O
</s>
<s>
The	O
last	O
state	O
is	O
used	O
to	O
allow	O
other	O
devices	O
to	O
access	O
the	O
bus	O
,	O
and	O
is	O
typically	O
used	O
for	O
multiprocessing	B-Operating_System
,	O
or	O
more	O
commonly	O
in	O
these	O
roles	O
,	O
for	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	B-General_Concept
)	O
.	O
</s>
<s>
The	O
next	O
major	O
difference	O
was	O
to	O
simplify	O
the	O
registers	B-General_Concept
.	O
</s>
<s>
To	O
start	O
with	O
,	O
one	O
of	O
the	O
two	O
accumulators	B-General_Concept
was	O
removed	O
.	O
</s>
<s>
General-purpose	O
registers	B-General_Concept
like	O
accumulators	B-General_Concept
have	O
to	O
be	O
accessed	O
by	O
many	O
parts	O
of	O
the	O
instruction	O
decoder	O
,	O
and	O
thus	O
require	O
significant	O
amounts	O
of	O
wiring	O
to	O
move	O
data	O
to	O
and	O
from	O
their	O
storage	O
.	O
</s>
<s>
Two	O
accumulators	B-General_Concept
makes	O
many	O
coding	O
tasks	O
easier	O
,	O
but	O
costs	O
the	O
chip	O
design	O
itself	O
significant	O
complexity	O
.	O
</s>
<s>
Further	O
savings	O
were	O
made	O
by	O
reducing	O
the	O
stack	B-General_Concept
register	I-General_Concept
from	O
16	O
to	O
8	O
bits	O
,	O
meaning	O
that	O
the	O
stack	B-Application
could	O
only	O
be	O
256	O
bytes	O
long	O
,	O
which	O
was	O
enough	O
for	O
its	O
intended	O
role	O
as	O
a	O
microcontroller	O
.	O
</s>
<s>
The	O
16-bit	B-Device
IX	O
index	B-General_Concept
register	I-General_Concept
was	O
split	O
in	O
two	O
,	O
becoming	O
X	O
and	O
Y	O
.	O
</s>
<s>
More	O
importantly	O
,	O
the	O
style	O
of	O
access	O
changed	O
;	O
in	O
the	O
6800	O
,	O
IX	O
held	O
a	O
16-bit	B-Device
address	O
,	O
which	O
was	O
offset	O
by	O
an	O
8-bit	O
number	O
supplied	O
with	O
the	O
instruction	O
,	O
the	O
two	O
were	O
added	O
to	O
produce	O
the	O
final	O
address	O
.	O
</s>
<s>
In	O
the	O
6502	O
(	O
and	O
most	O
other	O
contemporary	O
designs	O
)	O
,	O
the	O
16-bit	B-Device
base	O
address	O
was	O
stored	O
in	O
the	O
instruction	O
,	O
and	O
the	O
X	O
or	O
Y	O
was	O
added	O
to	O
it	O
.	O
</s>
<s>
Among	O
those	O
removed	O
were	O
instructions	O
that	O
moved	O
data	O
between	O
the	O
6800	O
's	O
two	O
accumulators	B-General_Concept
,	O
and	O
several	O
branch	O
instructions	O
inspired	O
by	O
the	O
PDP-11	B-Device
,	O
such	O
as	O
the	O
ability	O
to	O
directly	O
compare	O
two	O
numeric	O
values	O
.	O
</s>
<s>
At	O
MOS	B-Architecture
Technology	I-Architecture
,	O
the	O
"	O
layout	O
"	O
was	O
a	O
very	O
manual	O
process	O
done	O
with	O
color	O
pencils	O
and	O
vellum	O
paper	O
.	O
</s>
<s>
Mensch	O
and	O
Paivinen	O
worked	O
on	O
the	O
instruction	O
decoder	O
while	O
Mensch	O
,	O
Peddle	O
and	O
Orgill	O
worked	O
on	O
the	O
ALU	O
and	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
original	O
version	O
of	O
the	O
processor	O
had	O
no	O
rotate	B-Algorithm
right	I-Algorithm
(	O
ROR	B-Algorithm
)	O
capability	O
,	O
so	O
the	O
instruction	O
was	O
omitted	O
from	O
the	O
original	O
documentation	O
.	O
</s>
<s>
The	O
next	O
iteration	O
of	O
the	O
design	O
shrank	O
the	O
chip	O
and	O
added	O
the	O
rotate	B-Algorithm
right	I-Algorithm
capability	O
,	O
and	O
ROR	B-Algorithm
was	O
included	O
in	O
revised	O
documentation	O
.	O
</s>
<s>
MOS	O
would	O
introduce	O
two	O
microprocessors	B-Architecture
based	O
on	O
the	O
same	O
underlying	O
design	O
:	O
the	O
6501	O
would	O
plug	O
into	O
the	O
same	O
socket	O
as	O
the	O
Motorola	B-Device
6800	I-Device
,	O
while	O
the	O
6502	O
re-arranged	O
the	O
pinout	O
to	O
support	O
an	O
on-chip	O
clock	O
oscillator	O
.	O
</s>
<s>
They	O
would	O
not	O
run	O
6800	O
software	O
because	O
they	O
had	O
a	O
different	O
instruction	O
set	O
,	O
different	O
registers	B-General_Concept
,	O
and	O
mostly	O
different	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
Bill	O
Mensch	O
did	O
the	O
6502	O
;	O
he	O
was	O
the	O
designer	O
of	O
the	O
6820	O
Peripheral	B-General_Concept
Interface	I-General_Concept
Adapter	I-General_Concept
(	O
PIA	O
)	O
at	O
Motorola	O
.	O
</s>
<s>
MOS	B-Architecture
Technology	I-Architecture
's	O
microprocessor	B-Architecture
introduction	O
was	O
different	O
from	O
the	O
traditional	O
months-long	O
product	O
launch	O
.	O
</s>
<s>
Peddle	O
was	O
a	O
very	O
effective	O
spokesman	O
and	O
the	O
MOS	B-Architecture
Technology	I-Architecture
microprocessors	B-Architecture
were	O
extensively	O
covered	O
in	O
the	O
trade	O
press	O
.	O
</s>
<s>
One	O
of	O
the	O
earliest	O
was	O
a	O
full-page	O
story	O
on	O
the	O
MCS6501	O
and	O
MCS6502	O
microprocessors	B-Architecture
in	O
the	O
July	O
24	O
,	O
1975	O
issue	O
of	O
Electronics	O
magazine	O
.	O
</s>
<s>
Stories	O
also	O
ran	O
in	O
EE	O
Times	O
(	O
August	O
24	O
,	O
1975	O
)	O
,	O
EDN	O
(	O
September	O
20	O
,	O
1975	O
)	O
,	O
Electronic	O
News	O
(	O
November	O
3	O
,	O
1975	O
)	O
,	O
Byte	O
(	O
November	O
1975	O
)	O
and	O
Microcomputer	B-Architecture
Digest	O
(	O
November	O
1975	O
)	O
.	O
</s>
<s>
In	O
September	O
1975	O
,	O
the	O
advertisements	O
included	O
both	O
the	O
6501	O
and	O
the	O
6502	O
microprocessors	B-Architecture
.	O
</s>
<s>
When	O
MOS	B-Architecture
Technology	I-Architecture
arrived	O
at	O
Wescon	O
,	O
they	O
found	O
that	O
exhibitors	O
were	O
not	O
permitted	O
to	O
sell	O
anything	O
on	O
the	O
show	O
floor	O
.	O
</s>
<s>
Users	O
were	O
encouraged	O
to	O
make	O
photocopies	O
of	O
the	O
documents	O
,	O
an	O
inexpensive	O
way	O
for	O
MOS	B-Architecture
Technology	I-Architecture
to	O
distribute	O
product	O
information	O
.	O
</s>
<s>
The	O
preliminary	O
data	O
sheets	O
listed	O
just	O
55	O
instructions	O
excluding	O
the	O
Rotate	B-Algorithm
Right	I-Algorithm
(	O
ROR	B-Algorithm
)	O
instruction	O
which	O
was	O
not	O
supported	O
on	O
these	O
early	O
chips	O
.	O
</s>
<s>
The	O
reviews	O
in	O
Byte	O
and	O
EDN	O
noted	O
the	O
lack	O
of	O
the	O
ROR	B-Algorithm
instruction	O
.	O
</s>
<s>
For	O
example	O
,	O
Signetics	O
was	O
introducing	O
the	O
2650	B-General_Concept
microprocessor	B-Architecture
and	O
its	O
advertisements	O
asked	O
readers	O
to	O
write	O
for	O
information	O
on	O
their	O
company	O
letterhead	O
.	O
</s>
<s>
In	O
October	O
1975	O
,	O
Motorola	O
reduced	O
the	O
price	O
of	O
a	O
single	O
6800	O
microprocessor	B-Architecture
from	O
to	O
.	O
</s>
<s>
On	O
November	O
3	O
,	O
1975	O
,	O
Motorola	O
sought	O
an	O
injunction	O
in	O
Federal	O
Court	O
to	O
stop	O
MOS	B-Architecture
Technology	I-Architecture
from	O
making	O
and	O
selling	O
microprocessor	B-Architecture
products	O
.	O
</s>
<s>
Motorola	O
claimed	O
that	O
seven	O
former	O
employees	O
joined	O
MOS	B-Architecture
Technology	I-Architecture
to	O
create	O
that	O
company	O
's	O
microprocessor	B-Architecture
products	O
.	O
</s>
<s>
On	O
October	O
30	O
,	O
1974	O
,	O
Motorola	O
had	O
filed	O
numerous	O
patent	O
applications	O
on	O
the	O
microprocessor	B-Architecture
family	O
and	O
was	O
granted	O
twenty-five	O
patents	O
.	O
</s>
<s>
These	O
patents	O
covered	O
the	O
6800	O
bus	O
and	O
how	O
the	O
peripheral	O
chips	O
interfaced	O
with	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
Allen-Bradley	O
decided	O
not	O
to	O
fight	O
this	O
case	O
and	O
sold	O
their	O
interest	O
in	O
MOS	B-Architecture
Technology	I-Architecture
back	O
to	O
the	O
founders	O
.	O
</s>
<s>
During	O
the	O
discovery	O
process	O
,	O
Motorola	O
found	O
that	O
one	O
engineer	O
,	O
Mike	O
Janes	O
,	O
had	O
ignored	O
Peddle	O
's	O
instructions	O
and	O
brought	O
his	O
6800	O
design	O
documents	O
to	O
MOS	B-Architecture
Technology	I-Architecture
.	O
</s>
<s>
In	O
March	O
1976	O
,	O
the	O
now	O
independent	O
MOS	B-Architecture
Technology	I-Architecture
was	O
running	O
out	O
of	O
money	O
and	O
had	O
to	O
settle	O
the	O
case	O
.	O
</s>
<s>
Both	O
companies	O
agreed	O
to	O
cross-license	O
microprocessor	B-Architecture
patents	O
.	O
</s>
<s>
That	O
May	O
,	O
Motorola	O
dropped	O
the	O
price	O
of	O
a	O
single	O
6800	O
microprocessor	B-Architecture
to	O
.	O
</s>
<s>
By	O
November	O
,	O
Commodore	O
had	O
acquired	O
MOS	B-Architecture
Technology	I-Architecture
.	O
</s>
<s>
With	O
legal	O
troubles	O
behind	O
them	O
,	O
MOS	O
was	O
still	O
left	O
with	O
the	O
problem	O
of	O
getting	O
developers	O
to	O
try	O
their	O
processor	O
,	O
prompting	O
Chuck	O
Peddle	O
to	O
design	O
the	O
MDT-650	O
(	O
"	O
microcomputer	B-Architecture
development	O
terminal	O
"	O
)	O
single-board	B-Device
computer	I-Device
.	O
</s>
<s>
Another	O
group	O
inside	O
the	O
company	O
designed	O
the	O
KIM-1	B-Device
,	O
which	O
was	O
sold	O
semi-complete	O
and	O
could	O
be	O
turned	O
into	O
a	O
usable	O
system	O
with	O
the	O
addition	O
of	O
a	O
3rd	O
party	O
computer	B-General_Concept
terminal	I-General_Concept
and	O
compact	B-Device
cassette	I-Device
drive	O
.	O
</s>
<s>
While	O
it	O
sold	O
well	O
to	O
its	O
intended	O
market	O
,	O
the	O
company	O
found	O
the	O
KIM-1	B-Device
also	O
sold	O
well	O
to	O
hobbyists	O
and	O
tinkerers	O
.	O
</s>
<s>
The	O
related	O
Rockwell	B-Device
AIM-65	I-Device
control	O
,	O
training	O
,	O
and	O
development	O
system	O
also	O
did	O
well	O
.	O
</s>
<s>
The	O
software	O
in	O
the	O
AIM	B-Device
65	I-Device
was	O
based	O
on	O
that	O
in	O
the	O
MDT	O
.	O
</s>
<s>
Another	O
roughly	O
similar	O
product	O
was	O
the	O
Synertek	O
SYM-1	B-Device
.	O
</s>
<s>
One	O
of	O
the	O
first	O
"	O
public	O
"	O
uses	O
for	O
the	O
design	O
was	O
the	O
Apple	B-Device
I	I-Device
microcomputer	B-Architecture
,	O
introduced	O
in	O
1976	O
.	O
</s>
<s>
The	O
6502	O
was	O
next	O
used	O
in	O
the	O
Commodore	B-Device
PET	I-Device
and	O
the	O
Apple	B-Device
II	I-Device
,	O
both	O
released	O
in	O
1977	O
.	O
</s>
<s>
It	O
was	O
later	O
used	O
in	O
the	O
Atari	B-Device
8-bit	I-Device
family	I-Device
and	O
Acorn	B-Device
Atom	I-Device
home	O
computers	O
,	O
the	O
BBC	B-Device
Micro	I-Device
,	O
VIC-20	B-Device
and	O
other	O
designs	O
both	O
for	O
home	O
computers	O
and	O
business	O
,	O
such	O
as	O
Ohio	B-Application
Scientific	I-Application
and	O
Oric	B-Device
.	O
</s>
<s>
The	O
6510	B-General_Concept
,	O
a	O
direct	O
successor	O
of	O
the	O
6502	O
with	O
a	O
digital	O
I/O	O
port	O
and	O
a	O
tri-state	O
address	B-Architecture
bus	I-Architecture
,	O
was	O
the	O
CPU	B-General_Concept
utilized	O
in	O
the	O
best-selling	O
Commodore	O
64	O
home	O
computer	O
.	O
</s>
<s>
The	O
first	O
to	O
make	O
use	O
of	O
the	O
processor	O
design	O
was	O
the	O
1977	O
Atari	B-General_Concept
VCS	I-General_Concept
,	O
later	O
renamed	O
the	O
Atari	B-General_Concept
2600	I-General_Concept
.	O
</s>
<s>
The	O
VCS	O
used	O
a	O
6502	O
variant	O
named	O
the	O
6507	B-General_Concept
,	O
which	O
had	O
fewer	O
pins	O
,	O
so	O
it	O
could	O
address	O
only	O
8KB	O
of	O
memory	O
.	O
</s>
<s>
The	O
6502	O
used	O
in	O
the	O
NES	O
was	O
a	O
second	O
source	O
version	O
by	O
Ricoh	O
,	O
a	O
partial	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
,	O
that	O
lacked	O
the	O
binary-coded	O
decimal	O
mode	O
but	O
added	O
22	O
memory-mapped	O
registers	B-General_Concept
and	O
on-die	O
hardware	O
for	O
sound	O
generation	O
,	O
joypad	O
reading	O
,	O
and	O
sprite	O
list	O
DMA	B-General_Concept
.	O
</s>
<s>
Called	O
2A03	B-General_Concept
in	O
NTSC	O
consoles	O
and	O
2A07	B-General_Concept
in	O
PAL	B-Language
consoles	O
(	O
the	O
difference	O
being	O
the	O
memory	B-Device
divider	I-Device
ratio	O
and	O
a	O
lookup	O
table	O
for	O
audio	O
sample	O
rates	O
)	O
,	O
this	O
processor	O
was	O
produced	O
exclusively	O
for	O
Nintendo	O
.	O
</s>
<s>
The	O
Atari	B-General_Concept
Lynx	I-General_Concept
used	O
a	O
4MHz	O
version	O
of	O
the	O
chip	O
,	O
the	O
65SC02	O
.	O
</s>
<s>
6502	O
or	O
variants	O
were	O
used	O
in	O
all	O
of	O
Commodore	O
's	O
floppy	B-Device
disk	I-Device
drives	I-Device
for	O
all	O
of	O
their	O
8-bit	O
computers	O
,	O
from	O
the	O
PET	O
line	O
through	O
the	O
Commodore	O
128D	O
,	O
including	O
the	O
Commodore	O
64	O
.	O
</s>
<s>
8-inch	O
PET	O
drives	B-Device
had	O
two	O
6502	O
processors	O
.	O
</s>
<s>
Atari	O
used	O
the	O
same	O
6507	B-General_Concept
used	O
in	O
the	O
Atari	B-General_Concept
VCS	I-General_Concept
for	O
its	O
810	B-Device
and	O
1050	B-Device
disk	B-Device
drives	I-Device
used	O
for	O
all	O
of	O
their	O
8-bit	O
computer	O
line	O
,	O
from	O
the	O
400/800	O
through	O
the	O
XEGS	O
.	O
</s>
<s>
In	O
the	O
1980s	O
,	O
a	O
popular	O
electronics	O
magazine	O
Elektor/Elektuur	O
used	O
the	O
processor	O
in	O
its	O
microprocessor	B-Architecture
development	O
board	O
Junior	B-Device
Computer	I-Device
.	O
</s>
<s>
The	O
6502	O
is	O
a	O
little-endian	O
8-bit	O
processor	O
with	O
a	O
16-bit	B-Device
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Like	O
most	O
simple	O
CPUs	O
of	O
the	O
era	O
,	O
the	O
dynamic	O
NMOS	B-Algorithm
6502	O
chip	O
is	O
not	O
sequenced	O
by	O
a	O
microcode	B-Device
ROM	O
but	O
uses	O
a	O
PLA	O
(	O
which	O
occupied	O
about	O
15%	O
of	O
the	O
chip	O
area	O
)	O
for	O
instruction	O
decoding	O
and	O
sequencing	O
.	O
</s>
<s>
As	O
in	O
most	O
8-bit	O
microprocessors	B-Architecture
,	O
the	O
chip	O
does	O
some	O
limited	O
overlapping	O
of	O
fetching	O
and	O
execution	O
.	O
</s>
<s>
The	O
low	O
clock	O
frequency	O
moderated	O
the	O
speed	O
requirement	O
of	O
memory	O
and	O
peripherals	O
attached	O
to	O
the	O
CPU	B-General_Concept
,	O
as	O
only	O
about	O
50%	O
of	O
the	O
clock	O
cycle	O
was	O
available	O
for	O
memory	O
access	O
(	O
due	O
to	O
the	O
asynchronous	O
design	O
,	O
this	O
fraction	O
varied	O
strongly	O
among	O
chip	O
versions	O
)	O
.	O
</s>
<s>
This	O
technique	O
was	O
widely	O
used	O
by	O
computer	O
systems	O
;	O
they	O
would	O
use	O
memory	O
capable	O
of	O
access	O
at	O
2MHz	O
,	O
and	O
then	O
run	O
the	O
CPU	B-General_Concept
at	O
1MHz	O
.	O
</s>
<s>
This	O
guaranteed	O
that	O
the	O
CPU	B-General_Concept
and	O
video	O
hardware	O
could	O
interleave	O
their	O
accesses	O
,	O
with	O
a	O
total	O
performance	O
matching	O
that	O
of	O
the	O
memory	O
device	O
.	O
</s>
<s>
When	O
faster	O
memories	O
became	O
available	O
in	O
the	O
1980s	O
,	O
newer	O
machines	O
could	O
run	O
at	O
higher	O
clock	O
rates	O
,	O
like	O
the	O
2MHz	O
CPU	B-General_Concept
in	O
the	O
BBC	B-Device
Micro	I-Device
,	O
and	O
still	O
use	O
the	O
bus	O
sharing	O
techniques	O
.	O
</s>
<s>
Like	O
its	O
precursor	O
,	O
the	O
6800	O
,	O
the	O
6502	O
has	O
very	O
few	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
6502	O
's	O
registers	B-General_Concept
include	O
one	O
8-bit	O
accumulator	B-General_Concept
register	O
(	O
A	O
)	O
,	O
two	O
8-bit	O
index	B-General_Concept
registers	I-General_Concept
(	O
X	O
and	O
Y	O
)	O
,	O
7	O
processor	B-General_Concept
status	I-General_Concept
flag	I-General_Concept
bits	I-General_Concept
(	O
P	O
;	O
from	O
bit	O
7	O
to	O
bit	O
0	O
these	O
are	O
the	O
negative	O
(	O
N	B-Algorithm
)	O
,	O
overflow	O
(	O
V	B-Algorithm
)	O
,	O
reserved	O
,	O
break	O
(	O
B	O
)	O
,	O
decimal	O
(	O
D	O
)	O
,	O
interrupt	B-Application
disable	O
(	O
I	B-Device
)	O
,	O
zero	O
(	O
Z	B-Algorithm
)	O
and	O
carry	O
(	O
C	B-Algorithm
)	O
flag	O
)	O
,	O
an	O
8-bit	O
stack	B-Application
pointer	I-Application
(	O
S	O
)	O
,	O
and	O
a	O
16-bit	B-Device
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
.	O
</s>
<s>
This	O
compares	O
to	O
a	O
typical	O
design	O
of	O
the	O
same	O
era	O
,	O
the	O
Z80	B-General_Concept
,	O
which	O
has	O
eight	O
general-purpose	O
8-bit	O
registers	B-General_Concept
,	O
which	O
can	O
be	O
combined	O
into	O
four	O
16-bit	B-Device
ones	O
.	O
</s>
<s>
The	O
Z80	B-General_Concept
also	O
had	O
a	O
complete	O
set	O
of	O
alternate	O
registers	B-General_Concept
,	O
which	O
made	O
a	O
total	O
of	O
sixteen	O
general-purpose	O
registers	B-General_Concept
.	O
</s>
<s>
In	O
order	O
to	O
make	O
up	O
somewhat	O
for	O
the	O
lack	O
of	O
registers	B-General_Concept
,	O
the	O
6502	O
included	O
a	O
zero-page	O
addressing	B-Language
mode	I-Language
that	O
uses	O
one	O
address	O
byte	O
in	O
the	O
instruction	O
instead	O
of	O
the	O
two	O
needed	O
to	O
address	O
the	O
full	O
of	O
memory	O
.	O
</s>
<s>
Chuck	O
Peddle	O
has	O
said	O
in	O
interviews	O
that	O
the	O
specific	O
intention	O
was	O
to	O
allow	O
these	O
first	O
of	O
RAM	O
to	O
be	O
used	O
like	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
stack	B-Application
address	O
space	O
is	O
hardwired	O
to	O
memory	O
page	O
$01	O
,	O
i.e.	O
</s>
<s>
Software	O
access	O
to	O
the	O
stack	B-Application
is	O
done	O
via	O
four	O
implied	O
addressing	B-Language
mode	I-Language
instructions	O
,	O
whose	O
functions	O
are	O
to	O
push	O
or	O
pop	O
(	O
pull	O
)	O
the	O
accumulator	B-General_Concept
or	O
the	O
processor	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
same	O
stack	B-Application
is	O
also	O
used	O
for	O
subroutine	O
calls	O
via	O
the	O
JSR	O
(	O
jump	O
to	O
subroutine	O
)	O
and	O
RTS	O
(	O
return	O
from	O
subroutine	O
)	O
instructions	O
and	O
for	O
interrupt	B-Application
handling	I-Application
.	O
</s>
<s>
The	O
chip	O
uses	O
the	O
index	O
and	O
stack	B-General_Concept
registers	I-General_Concept
effectively	O
with	O
several	O
addressing	B-Language
modes	I-Language
,	O
including	O
a	O
fast	O
"	O
direct	O
page	O
"	O
or	O
"	O
zero	B-General_Concept
page	I-General_Concept
"	O
mode	O
,	O
similar	O
to	O
that	O
found	O
on	O
the	O
PDP-8	B-Device
,	O
that	O
accesses	O
memory	O
locations	O
from	O
addresses	O
0	O
to	O
255	O
with	O
a	O
single	O
8-bit	O
address	O
(	O
saving	O
the	O
cycle	O
normally	O
required	O
to	O
fetch	O
the	O
high-order	O
byte	O
of	O
the	O
address	O
)	O
code	O
for	O
the	O
6502	O
uses	O
the	O
zero	B-General_Concept
page	I-General_Concept
much	O
as	O
code	O
for	O
other	O
processors	O
would	O
use	O
registers	B-General_Concept
.	O
</s>
<s>
On	O
some	O
6502-based	O
microcomputers	B-Architecture
with	O
an	O
operating	B-General_Concept
system	I-General_Concept
,	O
the	O
operating	B-General_Concept
system	I-General_Concept
uses	O
most	O
of	O
zero	B-General_Concept
page	I-General_Concept
,	O
leaving	O
only	O
a	O
handful	O
of	O
locations	O
for	O
the	O
user	O
.	O
</s>
<s>
Addressing	B-Language
modes	I-Language
also	O
include	O
implied	O
(	O
1-byte	O
instructions	O
)	O
;	O
absolute	O
(	O
3	O
bytes	O
)	O
;	O
indexed	O
absolute	O
(	O
3	O
bytes	O
)	O
;	O
indexed	O
zero-page	O
(	O
2	O
bytes	O
)	O
;	O
relative	O
(	O
2	O
bytes	O
)	O
;	O
accumulator	B-General_Concept
(	O
1	O
)	O
;	O
indirect	O
,	O
x	O
and	O
indirect	O
,	O
y	O
(	O
2	O
)	O
;	O
and	O
immediate	O
(	O
2	O
)	O
.	O
</s>
<s>
Accumulator	B-General_Concept
mode	O
uses	O
the	O
accumulator	B-General_Concept
as	O
an	O
effective	B-Language
address	I-Language
and	O
does	O
not	O
need	O
any	O
operand	O
data	O
.	O
</s>
<s>
With	O
the	O
5/6	O
cycle	O
"	O
(	O
indirect	O
)	O
,	O
y	O
"	O
mode	O
,	O
the	O
8-bit	O
Y	O
register	O
is	O
added	O
to	O
a	O
16-bit	B-Device
base	O
address	O
read	O
from	O
zero	B-General_Concept
page	I-General_Concept
,	O
which	O
is	O
located	O
by	O
a	O
single	O
byte	O
following	O
the	O
opcode	B-Language
.	O
</s>
<s>
The	O
Y	O
register	O
is	O
therefore	O
an	O
index	B-General_Concept
register	I-General_Concept
in	O
the	O
sense	O
that	O
it	O
is	O
used	O
to	O
hold	O
an	O
actual	O
index	O
(	O
as	O
opposed	O
to	O
the	O
X	O
register	O
in	O
the	O
6800	O
,	O
where	O
a	O
base	O
address	O
was	O
directly	O
stored	O
and	O
to	O
which	O
an	O
immediate	O
offset	O
could	O
be	O
added	O
)	O
.	O
</s>
<s>
Incrementing	O
the	O
index	B-General_Concept
register	I-General_Concept
to	O
walk	O
the	O
array	O
byte-wise	O
takes	O
only	O
two	O
additional	O
cycles	O
.	O
</s>
<s>
With	O
the	O
less	O
frequently	O
used	O
"	O
(	O
indirect	O
,	O
x	O
)	O
"	O
mode	O
the	O
effective	B-Language
address	I-Language
for	O
the	O
operation	O
is	O
found	O
at	O
the	O
zero	B-General_Concept
page	I-General_Concept
address	O
formed	O
by	O
adding	O
the	O
second	O
byte	O
of	O
the	O
instruction	O
to	O
the	O
contents	O
of	O
the	O
X	O
register	O
.	O
</s>
<s>
Using	O
the	O
indexed	O
modes	O
,	O
the	O
zero	B-General_Concept
page	I-General_Concept
effectively	O
acts	O
as	O
a	O
set	O
of	O
up	O
to	O
128	O
additional	O
(	O
though	O
very	O
slow	O
)	O
address	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
Placing	O
the	O
CPU	B-General_Concept
into	O
BCD	O
mode	O
with	O
the	O
SED	O
(	O
set	O
D	O
flag	O
)	O
instruction	O
results	O
in	O
decimal	O
arithmetic	O
,	O
in	O
which	O
$99	O
+	O
$01	O
would	O
result	O
in	O
$00	O
and	O
the	O
carry	O
(	O
C	B-Algorithm
)	O
flag	O
being	O
set	O
.	O
</s>
<s>
In	O
binary	O
mode	O
(	O
CLD	O
,	O
clear	O
D	O
flag	O
)	O
,	O
the	O
same	O
operation	O
would	O
result	O
in	O
$9A	O
and	O
the	O
carry	B-Algorithm
flag	I-Algorithm
being	O
cleared	O
.	O
</s>
<s>
Other	O
than	O
Atari	B-Language
BASIC	I-Language
,	O
BCD	O
mode	O
was	O
seldom	O
used	O
in	O
home-computer	O
applications	O
.	O
</s>
<s>
article	O
for	O
a	O
simple	O
but	O
characteristic	O
example	O
of	O
6502	O
assembly	B-Language
language	I-Language
.	O
</s>
<s>
6502	O
instruction	O
operation	B-Language
codes	I-Language
(	O
opcodes	B-Language
)	O
are	O
8bits	O
long	O
and	O
have	O
the	O
general	O
form	O
AAABBBCC	O
,	O
where	O
AAA	O
and	O
CC	O
define	O
the	O
opcode	B-Language
,	O
and	O
BBB	O
defines	O
the	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
For	O
instance	O
,	O
consider	O
the	O
ORA	O
instruction	O
,	O
which	O
performs	O
a	O
bitwise	O
OR	O
on	O
the	O
bits	O
in	O
the	O
accumulator	B-General_Concept
with	O
another	O
value	O
.	O
</s>
<s>
The	O
instruction	B-Language
opcode	I-Language
is	O
of	O
the	O
form	O
000bbb01	O
,	O
where	O
bbb	O
may	O
be	O
010	O
for	O
an	O
immediate	O
mode	O
value	O
(	O
constant	O
)	O
,	O
001	O
for	O
zero-page	O
fixed	O
address	O
,	O
011	O
for	O
an	O
absolute	O
address	O
,	O
and	O
so	O
on	O
.	O
</s>
<s>
However	O
,	O
where	O
it	O
does	O
apply	O
,	O
it	O
allows	O
one	O
to	O
easily	O
deconstruct	O
opcode	B-Language
values	O
back	O
to	O
assembly	O
mnemonics	O
for	O
the	O
majority	O
of	O
instructions	O
,	O
handling	O
the	O
edge	O
cases	O
with	O
special-purpose	O
code	O
.	O
</s>
<s>
Of	O
the	O
256	O
possible	O
opcodes	B-Language
available	O
using	O
an	O
8-bit	O
pattern	O
,	O
the	O
original	O
6502	O
uses	O
151	O
of	O
them	O
,	O
organized	O
into	O
56	O
instructions	O
with	O
(	O
possibly	O
)	O
multiple	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
Depending	O
on	O
the	O
instruction	O
and	O
addressing	B-Language
mode	I-Language
,	O
the	O
opcode	B-Language
may	O
require	O
zero	O
,	O
one	O
or	O
two	O
additional	O
bytes	O
for	O
operands	O
.	O
</s>
<s>
The	O
65C816	B-General_Concept
,	O
the	O
16-bit	B-Device
CMOS	B-Device
descendant	O
of	O
the	O
6502	O
,	O
also	O
supports	O
24-bit	O
addressing	O
,	O
which	O
results	O
in	O
instructions	O
being	O
assembled	O
with	O
three-byte	O
operands	O
,	O
also	O
arranged	O
in	O
little-endian	O
format	O
.	O
</s>
<s>
The	O
remaining	O
105	O
opcodes	B-Language
are	O
undefined	O
.	O
</s>
<s>
Some	O
of	O
the	O
empty	O
slots	O
were	O
used	O
in	O
the	O
65C02	B-General_Concept
to	O
provide	O
both	O
new	O
instructions	O
and	O
variations	O
on	O
existing	O
ones	O
with	O
new	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
The	O
$Fx	O
instructions	O
were	O
initially	O
left	O
free	O
to	O
allow	O
3rd-party	O
vendors	O
to	O
add	O
their	O
own	O
instructions	O
,	O
but	O
later	O
versions	O
of	O
the	O
65C02	B-General_Concept
standardized	O
a	O
set	O
of	O
bit	B-Algorithm
manipulation	I-Algorithm
instructions	O
developed	O
by	O
Rockwell	O
Semiconductor	O
.	O
</s>
<s>
A	O
6502	O
assembly	B-Language
language	I-Language
statement	O
consists	O
of	O
a	O
three-character	O
instruction	O
mnemonic	O
,	O
followed	O
by	O
any	O
operands	O
.	O
</s>
<s>
Instructions	O
that	O
do	O
not	O
take	O
a	O
separate	O
operand	O
but	O
target	O
a	O
single	O
register	O
based	O
on	O
the	O
addressing	B-Language
mode	I-Language
combine	O
the	O
target	O
register	O
in	O
the	O
instruction	O
mnemonic	O
,	O
so	O
the	O
assembler	B-Language
uses	O
INX	O
as	O
opposed	O
to	O
INC	O
X	O
to	O
increment	O
the	O
X	O
register	O
.	O
</s>
<s>
Opcode	B-Language
matrix	O
for	O
the	O
6502	O
instruction	O
set	O
Addressing	B-Language
modes	I-Language
:	O
–	O
accumulator	B-General_Concept
,	O
–	O
immediate	O
,	O
–	O
zero	B-General_Concept
page	I-General_Concept
,	O
–	O
absolute	O
,	O
–	O
indirect	O
,	O
X	O
–	O
indexed	O
by	O
X	O
register	O
,	O
Y	O
–	O
indexed	O
by	O
Y	O
register	O
,	O
–	O
relative	O
High	O
nibble	O
Low	O
nibble	O
0	O
1	O
2	O
4	O
5	O
6	O
8	O
9	O
A	O
C	B-Algorithm
D	O
E	O
0BRKORA	O
(	O
ind	O
,	O
X	O
)	O
ORA	O
zpgASL	O
zpgPHPORA	O
#ASL	O
A	O
ORA	O
absASL	O
abs	O
1BPL	O
relORA	O
(	O
ind	O
)	O
,	O
Y	O
ORA	O
zpg	O
,	O
XASL	O
zpg	O
,	O
XCLCORA	O
abs	O
,	O
Y	O
ORA	O
abs	O
,	O
XASL	O
abs	O
,	O
X	O
2JSR	O
absAND	O
(	O
ind	O
,	O
X	O
)	O
BIT	O
zpgAND	O
zpgROL	O
zpgPLPAND	O
#ROL	O
ABIT	O
absAND	O
absROL	O
abs	O
3BMI	O
relAND	O
(	O
ind	O
)	O
,	O
Y	O
AND	O
zpg	O
,	O
XROL	O
zpg	O
,	O
XSECAND	O
abs	O
,	O
Y	O
AND	O
abs	O
,	O
XROL	O
abs	O
,	O
X	O
4RTIEOR	O
(	O
ind	O
,	O
X	O
)	O
EOR	O
zpgLSR	O
zpgPHAEOR	O
#LSR	O
AJMP	O
absEOR	O
absLSR	O
abs	O
5BVC	O
relEOR	O
(	O
ind	O
)	O
,	O
Y	O
EOR	O
zpg	O
,	O
XLSR	O
zpg	O
,	O
XCLIEOR	O
abs	O
,	O
Y	O
EOR	O
abs	O
,	O
XLSR	O
abs	O
,	O
X	O
6RTSADC	O
(	O
ind	O
,	O
X	O
)	O
ADC	O
zpgROR	O
zpgPLAADC	O
#ROR	O
AJMP	O
(	O
ind	O
)	O
ADC	O
absROR	O
abs	O
7BVS	O
relADC	O
(	O
ind	O
)	O
,	O
Y	O
ADC	O
zpg	O
,	O
XROR	O
zpg	O
,	O
XSEIADC	O
abs	O
,	O
Y	O
ADC	O
abs	O
,	O
XROR	O
abs	O
,	O
X	O
8	O
STA	O
(	O
ind	O
,	O
X	O
)	O
STY	O
zpgSTA	O
zpgSTX	O
zpgDEY	O
TXASTY	O
absSTA	O
absSTX	O
abs	O
9BCC	O
relSTA	O
(	O
ind	O
)	O
,	O
Y	O
STY	O
zpg	O
,	O
XSTA	O
zpg	O
,	O
XSTX	O
zpg	O
,	O
YTYASTA	O
abs	O
,	O
YTXS	O
STA	O
abs	O
,	O
X	O
ALDY	O
#LDA	O
(	O
ind	O
,	O
X	O
)	O
LDX	O
#LDY	O
zpgLDA	O
zpgLDX	O
zpgTAYLDA	O
#TAXLDY	O
absLDA	O
absLDX	O
abs	O
BBCS	O
relLDA	O
(	O
ind	O
)	O
,	O
Y	O
LDY	O
zpg	O
,	O
XLDA	O
zpg	O
,	O
XLDX	O
zpg	O
,	O
YCLVLDA	O
abs	O
,	O
YTSXLDY	O
abs	O
,	O
XLDA	O
abs	O
,	O
XLDX	O
abs	O
,	O
Y	O
CCPY	O
#CMP	O
(	O
ind	O
,	O
X	O
)	O
CPY	O
zpgCMP	O
zpgDEC	O
zpgINYCMP	O
#DEXCPY	O
absCMP	O
absDEC	O
abs	O
DBNE	O
relCMP	O
(	O
ind	O
)	O
,	O
Y	O
CMP	O
zpg	O
,	O
XDEC	O
zpg	O
,	O
X	O
CLDCMP	O
abs	O
,	O
Y	O
CMP	O
abs	O
,	O
XDEC	O
abs	O
,	O
X	O
ECPX	O
#SBC	O
(	O
ind	O
,	O
X	O
)	O
CPX	O
zpgSBC	O
zpgINC	O
zpgINXSBC	O
#NOPCPX	O
absSBC	O
absINC	O
abs	O
FBEQ	O
relSBC	O
(	O
ind	O
)	O
,	O
Y	O
SBC	O
zpg	O
,	O
XINC	O
zpg	O
,	O
XSEDSBC	O
abs	O
,	O
Y	O
SBC	O
abs	O
,	O
XINC	O
abs	O
,	O
XBlank	O
opcodes	B-Language
(	O
e.g.	O
,	O
F2	O
)	O
and	O
all	O
opcodes	B-Language
whose	O
low	O
nibbles	O
are	O
3	O
,	O
7	O
,	O
B	O
and	O
F	O
are	O
undefined	O
in	O
the	O
6502	O
instruction	O
set	O
.	O
</s>
<s>
The	O
processor	O
's	O
non-maskable	B-General_Concept
interrupt	I-General_Concept
(	O
NMI	O
)	O
input	O
is	O
edge	O
sensitive	O
,	O
which	O
means	O
that	O
the	O
interrupt	B-Application
is	O
triggered	O
by	O
the	O
falling	O
edge	O
of	O
the	O
signal	O
rather	O
than	O
its	O
level	O
.	O
</s>
<s>
The	O
implication	O
of	O
this	O
feature	O
is	O
that	O
a	O
wired-OR	O
interrupt	B-Application
circuit	O
is	O
not	O
readily	O
supported	O
.	O
</s>
<s>
However	O
,	O
this	O
also	O
prevents	O
nested	O
NMI	O
interrupts	B-Application
from	O
occurring	O
until	O
the	O
hardware	O
makes	O
the	O
NMI	O
input	O
inactive	O
again	O
,	O
often	O
under	O
control	O
of	O
the	O
NMI	O
interrupt	B-General_Concept
handler	I-General_Concept
.	O
</s>
<s>
The	O
simultaneous	O
assertion	O
of	O
the	O
NMI	O
and	O
IRQ	B-General_Concept
(	O
maskable	O
)	O
hardware	O
interrupt	B-Application
lines	I-Application
causes	O
IRQ	B-General_Concept
to	O
be	O
ignored	O
.	O
</s>
<s>
However	O
,	O
if	O
the	O
IRQ	B-General_Concept
line	O
remains	O
asserted	O
after	O
the	O
servicing	O
of	O
the	O
NMI	O
,	O
the	O
processor	O
will	O
immediately	O
respond	O
to	O
IRQ	B-General_Concept
,	O
as	O
IRQ	B-General_Concept
is	O
level	O
sensitive	O
.	O
</s>
<s>
Thus	O
a	O
sort	O
of	O
built-in	O
interrupt	B-Application
priority	O
was	O
established	O
in	O
the	O
6502	O
design	O
.	O
</s>
<s>
The	O
B	O
flag	O
is	O
set	O
by	O
the	O
6502	O
's	O
periodically	O
sampling	O
its	O
NMI	O
edge	O
detector	O
's	O
output	O
and	O
its	O
IRQ	B-General_Concept
input	O
.	O
</s>
<s>
The	O
IRQ	B-General_Concept
signal	O
being	O
driven	O
low	O
is	O
only	O
recognized	O
though	O
if	O
IRQs	B-General_Concept
are	O
allowed	O
by	O
the	O
I	B-Device
flag	O
.	O
</s>
<s>
If	O
in	O
this	O
way	O
a	O
NMI	O
request	O
or	O
(	O
maskable	O
)	O
IRQ	B-General_Concept
is	O
detected	O
the	O
B	O
flag	O
is	O
set	O
to	O
zero	O
and	O
causes	O
the	O
processor	O
to	O
execute	O
the	O
BRK	B-General_Concept
instruction	O
next	O
instead	O
of	O
executing	O
the	O
next	B-General_Concept
instruction	I-General_Concept
based	O
on	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
The	O
BRK	B-General_Concept
instruction	O
then	O
pushes	O
the	O
processor	O
status	O
onto	O
the	O
stack	B-Application
,	O
with	O
the	O
B	O
flag	O
bit	O
set	O
to	O
zero	O
.	O
</s>
<s>
At	O
the	O
end	O
of	O
its	O
execution	O
the	O
BRK	B-General_Concept
instruction	O
resets	O
the	O
B	O
flag	O
's	O
value	O
to	O
one	O
.	O
</s>
<s>
If	O
an	O
instruction	O
other	O
than	O
the	O
BRK	B-General_Concept
instruction	O
pushes	O
the	O
B	O
flag	O
onto	O
the	O
stack	B-Application
as	O
part	O
of	O
the	O
processor	O
status	O
the	O
B	O
flag	O
always	O
has	O
the	O
value	O
one	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
high-speed	O
polling	B-General_Concept
device	O
driver	O
can	O
poll	O
the	O
hardware	O
once	O
in	O
only	O
three	O
cycles	O
using	O
a	O
Branch-on-oVerflow-Clear	O
(	O
BVC	O
)	O
instruction	O
that	O
branches	O
to	O
itself	O
until	O
overflow	O
is	O
set	O
by	O
an	O
SO	O
falling	O
transition	O
.	O
</s>
<s>
The	O
Commodore	B-Device
1541	I-Device
and	O
other	O
Commodore	O
floppy	B-Device
disk	I-Device
drives	I-Device
use	O
this	O
technique	O
to	O
detect	O
when	O
the	O
serializer	B-Application
is	O
ready	O
to	O
transfer	O
another	O
byte	O
of	O
disk	B-Device
data	O
.	O
</s>
<s>
There	O
are	O
many	O
variants	O
of	O
the	O
original	O
NMOS	B-Algorithm
6502	O
.	O
</s>
<s>
+	O
Caption	O
Company	O
Model	O
Description	O
6502	O
A	O
1	O
MHz	O
chip	O
used	O
in	O
KIM-1	B-Device
and	O
other	O
single	B-Device
board	I-Device
computers	I-Device
in	O
the	O
mid-1970s	O
.	O
</s>
<s>
6502A	O
A	O
1.5	O
MHz	O
chip	O
used	O
in	O
Asteroids	B-Application
Deluxe	I-Application
and	O
at	O
2	O
MHz	O
,	O
in	O
the	O
BBC	B-Device
Micro	I-Device
6502B	O
Version	O
of	O
the	O
6502	O
capable	O
of	O
running	O
at	O
a	O
maximum	O
speed	O
of	O
3	O
MHz	O
instead	O
of	O
2	O
MHz	O
.	O
</s>
<s>
The	O
B	O
was	O
used	O
in	O
the	O
Apple	B-Device
III	I-Device
and	O
,	O
clocked	O
at	O
1.79	O
MHz	O
,	O
early	O
Atari	B-Device
8-bit	I-Device
computers	I-Device
.	O
</s>
<s>
Not	O
to	O
be	O
confused	O
with	O
SALLY	B-Device
,	O
a	O
custom	O
6502	O
designed	O
for	O
Atari	O
(	O
and	O
sometimes	O
referred	O
to	O
by	O
them	O
as	O
"	O
6502C	O
"	O
)	O
nor	O
with	O
the	O
similarly-named	O
65C02	B-General_Concept
.	O
</s>
<s>
SALLY	B-Device
,	O
C014806	O
,	O
"	O
6502C	O
"	O
Custom	O
6502	O
variant	O
designed	O
for	O
Atari	O
,	O
used	O
in	O
later	O
Atari	B-Device
8-bit	I-Device
computers	I-Device
and	O
Atari	B-General_Concept
5200	I-General_Concept
and	O
Atari	B-General_Concept
7800	I-General_Concept
consoles	O
.	O
</s>
<s>
Has	O
a	O
HALT	O
signal	O
on	O
pin	O
35	O
and	O
the	O
R/W	O
signal	O
on	O
pin	O
36	O
(	O
these	O
pins	O
are	O
not	O
connected	O
(	O
N/C	O
)	O
on	O
a	O
standard	O
6502	O
)	O
.	O
</s>
<s>
This	O
was	O
used	O
to	O
allow	O
the	O
video	O
circuitry	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	B-General_Concept
)	O
.	O
</s>
<s>
MOS6503	O
Reduced	O
memory	O
addressing	O
capability	O
(	O
4	O
KB	O
)	O
and	O
no	O
RDY	O
input	O
,	O
in	O
a	O
28-pin	O
DIP	B-Algorithm
package	O
(	O
with	O
the	O
phase	O
1	O
(	O
OUT	O
)	O
,	O
SYNC	O
,	O
redundant	O
Vss	O
,	O
and	O
SO	O
pins	O
of	O
the	O
6502	O
also	O
omitted	O
)	O
.1982	O
MOS	B-Architecture
Technology	I-Architecture
Data	O
Catalog	O
(	O
PDF	O
obtained	O
from	O
bitsavers.org	O
)	O
MOS6504	O
Reduced	O
memory	O
addressing	O
capability	O
(	O
8	O
KB	O
)	O
,	O
no	O
NMI	O
,	O
and	O
no	O
RDY	O
input	O
,	O
in	O
a	O
28-pin	O
DIP	B-Algorithm
package	O
(	O
with	O
the	O
phase	O
1	O
(	O
OUT	O
)	O
,	O
SYNC	O
,	O
redundant	O
Vss	O
,	O
and	O
SO	O
pins	O
of	O
the	O
6502	O
also	O
omitted	O
)	O
.	O
</s>
<s>
MOS6505	O
Reduced	O
memory	O
addressing	O
capability	O
(	O
4	O
KB	O
)	O
and	O
no	O
NMI	O
,	O
in	O
a	O
28-pin	O
DIP	B-Algorithm
package	O
(	O
with	O
the	O
phase	O
1	O
(	O
OUT	O
)	O
,	O
SYNC	O
,	O
redundant	O
Vss	O
,	O
and	O
SO	O
pins	O
of	O
the	O
6502	O
also	O
omitted	O
)	O
.	O
</s>
<s>
MOS6506	O
Reduced	O
memory	O
addressing	O
capability	O
(	O
4	O
KB	O
)	O
,	O
no	O
NMI	O
,	O
and	O
no	O
RDY	O
input	O
,	O
but	O
all	O
3	O
clock	O
pins	O
of	O
the	O
6502	O
(	O
i.e.	O
</s>
<s>
a	O
2-phase	O
output	O
clock	O
)	O
,	O
in	O
a	O
28-pin	O
DIP	B-Algorithm
package	O
(	O
with	O
the	O
SYNC	O
,	O
redundant	O
Vss	O
,	O
and	O
SO	O
pins	O
of	O
the	O
6502	O
also	O
omitted	O
)	O
.	O
</s>
<s>
MOS6507	O
Reduced	O
memory	O
addressing	O
capability	O
(	O
8	O
KB	O
)	O
and	O
no	O
interrupts	B-Application
,	O
in	O
a	O
28-pin	O
DIP	B-Algorithm
package	O
(	O
with	O
the	O
phase	O
1	O
(	O
OUT	O
)	O
,	O
SYNC	O
,	O
redundant	O
Vss	O
,	O
and	O
SO	O
pins	O
of	O
the	O
6502	O
also	O
omitted	O
)	O
.	O
</s>
<s>
This	O
chip	O
was	O
used	O
in	O
the	O
Atari	B-General_Concept
2600	I-General_Concept
video	O
game	O
system	O
.	O
</s>
<s>
MOS6509	O
Can	O
address	O
up	O
to	O
1	O
MB	O
of	O
RAM	O
as	O
16	O
banks	O
of	O
64	O
KB	O
and	O
was	O
used	O
in	O
the	O
Commodore	B-Device
CBM-II	I-Device
series	O
.	O
</s>
<s>
The	O
8500	O
is	O
effectively	O
an	O
HMOS	O
version	O
of	O
the	O
6510	B-General_Concept
,	O
and	O
replaced	O
it	O
in	O
later	O
versions	O
of	O
the	O
C64	O
.	O
</s>
<s>
MOS6512651365146515	O
The	O
MOS	B-Architecture
Technology	I-Architecture
6512	O
,	O
6513	O
,	O
6514	O
,	O
and	O
6515	O
each	O
rely	O
on	O
an	O
external	O
clock	O
,	O
instead	O
of	O
using	O
an	O
internal	O
clock	O
generator	O
like	O
the	O
650x	O
(	O
e.g.	O
</s>
<s>
This	O
was	O
used	O
to	O
advantage	O
in	O
some	O
designs	O
where	O
the	O
clocks	O
could	O
be	O
run	O
asymmetrically	O
,	O
increasing	O
overall	O
CPU	B-General_Concept
performance	O
.	O
</s>
<s>
The	O
6512	O
was	O
used	O
in	O
the	O
BBC	B-Device
Micro	I-Device
B+64	I-Device
.	O
</s>
<s>
MOS65916592	O
System	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
designs	O
that	O
utilize	O
a	O
complete	O
Atari	B-General_Concept
2600	I-General_Concept
in	O
a	O
48-pin	O
DIP	B-Algorithm
package	O
.	O
</s>
<s>
WDC65C02	O
CMOS	B-Device
version	O
of	O
the	O
NMOS	B-Algorithm
6502	O
that	O
was	O
designed	O
by	O
Bill	O
Mensch	O
of	O
the	O
Western	O
Design	O
Center	O
(	O
WDC	O
)	O
,	O
featuring	O
reduced	O
power	O
consumption	O
,	O
support	O
for	O
much	O
higher	O
clock	O
speeds	O
,	O
new	O
instructions	O
,	O
new	O
addressing	B-Language
modes	I-Language
for	O
some	O
existing	O
instructions	O
,	O
and	O
correction	O
of	O
NMOS	B-Algorithm
errata	O
,	O
such	O
as	O
the	O
JMP	O
( $xxFF	O
)	O
bug	O
.	O
</s>
<s>
WDC65SC02	O
WDC	B-General_Concept
65C02	I-General_Concept
variant	O
without	O
individual	O
bit	B-Algorithm
manipulation	I-Algorithm
operations	O
(	O
RMB	O
,	O
SMB	O
,	O
BBR	O
and	O
BBS	O
)	O
.	O
</s>
<s>
This	O
core	O
,	O
running	O
at	O
4	O
MHz	O
,	O
was	O
used	O
in	O
the	O
Atari	B-General_Concept
Lynx	I-General_Concept
's	O
main	O
system	O
IC.CSG	O
,	O
MOS65CE02	O
CMOS	B-Device
variant	O
developed	O
by	O
the	O
Commodore	O
Semiconductor	O
Group	O
(	O
CSG	O
)	O
,	O
formerly	O
MOS	B-Architecture
Technology	I-Architecture
.	O
</s>
<s>
RockwellR6511QR6500/11	O
,	O
R6500/12	O
,	O
R6500/15	O
"	O
One-Chip	O
Microcomputers	B-Architecture
"	O
Enhanced	O
versions	O
of	O
the	O
6502-based	O
processor	O
,	O
also	O
including	O
individual	O
bit	B-Algorithm
manipulation	I-Algorithm
operations	O
(	O
RMB	O
,	O
SMB	O
,	O
BBR	O
and	O
BBS	O
)	O
,	O
on-chip	O
192	O
byte	O
zero-page	O
RAM	O
,	O
UART	O
,	O
etc	O
.	O
</s>
<s>
Rockwell	O
R65F11R65F12	O
The	O
Rockwell	O
R65F11	O
(	O
introduced	O
in	O
1983	O
)	O
and	O
the	O
later	O
R65F12	O
are	O
enhanced	O
versions	O
of	O
the	O
6502-based	O
processor	O
,	O
also	O
including	O
individual	O
bit	B-Algorithm
manipulation	I-Algorithm
operations	O
(	O
RMB	O
,	O
SMB	O
,	O
BBR	O
and	O
BBS	O
)	O
,	O
on-chip	O
zero-page	O
RAM	O
,	O
on-chip	O
Forth	B-Application
kernel	O
ROM	O
,	O
a	O
UART	O
,	O
etc.Randy	O
M	O
.	O
Dumse	O
.	O
</s>
<s>
"	O
The	O
R65F11	O
and	O
F68K	O
Single-Chip	O
Forth	B-Application
Computers	O
"	O
.	O
</s>
<s>
"	O
Embedded	B-Architecture
systems	I-Architecture
:	O
1990	O
Rochester	O
Forth	B-Application
Conference	O
:	O
June	O
12	O
–	O
16th	O
,	O
1990	O
University	O
of	O
Rochester	O
"	O
.	O
</s>
<s>
"	O
RSC-Forth	O
User	O
's	O
Manual	O
"	O
.	O
</s>
<s>
GTEG65SC102	O
Software	O
compatible	O
with	O
the	O
65C02	B-General_Concept
,	O
but	O
has	O
a	O
slightly	O
different	O
pinout	O
and	O
oscillator	O
circuit	O
.	O
</s>
<s>
The	O
BBC	B-Device
Master	I-Device
Turbo	O
included	O
the	O
4	O
MHz	O
version	O
of	O
this	O
CPU	B-General_Concept
on	O
a	O
coprocessor	O
card	O
,	O
which	O
could	O
also	O
be	O
bought	O
separately	O
and	O
added	O
to	O
the	O
Master	O
128	O
.	O
</s>
<s>
Rockwell	O
R65C00R65C21R65C29	O
The	O
R65C00	O
,	O
R65C21	O
,	O
and	O
R65C29	O
have	O
two	O
enhanced	O
CMOS	B-Device
6502s	O
in	O
a	O
single	O
chip	O
,	O
and	O
the	O
R65C00	O
and	O
R65C21	O
additionally	O
contained	O
2	O
KB	O
of	O
mask-programmable	O
ROM	O
.	O
</s>
<s>
CM630	O
A	O
1	O
MHz	O
Eastern	O
Bloc	O
clone	O
of	O
the	O
6502	O
and	O
was	O
used	O
in	O
the	O
Pravetz	B-Device
8A	O
and	O
8C	O
,	O
Bulgarian	O
clones	O
of	O
the	O
Apple	B-Device
//	I-Device
series	O
.	O
</s>
<s>
MOS75018501	O
6510	B-General_Concept
(	O
an	O
enhanced	O
6502	O
)	O
variants	O
,	O
introduced	O
in	O
1984.http://plus4world.powweb.com/hardware/MOS_75018501	O
Hardware	O
–	O
MOS	O
7501/8501	O
They	O
extended	O
the	O
number	O
of	O
I/O	O
port	O
pins	O
from	O
6	O
to	O
7	O
,	O
but	O
omitted	O
pins	O
for	O
non-maskable	B-General_Concept
interrupt	I-General_Concept
and	O
clock	O
output.https://ist.uwaterloo.ca/	O
~	O
schepers/MJK/7501.html	O
CPU	B-General_Concept
7501	O
/	O
8501	O
Used	O
in	O
Commodore	O
's	O
C-16	B-Operating_System
,	O
C-116	B-Operating_System
and	O
Plus/4	B-Operating_System
computers	O
.	O
</s>
<s>
MOS8500	O
Introduced	O
in	O
1985	O
as	O
an	O
HMOS	O
version	O
of	O
the	O
6510	B-General_Concept
(	O
which	O
is	O
in	O
turn	O
based	O
on	O
the	O
6502	O
)	O
.	O
</s>
<s>
Other	O
than	O
the	O
process	O
modification	O
,	O
the	O
8500	O
is	O
virtually	O
identical	O
to	O
the	O
NMOS	B-Algorithm
version	O
of	O
the	O
6510	B-General_Concept
.	O
</s>
<s>
It	O
replaced	O
the	O
6510	B-General_Concept
in	O
later	O
versions	O
of	O
the	O
Commodore	O
64	O
.	O
</s>
<s>
MOS8502	O
Designed	O
by	O
MOS	B-Architecture
Technology	I-Architecture
and	O
used	O
in	O
the	O
Commodore	B-Device
128	I-Device
.	O
</s>
<s>
Based	O
on	O
the	O
MOS	B-General_Concept
6510	I-General_Concept
used	O
in	O
the	O
Commodore	O
64	O
,	O
the	O
8502	B-General_Concept
was	O
able	O
run	O
at	O
double	O
clock	O
rate	O
of	O
the	O
6510.Service	O
Manual	O
C-128/C128D	O
Computer	O
,	O
Commodore	O
Business	O
Machines	O
,	O
PN-314001-08	O
,	O
November	O
1987	O
The	O
8502	B-General_Concept
family	O
also	O
includes	O
the	O
MOS	O
7501	O
,	O
8500	O
and	O
8501	O
.	O
</s>
<s>
Hudson	O
SoftHuC6280	O
Japanese	O
video	O
game	O
company	O
Hudson	O
Soft	O
's	O
improved	O
version	O
of	O
the	O
WDC	B-General_Concept
65C02	I-General_Concept
.	O
</s>
<s>
Manufactured	O
for	O
them	O
by	O
Seiko	O
Epson	O
and	O
NEC	O
for	O
the	O
SuperGrafx	B-General_Concept
.	O
</s>
<s>
The	O
most	O
notable	O
product	O
using	O
the	O
HuC6280	B-General_Concept
is	O
NEC	O
's	O
TurboGrafx-16	O
video	B-Device
game	I-Device
console	I-Device
.	O
</s>
<s>
The	O
Western	O
Design	O
Center	O
designed	O
and	O
currently	O
produces	O
the	O
WDC	B-General_Concept
65C816S	I-General_Concept
processor	O
,	O
a	O
16-bit	B-Device
,	O
static-core	O
successor	O
to	O
the	O
65C02	B-General_Concept
.	O
</s>
<s>
The	O
W65C816S	B-General_Concept
is	O
a	O
newer	O
variant	O
of	O
the	O
65C816	B-General_Concept
,	O
which	O
is	O
the	O
core	O
of	O
the	O
Apple	B-Device
IIGS	I-Device
computer	O
and	O
is	O
the	O
basis	O
of	O
the	O
Ricoh	B-General_Concept
5A22	I-General_Concept
processor	O
that	O
powers	O
the	O
Super	B-Application
Nintendo	I-Application
Entertainment	I-Application
System	I-Application
.	O
</s>
<s>
The	O
W65C816S	B-General_Concept
incorporates	O
minor	O
improvements	O
over	O
the	O
65C816	B-General_Concept
that	O
make	O
the	O
newer	O
chip	O
not	O
an	O
exact	O
hardware-compatible	O
replacement	O
for	O
the	O
earlier	O
one	O
.	O
</s>
<s>
Among	O
these	O
improvements	O
was	O
conversion	O
to	O
a	O
static	O
core	O
,	O
which	O
makes	O
it	O
possible	O
to	O
stop	O
the	O
clock	O
in	O
either	O
phase	O
without	O
the	O
registers	B-General_Concept
losing	O
data	O
.	O
</s>
<s>
Available	O
through	O
electronics	O
distributors	O
,	O
as	O
of	O
March	O
2020	O
,	O
the	O
W65C816S	B-General_Concept
is	O
officially	O
rated	O
for	O
14MHz	O
operation	O
.	O
</s>
<s>
The	O
Western	O
Design	O
Center	O
also	O
designed	O
and	O
produced	O
the	O
65C802	B-General_Concept
,	O
which	O
was	O
a	O
65C816	B-General_Concept
core	O
with	O
a	O
64-kilobyte	O
address	O
space	O
in	O
a	O
65(C )	O
02	O
pin-compatible	O
package	O
.	O
</s>
<s>
The	O
65C802	B-General_Concept
could	O
be	O
retrofitted	O
to	O
a	O
6502	O
board	O
and	O
would	O
function	O
as	O
a	O
65C02	B-General_Concept
on	O
power-up	O
,	O
operating	O
in	O
"	O
emulation	O
mode.	O
"	O
</s>
<s>
As	O
with	O
the	O
65C816	B-General_Concept
,	O
a	O
two-instruction	O
sequence	O
would	O
switch	O
the	O
65C802	B-General_Concept
to	O
"	O
native	O
mode	O
"	O
operation	O
,	O
exposing	O
its	O
16-bit	B-Device
accumulator	B-General_Concept
and	O
index	B-General_Concept
registers	I-General_Concept
,	O
and	O
other	O
65C816	B-General_Concept
features	O
.	O
</s>
<s>
The	O
65C802	B-General_Concept
was	O
not	O
widely	O
used	O
and	O
production	O
ended	O
.	O
</s>
<s>
The	O
following	O
6502	O
assembly	B-Language
language	I-Language
source	O
code	O
is	O
for	O
a	O
subroutine	O
named	O
TOLOWER	O
,	O
which	O
copies	O
a	O
null-terminated	B-Data_Structure
character	O
string	O
from	O
one	O
location	O
to	O
another	O
,	O
converting	O
upper-case	O
letter	O
characters	O
to	O
lower-case	O
letters	O
.	O
</s>
<s>
;	O
Convert	O
a	O
null-terminated	B-Data_Structure
character	O
string	O
to	O
all	O
lower	O
case	O
.	O
</s>
<s>
CMP	O
#'Z'+1	O
;	O
if	O
greater	O
than	O
UC	O
alphabet	O
...	O
</s>
<s>
The	O
6502	O
had	O
several	O
bugs	B-Error_Name
and	O
quirks	O
,	O
which	O
had	O
to	O
be	O
accounted	O
for	O
when	O
programming	O
it	O
:	O
</s>
<s>
The	O
earliest	O
revisions	O
of	O
the	O
6502	O
,	O
such	O
as	O
those	O
shipped	O
with	O
some	O
KIM-1	B-Device
computers	O
,	O
did	O
not	O
have	O
a	O
ROR	B-Algorithm
(	O
rotate	B-Algorithm
right	I-Algorithm
memory	O
or	O
accumulator	B-General_Concept
)	O
instruction	O
.	O
</s>
<s>
The	O
operation	O
of	O
ROR	B-Algorithm
in	O
these	O
chips	O
is	O
effectively	O
an	O
ASL	O
(	O
arithmetic	O
shift	O
left	O
)	O
instruction	O
that	O
does	O
not	O
affect	O
the	O
carry	B-Algorithm
bit	I-Algorithm
in	O
the	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
MOS	O
left	O
the	O
instruction	O
out	O
of	O
chip	O
documentation	O
entirely	O
,	O
promising	O
that	O
ROR	B-Algorithm
would	O
appear	O
on	O
6502	O
chips	O
starting	O
in	O
1976	O
.	O
</s>
<s>
The	O
NMOS	B-Algorithm
6502	O
family	O
has	O
a	O
variety	O
of	O
undocumented	B-Language
instructions	I-Language
,	O
which	O
vary	O
from	O
one	O
chip	O
manufacturer	O
to	O
another	O
.	O
</s>
<s>
The	O
6502	O
instruction	O
decoding	O
is	O
implemented	O
in	O
a	O
hardwired	O
logic	O
array	O
(	O
similar	O
to	O
a	O
programmable	O
logic	O
array	O
)	O
that	O
is	O
only	O
defined	O
for	O
151	O
of	O
the	O
256	O
available	O
opcodes	B-Language
.	O
</s>
<s>
Eastern	O
House	O
Software	O
developed	O
the	O
"	O
Trap65	O
"	O
,	O
a	O
device	O
that	O
plugged	O
between	O
the	O
processor	O
and	O
its	O
socket	O
to	O
convert	O
(	O
trap	B-Application
)	O
unimplemented	O
opcodes	B-Language
into	O
BRK	B-General_Concept
(	O
software	O
interrupt	B-Application
)	O
instructions	O
.	O
</s>
<s>
Some	O
programmers	O
utilized	O
this	O
feature	O
to	O
extend	O
the	O
6502	O
instruction	O
set	O
by	O
providing	O
functionality	O
for	O
the	O
unimplemented	O
opcodes	B-Language
with	O
specially	O
written	O
software	O
intercepted	O
at	O
the	O
BRK	B-General_Concept
instruction	O
's	O
0xFFFE	O
vector	O
.	O
</s>
<s>
All	O
of	O
the	O
undefined	B-Language
opcodes	I-Language
have	O
been	O
replaced	O
with	O
NOP	B-Language
instructions	O
in	O
the	O
65C02	B-General_Concept
,	O
an	O
enhanced	O
CMOS	B-Device
version	O
of	O
the	O
6502	O
,	O
although	O
with	O
varying	O
byte	O
sizes	O
and	O
execution	O
times	O
.	O
</s>
<s>
In	O
the	O
65C802/65C816	B-General_Concept
,	O
all	O
256	O
opcodes	B-Language
perform	O
defined	O
operations	O
.	O
</s>
<s>
The	O
6502	O
's	O
memory	B-Language
indirect	I-Language
jump	I-Language
instruction	O
,	O
JMP	O
(	O
<address>	O
)	O
,	O
is	O
partly	O
broken	O
.	O
</s>
<s>
If	O
<address>	O
is	O
hex	O
xxFF	O
(	O
i.e.	O
,	O
any	O
word	O
ending	O
in	O
FF	O
)	O
,	O
the	O
processor	O
will	O
not	O
jump	O
to	O
the	O
address	O
stored	O
in	O
xxFF	O
and	O
xxFF+1	O
as	O
expected	O
,	O
but	O
rather	O
the	O
one	O
defined	O
by	O
xxFF	O
and	O
xx00	O
(	O
for	O
example	O
,	O
JMP	O
( $10FF	O
)	O
would	O
jump	O
to	O
the	O
address	O
stored	O
in	O
10FF	O
and	O
1000	O
,	O
instead	O
of	O
the	O
one	O
stored	O
in	O
10FF	O
and	O
1100	O
)	O
.	O
</s>
<s>
This	O
defect	O
continued	O
through	O
the	O
entire	O
NMOS	B-Algorithm
line	O
,	O
but	O
was	O
corrected	O
in	O
the	O
CMOS	B-Device
derivatives	O
.	O
</s>
<s>
The	O
NMOS	B-Algorithm
6502	O
indexed	B-Language
addressing	I-Language
across	O
page	O
boundaries	O
will	O
do	O
an	O
extra	O
read	O
of	O
an	O
invalid	O
address	O
.	O
</s>
<s>
This	O
characteristic	O
may	O
cause	O
random	O
issues	O
by	O
accessing	O
hardware	O
that	O
acts	O
on	O
a	O
read	O
,	O
such	O
as	O
clearing	O
timer	O
or	O
IRQ	B-General_Concept
flags	O
,	O
sending	O
an	O
I/O	O
handshake	O
,	O
etc	O
.	O
</s>
<s>
This	O
defect	O
continued	O
through	O
the	O
entire	O
NMOS	B-Algorithm
line	O
,	O
but	O
was	O
corrected	O
in	O
the	O
CMOS	B-Device
derivatives	O
,	O
in	O
which	O
the	O
processor	O
does	O
an	O
extra	O
read	O
of	O
the	O
last	O
instruction	B-Language
byte	I-Language
.	O
</s>
<s>
The	O
6502	O
read	B-Operating_System
–	I-Operating_System
modify	I-Operating_System
–	I-Operating_System
write	I-Operating_System
instructions	O
perform	O
one	O
read	O
and	O
two	O
write	O
cycles	O
.	O
</s>
<s>
This	O
anomaly	O
continued	O
through	O
the	O
full	O
NMOS	B-Algorithm
line	O
,	O
but	O
was	O
fixed	O
in	O
the	O
CMOS	B-Device
derivatives	O
,	O
in	O
which	O
the	O
processor	O
does	O
two	O
reads	O
and	O
one	O
write	O
cycle	O
.	O
</s>
<s>
Defensive	B-Application
programming	I-Application
practice	O
will	O
generally	O
avoid	O
this	O
problem	O
by	O
not	O
executing	O
read/modify/write	O
instructions	O
on	O
hardware	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
N	B-Algorithm
(	O
result	O
negative	O
)	O
,	O
V	B-Algorithm
(	O
sign	O
bit	O
overflow	O
)	O
and	O
Z	B-Algorithm
(	O
result	O
zero	O
)	O
status	B-General_Concept
flags	I-General_Concept
are	O
generally	O
meaningless	O
when	O
performing	O
arithmetic	O
operations	O
while	O
the	O
processor	O
is	O
in	O
BCD	O
mode	O
,	O
as	O
these	O
flags	O
reflect	O
the	O
binary	O
,	O
not	O
BCD	O
,	O
result	O
.	O
</s>
<s>
This	O
limitation	O
was	O
removed	O
in	O
the	O
CMOS	B-Device
derivatives	O
.	O
</s>
<s>
Therefore	O
,	O
this	O
feature	O
may	O
be	O
used	O
to	O
distinguish	O
a	O
CMOS	B-Device
processor	O
from	O
an	O
NMOS	B-Algorithm
version	O
.	O
</s>
<s>
If	O
the	O
6502	O
happens	O
to	O
be	O
in	O
BCD	O
mode	O
when	O
a	O
hardware	O
interrupt	B-Application
occurs	O
,	O
it	O
will	O
not	O
revert	O
to	O
binary	O
mode	O
.	O
</s>
<s>
This	O
characteristic	O
could	O
result	O
in	O
obscure	O
bugs	B-Error_Name
in	O
the	O
interrupt	B-General_Concept
service	I-General_Concept
routine	I-General_Concept
if	O
it	O
fails	O
to	O
clear	O
BCD	O
mode	O
before	O
performing	O
any	O
arithmetic	O
operations	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
Commodore	O
64	O
's	O
KERNAL	B-Operating_System
did	O
not	O
correctly	O
handle	O
this	O
processor	O
characteristic	O
,	O
requiring	O
that	O
IRQs	B-General_Concept
be	O
disabled	O
or	O
re-vectored	O
during	O
BCD	O
math	O
operations	O
.	O
</s>
<s>
This	O
issue	O
was	O
addressed	O
in	O
the	O
CMOS	B-Device
derivatives	O
also	O
.	O
</s>
<s>
The	O
6502	O
instruction	O
set	O
includes	O
BRK	B-General_Concept
(	O
opcode	B-Language
$00	O
)	O
,	O
which	O
is	O
technically	O
a	O
software	O
interrupt	B-Application
(	O
similar	O
in	O
spirit	O
to	O
the	O
SWI	O
mnemonic	O
of	O
the	O
Motorola	B-Device
6800	I-Device
and	O
ARM	B-Architecture
processors	I-Architecture
)	O
.	O
</s>
<s>
BRK	B-General_Concept
is	O
most	O
often	O
used	O
to	O
interrupt	B-Application
program	O
execution	O
and	O
start	O
a	O
machine	B-General_Concept
language	I-General_Concept
monitor	I-General_Concept
for	O
testing	O
and	O
debugging	O
during	O
software	O
development	O
.	O
</s>
<s>
BRK	B-General_Concept
could	O
also	O
be	O
used	O
to	O
route	O
program	O
execution	O
using	O
a	O
simple	O
jump	O
table	O
(	O
analogous	O
to	O
the	O
manner	O
in	O
which	O
the	O
Intel	B-General_Concept
8086	I-General_Concept
and	O
derivatives	O
handle	O
software	O
interrupts	B-Application
by	O
number	O
)	O
.	O
</s>
<s>
However	O
,	O
if	O
a	O
hardware	O
interrupt	B-Application
occurs	O
when	O
the	O
processor	O
is	O
fetching	O
a	O
BRK	B-General_Concept
instruction	O
,	O
the	O
NMOS	B-Algorithm
version	O
of	O
the	O
processor	O
will	O
fail	O
to	O
execute	O
BRK	B-General_Concept
and	O
instead	O
proceed	O
as	O
if	O
only	O
a	O
hardware	O
interrupt	B-Application
had	O
occurred	O
.	O
</s>
<s>
This	O
fault	O
was	O
corrected	O
in	O
the	O
CMOS	B-Device
implementation	O
of	O
the	O
processor	O
.	O
</s>
<s>
When	O
executing	O
JSR	O
(	O
jump	O
to	O
subroutine	O
)	O
and	O
RTS	O
(	O
return	O
from	O
subroutine	O
)	O
instructions	O
,	O
the	O
return	O
address	O
pushed	O
to	O
the	O
stack	B-Application
by	O
JSR	O
is	O
that	O
of	O
the	O
last	O
byte	O
of	O
the	O
JSR	O
operand	O
(	O
that	O
is	O
,	O
the	O
most	O
significant	O
byte	O
of	O
the	O
subroutine	O
address	O
)	O
,	O
rather	O
than	O
the	O
address	O
of	O
the	O
following	O
instruction	O
.	O
</s>
<s>
This	O
is	O
because	O
the	O
actual	O
copy	O
(	O
from	O
program	B-General_Concept
counter	I-General_Concept
to	O
stack	B-Application
and	O
then	O
conversely	O
)	O
takes	O
place	O
before	O
the	O
automatic	O
increment	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
that	O
occurs	O
at	O
the	O
end	O
of	O
every	O
instruction	O
.	O
</s>
<s>
The	O
read	O
access	O
of	O
the	O
CPU	B-General_Concept
can	O
be	O
delayed	O
by	O
setting	O
the	O
RDY	O
pin	O
to	O
low	O
temporarily	O
.	O
</s>
<s>
However	O
,	O
during	O
write	O
access	O
,	O
which	O
can	O
take	O
up	O
to	O
three	O
clock	O
cycles	O
for	O
a	O
BRK	B-General_Concept
instruction	O
,	O
the	O
CPU	B-General_Concept
will	O
stop	O
only	O
in	O
the	O
next	O
read	O
cycle	O
.	O
</s>
<s>
This	O
quirk	O
was	O
corrected	O
in	O
the	O
CMOS	B-Device
derivatives	O
and	O
also	O
in	O
the	O
6510	B-General_Concept
and	O
its	O
variants	O
.	O
</s>
