<s>
S1	B-General_Concept
Core	I-General_Concept
(	O
codename	O
Sirocco	O
)	O
is	O
an	O
open	O
source	O
hardware	O
microprocessor	B-Architecture
design	O
developed	O
by	O
Simply	O
RISC	O
.	O
</s>
<s>
Based	O
on	O
Sun	O
Microsystems	O
 '	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
,	O
the	O
S1	B-General_Concept
Core	I-General_Concept
is	O
licensed	O
under	O
the	O
GNU	B-License
General	I-License
Public	I-License
License	I-License
,	O
which	O
is	O
the	O
license	O
Sun	O
chose	O
for	O
the	O
OpenSPARC	B-Device
project	O
.	O
</s>
<s>
The	O
main	O
goal	O
of	O
the	O
project	O
is	O
to	O
keep	O
the	O
S1	B-General_Concept
Core	I-General_Concept
as	O
simple	O
as	O
possible	O
to	O
encourage	O
developers	O
.	O
</s>
<s>
S1	B-General_Concept
Core	I-General_Concept
only	O
has	O
one	O
64-bit	O
SPARC	B-Architecture
Core	O
(	O
supporting	O
one	O
to	O
four	O
independent	O
threads	O
of	O
execution	O
)	O
instead	O
of	O
eight	O
cores	O
;	O
</s>
<s>
S1	B-General_Concept
Core	I-General_Concept
adds	O
a	O
Wishbone	B-Architecture
bridge	O
,	O
a	O
reset	O
controller	O
and	O
a	O
basic	O
interrupt	B-Architecture
controller	I-Architecture
;	O
</s>
<s>
the	O
S1	B-General_Concept
Core	I-General_Concept
environment	O
can	O
be	O
run	O
using	O
only	O
free	O
tools	O
on	O
a	O
common	O
x86	O
Linux	O
machine	O
.	O
</s>
