<s>
The	O
Runway	B-Architecture
bus	I-Architecture
is	O
a	O
front-side	B-Architecture
bus	I-Architecture
developed	O
by	O
Hewlett-Packard	O
for	O
use	O
by	O
its	O
PA-RISC	B-Device
microprocessor	B-Architecture
family	O
.	O
</s>
<s>
The	O
Runway	B-Architecture
bus	I-Architecture
is	O
a	O
64-bit	O
wide	O
,	O
split	O
transaction	O
,	O
time	B-Protocol
multiplexed	I-Protocol
address	O
and	O
data	O
bus	O
running	O
at	O
120MHz	O
.	O
</s>
<s>
This	O
scheme	O
was	O
chosen	O
by	O
HP	O
as	O
they	O
determined	O
that	O
a	O
bus	O
using	O
separate	O
address	O
and	O
data	O
wires	O
would	O
have	O
only	O
delivered	O
20%	O
more	O
bandwidth	O
for	O
a	O
50%	O
increase	O
in	O
pin	O
count	O
,	O
which	O
would	O
have	O
made	O
microprocessors	B-Architecture
using	O
the	O
bus	O
more	O
expensive	O
.	O
</s>
<s>
The	O
Runway	B-Architecture
bus	I-Architecture
was	O
introduced	O
with	O
the	O
release	O
of	O
the	O
PA-7200	B-General_Concept
and	O
was	O
subsequently	O
used	O
by	O
the	O
PA-8000	B-General_Concept
,	O
PA-8200	B-General_Concept
,	O
PA-8500	B-General_Concept
,	O
PA-8600	B-General_Concept
and	O
PA-8700	B-General_Concept
microprocessors	B-Architecture
.	O
</s>
<s>
Early	O
implementations	O
of	O
the	O
bus	O
used	O
in	O
the	O
PA-7200	B-General_Concept
,	O
PA-8000	B-General_Concept
and	O
PA-8200	B-General_Concept
had	O
a	O
theoretical	O
bandwidth	O
of	O
960	O
MB/s	O
.	O
</s>
<s>
Beginning	O
with	O
the	O
PA-8500	B-General_Concept
,	O
the	O
Runway	B-Architecture
bus	I-Architecture
was	O
revised	O
to	O
transmit	O
on	O
both	O
rising	O
and	O
falling	O
edges	O
of	O
a	O
125MHz	O
clock	O
signal	O
,	O
which	O
increased	O
its	O
theoretical	O
bandwidth	O
to	O
2	O
GB/s	O
.	O
</s>
<s>
The	O
Runway	B-Architecture
bus	I-Architecture
was	O
succeeded	O
with	O
the	O
introduction	O
of	O
the	O
PA-8800	B-General_Concept
,	O
which	O
used	O
the	O
Itanium	O
2	O
bus	O
.	O
</s>
<s>
Runway+	O
/Runway	O
DDR	O
:	O
On	O
PA-8500	B-General_Concept
,	O
PA-8600	B-General_Concept
and	O
PA-8700	B-General_Concept
,	O
the	O
bus	O
operates	O
in	O
DDR	O
(	O
double	O
data	O
rate	O
)	O
mode	O
,	O
</s>
<s>
Most	O
machines	O
use	O
the	O
Runway	B-Architecture
bus	I-Architecture
to	O
connect	O
the	O
CPUs	O
directly	O
to	O
the	O
IOMMU	B-General_Concept
(	O
Astro	O
,	O
U2/Uturn	O
or	O
Java	O
)	O
and	O
memory	O
.	O
</s>
<s>
However	O
,	O
the	O
N	O
class	O
and	O
L3000	O
servers	O
use	O
an	O
interface	O
chip	O
called	O
Dew	O
to	O
bridge	O
the	O
Runway	B-Architecture
bus	I-Architecture
to	O
the	O
Merced	O
bus	O
that	O
connects	O
to	O
the	O
IOMMU	B-General_Concept
and	O
memory	O
.	O
</s>
