<s>
Runahead	B-General_Concept
is	O
a	O
technique	O
that	O
allows	O
a	O
microprocessor	B-Architecture
to	O
pre-process	O
instructions	O
during	O
cache	B-General_Concept
miss	O
cycles	O
instead	O
of	O
stalling	O
.	O
</s>
<s>
The	O
pre-processed	O
instructions	O
are	O
used	O
to	O
generate	O
instruction	B-General_Concept
and	O
data	B-General_Concept
stream	I-General_Concept
prefetches	B-General_Concept
by	O
detecting	O
cache	B-General_Concept
misses	I-General_Concept
before	O
they	O
would	O
otherwise	O
occur	O
by	O
using	O
the	O
idle	O
execution	O
resources	O
to	O
calculate	O
instruction	B-General_Concept
and	O
data	B-General_Concept
stream	I-General_Concept
fetch	O
addresses	B-General_Concept
using	O
the	O
available	O
information	O
that	O
is	O
independent	O
of	O
the	O
cache	B-General_Concept
miss	O
.	O
</s>
<s>
The	O
principal	O
hardware	O
cost	O
is	O
a	O
means	O
of	O
checkpointing	B-General_Concept
the	O
register	B-General_Concept
file	I-General_Concept
state	O
and	O
preventing	O
pre-processed	O
stores	O
from	O
modifying	O
memory	B-General_Concept
.	O
</s>
<s>
This	O
checkpointing	B-General_Concept
can	O
be	O
accomplished	O
using	O
very	O
little	O
hardware	O
since	O
all	O
results	O
computed	O
during	O
runahead	B-General_Concept
are	O
discarded	O
after	O
the	O
cache	B-General_Concept
miss	O
has	O
been	O
serviced	O
,	O
at	O
which	O
time	O
normal	O
execution	O
resumes	O
using	O
the	O
checkpointed	O
register	B-General_Concept
file	I-General_Concept
state	O
.	O
</s>
<s>
Branch	O
outcomes	O
computed	O
during	O
runahead	B-General_Concept
mode	O
can	O
be	O
saved	O
into	O
a	O
shift	B-General_Concept
register	I-General_Concept
,	O
which	O
can	O
be	O
used	O
as	O
a	O
highly	O
accurate	O
branch	B-General_Concept
predictor	I-General_Concept
when	O
normal	O
operation	O
resumes	O
.	O
</s>
<s>
Runahead	B-General_Concept
was	O
initially	O
investigated	O
in	O
the	O
context	O
of	O
an	O
in-order	O
microprocessor	B-Architecture
;	O
however	O
,	O
this	O
technique	O
has	O
been	O
extended	O
for	O
use	O
with	O
out-of-order	B-General_Concept
microprocessors	B-Architecture
.	O
</s>
<s>
When	O
a	O
runahead	B-General_Concept
processor	O
detects	O
a	O
level	O
one	O
instruction	B-General_Concept
or	O
data	B-General_Concept
cache	I-General_Concept
miss	O
it	O
records	O
the	O
instruction	B-General_Concept
address	O
of	O
the	O
faulting	O
access	O
and	O
enters	O
runahead	B-General_Concept
mode	O
.	O
</s>
<s>
A	O
demand	O
fetch	O
for	O
the	O
missing	O
instruction	B-General_Concept
or	O
data	B-General_Concept
cache	I-General_Concept
line	O
is	O
generated	O
if	O
necessary	O
.	O
</s>
<s>
The	O
processor	O
checkpoints	O
the	O
register	B-General_Concept
file	I-General_Concept
by	O
one	O
of	O
several	O
mechanisms	O
(	O
discussed	O
later	O
)	O
.	O
</s>
<s>
The	O
state	O
of	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
is	O
checkpointed	O
by	O
disabling	O
stores	O
.	O
</s>
<s>
Store	O
instructions	O
are	O
allowed	O
to	O
compute	O
addresses	B-General_Concept
and	O
check	O
for	O
a	O
hit	O
,	O
but	O
they	O
are	O
not	O
allowed	O
to	O
write	O
to	O
memory	B-General_Concept
.	O
</s>
<s>
Because	O
the	O
value	O
returned	O
from	O
a	O
cache	B-General_Concept
miss	O
cannot	O
be	O
known	O
ahead	O
of	O
time	O
,	O
it	O
is	O
possible	O
for	O
pre-processed	O
instructions	O
to	O
be	O
dependent	O
upon	O
invalid	O
data	O
.	O
</s>
<s>
These	O
are	O
denoted	O
by	O
adding	O
an	O
"	O
invalid	O
"	O
or	O
INV	O
bit	O
to	O
every	O
register	B-General_Concept
in	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
If	O
runahead	B-General_Concept
was	O
initiated	O
by	O
a	O
load	O
instruction	B-General_Concept
,	O
the	O
load	O
's	O
destination	O
register	B-General_Concept
is	O
marked	O
INV	O
.	O
</s>
<s>
The	O
processor	O
then	O
continues	O
to	O
execute	O
instructions	O
after	O
the	O
miss	O
;	O
however	O
,	O
all	O
results	O
are	O
strictly	O
temporary	O
and	O
are	O
only	O
used	O
to	O
attempt	O
to	O
generate	O
additional	O
load	O
,	O
store	O
,	O
and	O
instruction	B-General_Concept
cache	B-General_Concept
misses	I-General_Concept
,	O
which	O
are	O
turned	O
into	O
prefetches	B-General_Concept
.	O
</s>
<s>
The	O
designer	O
can	O
opt	O
to	O
allow	O
runahead	B-General_Concept
to	O
skip	O
over	O
instructions	O
that	O
are	O
not	O
present	O
in	O
the	O
instruction	B-General_Concept
cache	B-General_Concept
with	O
the	O
understanding	O
that	O
the	O
quality	O
of	O
any	O
prefetches	B-General_Concept
generated	O
will	O
be	O
reduced	O
since	O
the	O
effect	O
of	O
the	O
missing	O
instructions	O
is	O
unknown	O
.	O
</s>
<s>
Registers	O
that	O
are	O
the	O
target	O
of	O
an	O
instruction	B-General_Concept
that	O
has	O
one	O
or	O
more	O
source	O
registers	O
marked	O
INV	O
are	O
marked	O
INV	O
.	O
</s>
<s>
This	O
allows	O
the	O
processor	O
to	O
know	O
which	O
register	B-General_Concept
values	O
can	O
be	O
(	O
reasonably	O
)	O
trusted	O
during	O
runahead	B-General_Concept
mode	O
.	O
</s>
<s>
Branch	O
outcomes	O
are	O
saved	O
in	O
a	O
shift	B-General_Concept
register	I-General_Concept
for	O
later	O
use	O
as	O
highly	O
accurate	O
predictions	O
during	O
normal	O
operation	O
.	O
</s>
<s>
Note	O
that	O
it	O
is	O
not	O
possible	O
to	O
perfectly	O
track	O
INV	O
register	B-General_Concept
values	O
during	O
runahead	B-General_Concept
mode	O
.	O
</s>
<s>
This	O
is	O
not	O
required	O
since	O
runahead	B-General_Concept
is	O
only	O
used	O
to	O
optimize	O
performance	O
and	O
all	O
results	O
computed	O
during	O
runahead	B-General_Concept
mode	O
are	O
discarded	O
.	O
</s>
<s>
In	O
fact	O
,	O
it	O
is	O
impossible	O
to	O
perfectly	O
track	O
invalid	O
register	B-General_Concept
values	O
if	O
runahead	B-General_Concept
was	O
initiated	O
by	O
an	O
instruction	B-General_Concept
cache	B-General_Concept
miss	O
,	O
an	O
instruction	B-General_Concept
cache	B-General_Concept
miss	O
occurred	O
during	O
runahead	B-General_Concept
,	O
a	O
load	O
is	O
dependent	O
upon	O
a	O
store	O
with	O
an	O
INV	O
address	O
(	O
assumes	O
that	O
hardware	O
is	O
present	O
to	O
allow	O
store	O
to	O
load	O
forwarding	O
during	O
runahead	B-General_Concept
)	O
,	O
or	O
if	O
a	O
branch	O
outcome	O
during	O
runahead	B-General_Concept
is	O
dependent	O
upon	O
an	O
INV	O
register	B-General_Concept
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
state	O
is	O
restored	O
from	O
the	O
checkpoint	O
and	O
the	O
processor	O
is	O
redirected	O
to	O
the	O
original	O
faulting	O
fetch	O
address	O
when	O
the	O
fetch	O
that	O
initiated	O
runahead	B-General_Concept
mode	O
has	O
been	O
serviced	O
.	O
</s>
<s>
The	O
most	O
obvious	O
method	O
of	O
checkpointing	B-General_Concept
the	O
register	B-General_Concept
file	I-General_Concept
(	O
RF	O
)	O
is	O
to	O
simply	O
perform	O
a	O
flash	B-Device
copy	I-Device
to	O
a	O
shadow	O
register	B-General_Concept
file	I-General_Concept
,	O
or	O
backup	O
register	B-General_Concept
file	I-General_Concept
(	O
BRF	O
)	O
when	O
the	O
processor	O
enters	O
runahead	B-General_Concept
mode	O
,	O
then	O
perform	O
a	O
flash	B-Device
copy	I-Device
from	O
the	O
BRF	O
to	O
the	O
RF	O
when	O
normal	O
operation	O
resumes	O
.	O
</s>
<s>
One	O
way	O
to	O
eliminate	O
the	O
flash	B-Device
copy	I-Device
operations	O
is	O
to	O
write	O
to	O
both	O
the	O
BRF	O
and	O
RF	O
during	O
normal	O
operation	O
,	O
read	O
from	O
only	O
the	O
RF	O
during	O
normal	O
operation	O
,	O
and	O
read/write	O
only	O
the	O
BRF	O
during	O
runahead	B-General_Concept
mode	O
.	O
</s>
<s>
An	O
even	O
more	O
aggressive	O
approach	O
is	O
to	O
eliminate	O
the	O
BRF	O
and	O
rely	O
upon	O
the	O
forwarding	O
paths	O
to	O
provide	O
modified	O
values	O
during	O
runahead	B-General_Concept
mode	O
.	O
</s>
<s>
Checkpointing	B-General_Concept
is	O
accomplished	O
by	O
disabling	O
register	B-General_Concept
file	I-General_Concept
writes	O
.	O
</s>
<s>
Modified	O
values	O
during	O
runahead	B-General_Concept
mode	O
can	O
only	O
be	O
provided	O
by	O
the	O
forwarding	O
paths	O
.	O
</s>
