<s>
Row	B-General_Concept
hammer	I-General_Concept
(	O
also	O
written	O
as	O
rowhammer	B-General_Concept
)	O
is	O
a	O
security	O
exploit	O
that	O
takes	O
advantage	O
of	O
an	O
unintended	O
and	O
undesirable	O
side	O
effect	O
in	O
dynamic	O
random-access	O
memory	O
(	O
DRAM	O
)	O
in	O
which	O
memory	B-Algorithm
cells	I-Algorithm
interact	O
electrically	O
between	O
themselves	O
by	O
leaking	O
their	O
charges	O
,	O
possibly	O
changing	O
the	O
contents	O
of	O
nearby	O
memory	O
rows	O
that	O
were	O
not	O
addressed	B-General_Concept
in	O
the	O
original	O
memory	O
access	O
.	O
</s>
<s>
This	O
circumvention	O
of	O
the	O
isolation	O
between	O
DRAM	O
memory	B-Algorithm
cells	I-Algorithm
results	O
from	O
the	O
high	O
cell	O
density	O
in	O
modern	O
DRAM	O
,	O
and	O
can	O
be	O
triggered	O
by	O
specially	O
crafted	O
memory	O
access	O
patterns	O
that	O
rapidly	O
activate	O
the	O
same	O
memory	O
rows	O
numerous	O
times	O
.	O
</s>
<s>
The	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
has	O
been	O
used	O
in	O
some	O
privilege	O
escalation	O
computer	O
security	O
exploits	O
,	O
and	O
network-based	O
attacks	O
are	O
also	O
theoretically	O
possible	O
.	O
</s>
<s>
Different	O
hardware-based	O
techniques	O
exist	O
to	O
prevent	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
from	O
occurring	O
,	O
including	O
required	O
support	O
in	O
some	O
processors	B-General_Concept
and	O
types	O
of	O
DRAM	O
memory	B-General_Concept
modules	I-General_Concept
.	O
</s>
<s>
In	O
dynamic	O
RAM	O
(	O
DRAM	O
)	O
,	O
each	O
bit	O
of	O
stored	O
data	O
occupies	O
a	O
separate	O
memory	B-Algorithm
cell	I-Algorithm
that	O
is	O
electrically	O
implemented	O
with	O
one	O
capacitor	O
and	O
one	O
transistor	B-Application
.	O
</s>
<s>
The	O
charge	O
state	O
of	O
a	O
capacitor	O
(	O
charged	O
or	O
discharged	O
)	O
is	O
what	O
determines	O
whether	O
a	O
DRAM	B-Algorithm
cell	I-Algorithm
stores	O
"	O
1	O
"	O
or	O
"	O
0	O
"	O
as	O
a	O
binary	O
value	O
.	O
</s>
<s>
Huge	O
numbers	O
of	O
DRAM	O
memory	B-Algorithm
cells	I-Algorithm
are	O
packed	O
into	O
integrated	O
circuits	O
,	O
together	O
with	O
some	O
additional	O
logic	O
that	O
organizes	O
the	O
cells	O
for	O
the	O
purposes	O
of	O
reading	O
,	O
writing	O
,	O
and	O
refreshing	B-General_Concept
the	O
data	O
.	O
</s>
<s>
Memory	B-Algorithm
cells	I-Algorithm
(	O
blue	O
squares	O
in	O
both	O
illustrations	O
)	O
are	O
further	O
organized	O
into	O
matrices	B-Architecture
and	O
addressed	B-General_Concept
through	O
rows	O
and	O
columns	O
.	O
</s>
<s>
A	O
memory	B-General_Concept
address	I-General_Concept
applied	O
to	O
a	O
matrix	O
is	O
broken	O
into	O
the	O
row	O
address	O
and	O
column	O
address	O
,	O
which	O
are	O
processed	O
by	O
the	O
row	O
and	O
column	O
address	B-Device
decoders	I-Device
(	O
in	O
both	O
illustrations	O
,	O
vertical	O
and	O
horizontal	O
green	O
rectangles	O
,	O
respectively	O
)	O
.	O
</s>
<s>
Consequently	O
,	O
read	O
operations	O
are	O
of	O
a	O
destructive	O
nature	O
because	O
the	O
design	O
of	O
DRAM	O
requires	O
memory	B-Algorithm
cells	I-Algorithm
to	O
be	O
rewritten	O
after	O
their	O
values	O
have	O
been	O
read	O
by	O
transferring	O
the	O
cell	O
charges	O
into	O
the	O
row	O
buffer	O
.	O
</s>
<s>
As	O
a	O
result	O
of	O
storing	O
data	O
bits	O
using	O
capacitors	O
that	O
have	O
a	O
natural	O
discharge	O
rate	O
,	O
DRAM	O
memory	B-Algorithm
cells	I-Algorithm
lose	O
their	O
state	O
over	O
time	O
and	O
require	O
periodic	O
rewriting	B-General_Concept
of	O
all	O
memory	B-Algorithm
cells	I-Algorithm
,	O
which	O
is	O
a	O
process	O
known	O
as	O
refreshing	B-General_Concept
.	O
</s>
<s>
Increased	O
densities	O
of	O
DRAM	O
integrated	O
circuits	O
have	O
led	O
to	O
physically	O
smaller	O
memory	B-Algorithm
cells	I-Algorithm
containing	O
less	O
charge	O
,	O
resulting	O
in	O
lower	O
operational	O
noise	O
margins	O
,	O
increased	O
rates	O
of	O
electromagnetic	O
interactions	O
between	O
memory	B-Algorithm
cells	I-Algorithm
,	O
and	O
greater	O
possibility	O
of	O
data	O
loss	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
disturbance	O
errors	O
have	O
been	O
observed	O
,	O
being	O
caused	O
by	O
cells	O
interfering	O
with	O
each	O
other	O
's	O
operation	O
and	O
manifesting	O
as	O
random	O
changes	O
in	O
the	O
values	O
of	O
bits	O
stored	O
in	O
affected	O
memory	B-Algorithm
cells	I-Algorithm
.	O
</s>
<s>
However	O
,	O
researchers	O
proved	O
in	O
a	O
2014	O
analysis	O
that	O
commercially	O
available	O
DDR3	O
SDRAM	O
chips	O
manufactured	O
in	O
2012	O
and	O
2013	O
are	O
susceptible	O
to	O
disturbance	O
errors	O
,	O
while	O
using	O
the	O
term	O
row	B-General_Concept
hammer	I-General_Concept
to	O
name	O
the	O
associated	O
side	O
effect	O
that	O
led	O
to	O
observed	O
bit	O
flips	O
.	O
</s>
<s>
The	O
opportunity	O
for	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
to	O
occur	O
in	O
DDR3	O
memory	O
is	O
primarily	O
attributed	O
to	O
DDR3	O
's	O
high	O
density	O
of	O
memory	B-Algorithm
cells	I-Algorithm
and	O
the	O
results	O
of	O
associated	O
interactions	O
between	O
the	O
cells	O
,	O
while	O
rapid	O
DRAM	O
row	O
activations	O
have	O
been	O
determined	O
as	O
the	O
primary	O
cause	O
.	O
</s>
<s>
Frequent	O
row	O
activations	O
cause	O
voltage	O
fluctuations	O
on	O
the	O
associated	O
row	O
selection	O
lines	O
,	O
which	O
have	O
been	O
observed	O
to	O
induce	O
higher-than-natural	O
discharge	O
rates	O
in	O
capacitors	O
belonging	O
to	O
nearby	O
(	O
adjacent	O
,	O
in	O
most	O
cases	O
)	O
memory	O
rows	O
,	O
which	O
are	O
called	O
victim	O
rows	O
;	O
if	O
the	O
affected	O
memory	B-Algorithm
cells	I-Algorithm
are	O
not	O
refreshed	B-General_Concept
before	O
they	O
lose	O
too	O
much	O
charge	O
,	O
disturbance	O
errors	O
occur	O
.	O
</s>
<s>
Tests	O
show	O
that	O
a	O
disturbance	O
error	O
may	O
be	O
observed	O
after	O
performing	O
around	O
139,000	O
subsequent	O
memory	O
row	O
accesses	O
(	O
with	O
cache	B-General_Concept
flushes	I-General_Concept
)	O
,	O
and	O
that	O
up	O
to	O
one	O
memory	B-Algorithm
cell	I-Algorithm
in	O
every	O
1,700	O
cells	O
may	O
be	O
susceptible	O
.	O
</s>
<s>
As	O
DRAM	O
vendors	O
have	O
deployed	O
mitigations	O
,	O
patterns	O
had	O
to	O
become	O
more	O
sophisticated	O
to	O
bypass	O
Rowhammer	B-General_Concept
mitigations	O
.	O
</s>
<s>
More	O
recent	O
Rowhammer	B-General_Concept
patterns	O
include	O
non-uniform	O
,	O
frequency-based	O
patterns	O
.	O
</s>
<s>
Based	O
on	O
this	O
idea	O
,	O
academics	O
built	O
a	O
Rowhammer	B-General_Concept
fuzzer	O
named	O
Blacksmith	O
that	O
can	O
bypass	O
existing	O
mitigations	O
on	O
all	O
DDR4	O
devices	O
.	O
</s>
<s>
Different	O
methods	O
exist	O
for	O
more	O
or	O
less	O
successful	O
detection	O
,	O
prevention	O
,	O
correction	O
or	O
mitigation	O
of	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
.	O
</s>
<s>
Tests	O
show	O
that	O
simple	O
error	B-General_Concept
correction	I-General_Concept
code	I-General_Concept
,	O
providing	O
single-error	O
correction	O
and	O
double-error	O
detection	O
(	O
SECDED	O
)	O
capabilities	O
,	O
are	O
not	O
able	O
to	O
correct	O
or	O
detect	O
all	O
observed	O
disturbance	O
errors	O
because	O
some	O
of	O
them	O
include	O
more	O
than	O
two	O
flipped	O
bits	O
per	O
memory	O
word	O
.	O
</s>
<s>
Furthermore	O
,	O
research	O
shows	O
that	O
precisely	O
targeted	O
three-bit	O
row	B-General_Concept
hammer	I-General_Concept
flips	O
prevents	O
ECC	B-General_Concept
memory	I-General_Concept
from	O
noticing	O
the	O
modifications	O
.	O
</s>
<s>
A	O
less	O
effective	O
solution	O
is	O
to	O
introduce	O
more	O
frequent	O
memory	O
refreshing	B-General_Concept
,	O
with	O
the	O
refresh	O
intervals	O
shorter	O
than	O
the	O
usual	O
64ms	O
,	O
but	O
this	O
technique	O
results	O
in	O
higher	O
power	O
consumption	O
and	O
increased	O
processing	O
overhead	O
;	O
some	O
vendors	O
provide	O
firmware	B-Application
updates	O
that	O
implement	O
this	O
type	O
of	O
mitigation	O
.	O
</s>
<s>
Since	O
the	O
release	O
of	O
Ivy	B-Device
Bridge	I-Device
microarchitecture	B-General_Concept
,	O
Intel	B-Device
Xeon	I-Device
processors	B-General_Concept
support	O
the	O
so-called	O
pseudo	O
target	O
row	O
refresh	O
(	O
pTRR	O
)	O
that	O
can	O
be	O
used	O
in	O
combination	O
with	O
pTRR-compliant	O
DDR3	O
dual	B-General_Concept
in-line	I-General_Concept
memory	I-General_Concept
modules	I-General_Concept
(	O
DIMMs	B-General_Concept
)	O
to	O
mitigate	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
by	O
automatically	O
refreshing	B-General_Concept
possible	O
victim	O
rows	O
,	O
with	O
no	O
negative	O
impact	O
on	O
performance	O
or	O
power	O
consumption	O
.	O
</s>
<s>
When	O
used	O
with	O
DIMMs	B-General_Concept
that	O
are	O
not	O
pTRR-compliant	O
,	O
these	O
Xeon	B-Device
processors	B-General_Concept
by	O
default	O
fall	O
back	O
on	O
performing	O
DRAM	B-General_Concept
refreshes	I-General_Concept
at	O
twice	O
the	O
usual	O
frequency	O
,	O
which	O
results	O
in	O
slightly	O
higher	O
memory	O
access	O
latency	O
and	O
may	O
reduce	O
the	O
memory	O
bandwidth	O
by	O
up	O
to	O
2	O
–	O
4%	O
.	O
</s>
<s>
The	O
LPDDR4	O
mobile	O
memory	O
standard	O
published	O
by	O
JEDEC	O
includes	O
optional	O
hardware	O
support	O
for	O
the	O
so-called	O
target	O
row	O
refresh	O
(	O
TRR	O
)	O
that	O
prevents	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
without	O
negatively	O
impacting	O
performance	O
or	O
power	O
consumption	O
.	O
</s>
<s>
Research	O
showed	O
that	O
TRR	O
mitigations	O
deployed	O
on	O
DDR4	O
UDIMMs	O
and	O
LPDDR4X	O
chips	O
from	O
devices	O
produced	O
between	O
2019	O
and	O
2020	O
are	O
not	O
effective	O
in	O
protecting	O
against	O
Rowhammer	B-General_Concept
.	O
</s>
<s>
Due	O
to	O
their	O
necessity	O
of	O
huge	O
numbers	O
of	O
rapidly	O
performed	O
DRAM	O
row	O
activations	O
,	O
row	B-General_Concept
hammer	I-General_Concept
exploits	O
issue	O
large	O
numbers	O
of	O
uncached	O
memory	O
accesses	O
that	O
cause	O
cache	O
misses	O
,	O
which	O
can	O
be	O
detected	O
by	O
monitoring	O
the	O
rate	O
of	O
cache	O
misses	O
for	O
unusual	O
peaks	O
using	O
hardware	B-General_Concept
performance	I-General_Concept
counters	I-General_Concept
.	O
</s>
<s>
Version	O
5.0	O
of	O
the	O
MemTest86	B-Application
memory	O
diagnostic	O
software	O
,	O
released	O
on	O
December	O
3	O
,	O
2013	O
,	O
added	O
a	O
row	B-General_Concept
hammer	I-General_Concept
test	O
that	O
checks	O
whether	O
computer	O
RAM	O
is	O
susceptible	O
to	O
disturbance	O
errors	O
,	O
but	O
it	O
only	O
works	O
if	O
the	O
computer	O
boots	O
UEFI	B-Architecture
;	O
without	O
UEFI	B-Architecture
,	O
it	O
boots	O
an	O
older	O
version	O
with	O
no	O
hammer	O
test	O
.	O
</s>
<s>
Memory	B-General_Concept
protection	I-General_Concept
,	O
as	O
a	O
way	O
of	O
preventing	O
processes	B-Operating_System
from	O
accessing	O
memory	O
that	O
has	O
not	O
been	O
assigned	B-General_Concept
to	O
each	O
of	O
them	O
,	O
is	O
one	O
of	O
the	O
concepts	O
behind	O
most	O
modern	O
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
By	O
using	O
memory	B-General_Concept
protection	I-General_Concept
in	O
combination	O
with	O
other	O
security-related	O
mechanisms	O
such	O
as	O
protection	B-Operating_System
rings	I-Operating_System
,	O
it	O
is	O
possible	O
to	O
achieve	O
privilege	O
separation	O
between	O
processes	B-Operating_System
,	O
in	O
which	O
programs	B-Application
and	O
computer	O
systems	O
in	O
general	O
are	O
divided	O
into	O
parts	O
limited	O
to	O
the	O
specific	O
privileges	O
they	O
require	O
to	O
perform	O
a	O
particular	O
task	O
.	O
</s>
<s>
Disturbance	O
errors	O
(	O
explained	O
in	O
the	O
section	O
above	O
)	O
effectively	O
defeat	O
various	O
layers	O
of	O
memory	B-General_Concept
protection	I-General_Concept
by	O
"	O
short	O
circuiting	O
"	O
them	O
at	O
a	O
very	O
low	O
hardware	O
level	O
,	O
practically	O
creating	O
a	O
unique	O
attack	O
vector	O
type	O
that	O
allows	O
processes	B-Operating_System
to	O
alter	O
the	O
contents	O
of	O
arbitrary	O
parts	O
of	O
the	O
main	O
memory	O
by	O
directly	O
manipulating	O
the	O
underlying	O
memory	O
hardware	O
.	O
</s>
<s>
In	O
comparison	O
,	O
"	O
conventional	O
"	O
attack	O
vectors	O
such	O
as	O
buffer	B-General_Concept
overflows	I-General_Concept
aim	O
at	O
circumventing	O
the	O
protection	O
mechanisms	O
at	O
the	O
software	O
level	O
,	O
by	O
exploiting	O
various	O
programming	O
mistakes	O
to	O
achieve	O
alterations	O
of	O
otherwise	O
inaccessible	O
main	O
memory	O
contents	O
.	O
</s>
<s>
The	O
initial	O
research	O
into	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
,	O
published	O
in	O
June	O
2014	O
,	O
described	O
the	O
nature	O
of	O
disturbance	O
errors	O
and	O
indicated	O
the	O
potential	O
for	O
constructing	O
an	O
attack	O
,	O
but	O
did	O
not	O
provide	O
any	O
examples	O
of	O
a	O
working	O
security	O
exploit	O
.	O
</s>
<s>
A	O
subsequent	O
October	O
2014	O
research	O
paper	O
did	O
not	O
imply	O
the	O
existence	O
of	O
any	O
security-related	O
issues	O
arising	O
from	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
.	O
</s>
<s>
On	O
March	O
9	O
,	O
2015	O
,	O
Google	B-Application
's	I-Application
Project	B-Application
Zero	I-Application
revealed	O
two	O
working	O
privilege	O
escalation	O
exploits	O
based	O
on	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
,	O
establishing	O
its	O
exploitable	O
nature	O
on	O
the	O
x86-64	B-Device
architecture	B-General_Concept
.	O
</s>
<s>
One	O
of	O
the	O
revealed	O
exploits	O
targets	O
the	B-Application
Google	I-Application
Native	B-Application
Client	I-Application
(	O
NaCl	B-Application
)	O
mechanism	O
for	O
running	O
a	O
limited	O
subset	O
of	O
x86-64	B-Device
machine	B-Language
instructions	I-Language
within	O
a	O
sandbox	O
,	O
exploiting	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
to	O
escape	O
from	O
the	O
sandbox	O
and	O
gain	O
the	O
ability	O
to	O
issue	O
system	B-Operating_System
calls	I-Operating_System
directly	O
.	O
</s>
<s>
This	O
NaCl	B-Application
vulnerability	O
,	O
tracked	O
as	O
,	O
has	O
been	O
mitigated	O
by	O
modifying	O
the	O
NaCl	B-Application
so	O
it	O
does	O
not	O
allow	O
execution	O
of	O
the	O
clflush	O
(	O
cache	B-General_Concept
line	I-General_Concept
flush	O
)	O
machine	B-Language
instruction	I-Language
,	O
which	O
was	O
previously	O
believed	O
to	O
be	O
required	O
for	O
constructing	O
an	O
effective	O
row	B-General_Concept
hammer	I-General_Concept
attack	O
.	O
</s>
<s>
The	O
second	O
exploit	O
revealed	O
by	O
Project	B-Application
Zero	I-Application
runs	O
as	O
an	O
unprivileged	O
Linux	B-Application
process	O
on	O
the	O
x86-64	B-Device
architecture	B-General_Concept
,	O
exploiting	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
to	O
gain	O
unrestricted	O
access	O
to	O
all	O
physical	O
memory	O
installed	O
in	O
a	O
computer	O
.	O
</s>
<s>
By	O
combining	O
the	O
disturbance	O
errors	O
with	O
memory	O
spraying	O
,	O
this	O
exploit	O
is	O
capable	O
of	O
altering	O
page	O
table	O
entries	O
used	O
by	O
the	O
virtual	B-Architecture
memory	I-Architecture
system	O
for	O
mapping	O
virtual	O
addresses	O
to	O
physical	O
addresses	O
,	O
which	O
results	O
in	O
the	O
exploit	O
gaining	O
unrestricted	O
memory	O
access	O
.	O
</s>
<s>
Due	O
to	O
its	O
nature	O
and	O
the	O
inability	O
of	O
the	O
x86-64	B-Device
architecture	B-General_Concept
to	O
make	O
clflush	O
a	O
privileged	O
machine	B-Language
instruction	I-Language
,	O
this	O
exploit	O
can	O
hardly	O
be	O
mitigated	O
on	O
computers	O
that	O
do	O
not	O
use	O
hardware	O
with	O
built-in	O
row	B-General_Concept
hammer	I-General_Concept
prevention	O
mechanisms	O
.	O
</s>
<s>
While	O
testing	O
the	O
viability	O
of	O
exploits	O
,	O
Project	B-Application
Zero	I-Application
found	O
that	O
about	O
half	O
of	O
the	O
29	O
tested	O
laptops	B-Device
experienced	O
disturbance	O
errors	O
,	O
with	O
some	O
of	O
them	O
occurring	O
on	O
vulnerable	O
laptops	B-Device
in	O
less	O
than	O
five	O
minutes	O
of	O
running	O
row-hammer-inducing	O
code	O
;	O
the	O
tested	O
laptops	B-Device
were	O
manufactured	O
between	O
2010	O
and	O
2014	O
and	O
used	O
non-ECC	O
DDR3	O
memory	O
.	O
</s>
<s>
In	O
July	O
2015	O
,	O
a	O
group	O
of	O
security	O
researchers	O
published	O
a	O
paper	O
that	O
describes	O
an	O
architecture	B-General_Concept
-	O
and	O
instruction-set-independent	O
way	O
for	O
exploiting	O
the	O
row	B-General_Concept
hammer	I-General_Concept
effect	I-General_Concept
.	O
</s>
<s>
Instead	O
of	O
relying	O
on	O
the	O
clflush	O
instruction	O
to	O
perform	O
cache	B-General_Concept
flushes	I-General_Concept
,	O
this	O
approach	O
achieves	O
uncached	O
memory	O
accesses	O
by	O
causing	O
a	O
very	O
high	O
rate	O
of	O
cache	O
eviction	O
using	O
carefully	O
selected	O
memory	O
access	O
patterns	O
.	O
</s>
<s>
Although	O
the	O
cache	B-General_Concept
replacement	I-General_Concept
policies	I-General_Concept
differ	O
between	O
processors	B-General_Concept
,	O
this	O
approach	O
overcomes	O
the	O
architectural	O
differences	O
by	O
employing	O
an	O
adaptive	O
cache	O
eviction	O
strategy	O
algorithm	O
.	O
</s>
<s>
The	O
proof	O
of	O
concept	O
for	O
this	O
approach	O
is	O
provided	O
both	O
as	O
a	O
native	B-Language
code	I-Language
implementation	O
,	O
and	O
as	O
a	O
pure	O
JavaScript	B-Language
implementation	O
that	O
runs	O
on	O
Firefox39	O
.	O
</s>
<s>
The	O
JavaScript	B-Language
implementation	O
,	O
called	O
Rowhammer.js	O
,	O
uses	O
large	O
typed	O
arrays	B-Data_Structure
and	O
relies	O
on	O
their	O
internal	O
allocation	B-General_Concept
using	O
large	O
pages	O
;	O
as	O
a	O
result	O
,	O
it	O
demonstrates	O
a	O
very	O
high-level	O
exploit	O
of	O
a	O
very	O
low-level	O
vulnerability	O
.	O
</s>
<s>
In	O
October	O
2016	O
,	O
researchers	O
published	O
DRAMMER	O
,	O
an	O
Android	O
application	O
that	O
uses	O
row	B-General_Concept
hammer	I-General_Concept
,	O
together	O
with	O
other	O
methods	O
,	O
to	O
reliably	O
gain	O
root	O
access	O
on	O
several	O
popular	O
smartphones	O
.	O
</s>
<s>
The	O
vulnerability	O
was	O
acknowledged	O
as	O
and	O
a	O
mitigation	O
was	O
released	O
by	O
Google	B-Application
within	O
a	O
month	O
.	O
</s>
<s>
As	O
a	O
mitigation	O
,	O
researchers	O
proposed	O
a	O
lightweight	O
defense	O
that	O
prevents	O
attacks	O
based	O
on	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
by	O
isolating	O
DMA	O
buffers	O
with	O
guard	O
rows	O
.	O
</s>
<s>
In	O
May	O
2021	O
,	O
a	O
Google	B-Application
research	O
team	O
announced	O
a	O
new	O
exploit	O
,	O
Half-Double	O
that	O
takes	O
advantage	O
of	O
the	O
worsening	O
physics	O
of	O
some	O
of	O
the	O
newer	O
DRAM	O
chips	O
.	O
</s>
