<s>
In	O
a	O
PCI	O
Express	O
(	O
PCIe	O
)	O
system	O
,	O
a	O
root	B-Architecture
complex	I-Architecture
device	O
connects	O
the	O
CPU	B-Device
and	O
memory	O
subsystem	O
to	O
the	O
PCI	O
Express	O
switch	O
fabric	O
composed	O
of	O
one	O
or	O
more	O
PCIe	O
or	O
PCI	O
devices	O
.	O
</s>
<s>
Similar	O
to	O
a	O
host	B-Device
bridge	I-Device
in	O
a	O
PCI	O
system	O
,	O
the	O
root	B-Architecture
complex	I-Architecture
generates	O
transaction	O
requests	O
on	O
behalf	O
of	O
the	O
CPU	B-Device
,	O
which	O
is	O
interconnected	O
through	O
a	O
local	O
bus	O
.	O
</s>
<s>
Root	B-Architecture
complex	I-Architecture
functionality	O
may	O
be	O
integrated	O
in	O
the	O
chipset	O
and/or	O
the	O
CPU	B-Device
.	O
</s>
<s>
A	O
root	B-Architecture
complex	I-Architecture
may	O
contain	O
more	O
than	O
one	O
PCI	O
Express	O
port	O
and	O
multiple	O
switch	O
devices	O
can	O
be	O
connected	O
to	O
ports	O
on	O
the	O
root	B-Architecture
complex	I-Architecture
or	O
cascaded	O
.	O
</s>
<s>
The	O
PCIE	B-Architecture
Root	I-Architecture
Complex	I-Architecture
holds	O
a	O
master	O
copy	O
of	O
a	O
'	O
Type	O
1	O
Configuration	O
Table	O
 '	O
that	O
defines	O
the	O
host	O
memory	O
space	O
that	O
is	O
accessible	O
from	O
each	O
Endpoint	O
device	O
.	O
</s>
<s>
Both	O
the	O
Type	O
1	O
and	O
Type	O
0	O
configuration	O
tables	O
are	O
set	O
up	O
by	O
the	O
Host	O
Operating	O
System	O
that	O
controls	O
the	O
Root	B-Architecture
Complex	I-Architecture
by	O
a	O
process	O
known	O
as	O
enumeration	O
and	O
which	O
acts	O
to	O
build	O
a	O
device	O
memory	O
map	O
for	O
the	O
system	O
by	O
querying	O
each	O
bridge	O
,	O
and	O
endpoint	O
device	O
connected	O
on	O
the	O
bus	O
network	O
.	O
</s>
<s>
Similarly	O
,	O
a	O
PCIE	O
Bridge	O
acts	O
a	O
tiered	O
root	B-Architecture
complex	I-Architecture
with	O
a	O
"	O
Type	O
0	O
Configuration	O
Table	O
"	O
.	O
</s>
