<s>
Rigel	B-Device
was	O
a	O
microprocessor	B-Architecture
chip	B-Device
set	I-Device
developed	O
and	O
fabricated	O
by	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
that	O
implemented	O
the	O
VAX	B-Device
instruction	O
set	O
architecture	O
(	O
ISA	O
)	O
.	O
</s>
<s>
It	O
was	O
introduced	O
on	O
11	O
July	O
1989	O
with	O
the	O
introduction	O
of	O
the	O
VAX	B-Device
6000	O
Model	O
400	O
,	O
the	O
first	O
system	O
to	O
feature	O
the	O
chip	B-Device
set	I-Device
.	O
</s>
<s>
Rigel	B-Device
was	O
also	O
used	O
in	O
the	O
VAX	B-Device
4000	I-Device
Model	O
300	O
and	O
VAXstation	B-Device
3100	O
Model	O
76	O
.	O
</s>
<s>
Production	O
Rigel	B-Device
CPUs	O
were	O
rated	O
at	O
35	O
to	O
43MHz	O
.	O
</s>
<s>
The	O
Rigel	B-Device
chipset	B-Device
consisted	O
of	O
several	O
devices	O
:	O
</s>
<s>
In	O
addition	O
,	O
two	O
further	O
devices	O
implemented	O
the	O
VAX	B-Device
vector	B-Operating_System
processor	I-Operating_System
option	O
;	O
these	O
comprised	O
the	O
DC555	O
Vector	O
Register	O
set	O
chip	O
(	O
VERSE	O
)	O
and	O
the	O
DC556	O
Vector	O
Data	O
Path	O
chip	O
(	O
FAVOR	O
)	O
.	O
</s>
<s>
Support	O
chips	O
for	O
Rigel-based	O
systems	O
included	O
the	O
RSSC	O
(	O
Rigel	B-Device
System	O
Support	O
Chip	O
)	O
and	O
Ghidra	O
,	O
the	O
VAX	B-Device
4000	I-Device
system	O
interface	O
chip	O
.	O
</s>
<s>
The	O
Rigel	B-Device
architecture	O
was	O
based	O
on	O
the	O
VAX	B-Device
8800	O
processor	O
.	O
</s>
<s>
The	O
Rigel	B-Device
chip	B-Device
set	I-Device
supported	O
an	O
optional	O
vector	B-Operating_System
processor	I-Operating_System
and	O
the	O
REX520	O
decoded	O
any	O
vector	O
instructions	O
and	O
passed	O
on	O
to	O
the	O
vector	O
interface	O
(	O
VC	O
)	O
chip	O
by	O
the	O
REX520	O
.	O
</s>
<s>
The	O
REX520	O
has	O
a	O
2	O
KB	O
unified	O
primary	O
cache	O
,	O
configurable	O
as	O
an	O
instruction	O
cache	O
and	O
an	O
external	O
128	O
KB	O
secondary	O
cache	O
(	O
backup	O
cache	O
)	O
implemented	O
with	O
CMOS	B-Device
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
chips	O
.	O
</s>
<s>
The	O
REX520	O
has	O
an	O
external	O
cache	O
because	O
the	O
VAX	B-Device
8800	O
's	O
64	O
KB	O
primary	O
cache	O
could	O
not	O
be	O
integrated	O
on	O
the	O
same	O
die	O
.	O
</s>
<s>
The	O
chip	B-Device
set	I-Device
was	O
fabricated	O
by	O
DEC	O
in	O
their	O
second-generation	O
complementary	B-Device
metal	I-Device
–	I-Device
oxide	I-Device
–	I-Device
semiconductor	I-Device
(	O
CMOS	B-Device
)	O
process	O
,	O
CMOS-2	O
.	O
</s>
<s>
Mariah	O
was	O
a	O
revised	O
version	O
of	O
the	O
Rigel	B-Device
chip	B-Device
set	I-Device
fabricated	O
by	O
DEC	O
in	O
their	O
1µm	O
CMOS-3	O
process	O
,	O
with	O
higher	O
clock	O
frequencies	O
between	O
55	O
and	O
71MHz	O
.	O
</s>
<s>
Enhancements	O
over	O
Rigel	B-Device
included	O
a	O
4	O
kB	O
first-level	O
cache	O
and	O
32-bit	O
physical	O
memory	O
addressing	O
in	O
the	O
Mariah	O
CPU	O
,	O
and	O
write-back	O
caching	O
implemented	O
in	O
the	O
cache	O
controller	O
chip	O
.	O
</s>
<s>
Mariah	O
was	O
used	O
in	O
the	O
VAX	B-Device
6000	O
Model	O
500	O
,	O
MicroVAX	B-Device
3100	O
Model	O
80	O
and	O
VAXstation	B-Device
4000	O
Model	O
60	O
.	O
</s>
