<s>
The	O
Ricoh	B-General_Concept
5A22	I-General_Concept
is	O
an	O
8/16	O
-bit	O
microprocessor	B-Architecture
produced	O
by	O
Ricoh	O
for	O
the	O
Super	B-Application
Nintendo	I-Application
Entertainment	I-Application
System	I-Application
(	O
SNES	B-Application
)	O
video	B-Device
game	I-Device
console	I-Device
.	O
</s>
<s>
It	O
is	O
based	O
on	O
the	O
8/16	O
-bit	O
WDC	B-General_Concept
65C816	I-General_Concept
,	O
which	O
was	O
developed	O
between	O
1982	O
and	O
1984	O
for	O
the	O
Apple	B-Device
IIGS	I-Device
personal	O
computer	O
.	O
</s>
<s>
It	O
has	O
92	O
instructions	O
,	O
an	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
,	O
a	O
16-bit	B-Device
accumulator	B-General_Concept
,	O
and	O
a	O
24-bit	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
CPU	O
runs	O
between	O
1.79	O
MHz	O
and	O
3.58	O
MHz	O
,	O
and	O
uses	O
an	O
extended	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
65C816	B-General_Concept
CPU	O
core	O
,	O
the	O
5A22	O
contains	O
support	O
hardware	O
,	O
including	O
:	O
</s>
<s>
A	O
DMA	B-General_Concept
unit	O
,	O
supporting	O
two	O
primary	O
modes	O
:	O
</s>
<s>
The	O
CPU	O
as	O
a	O
whole	O
employs	O
a	O
variable-speed	O
system	B-Architecture
bus	I-Architecture
,	O
with	O
bus	O
access	O
times	O
determined	O
by	O
the	O
memory	O
location	O
accessed	O
.	O
</s>
<s>
The	O
bus	O
runs	O
at	O
3.58MHz	O
for	O
non-access	O
cycles	O
and	O
when	O
accessing	O
Bus	O
B	O
and	O
most	O
internal	O
registers	B-Architecture
,	O
and	O
either	O
2.68	O
or	O
3.58MHz	O
when	O
accessing	O
Bus	O
A	O
.	O
</s>
<s>
It	O
runs	O
at	O
1.79MHz	O
only	O
when	O
accessing	O
the	O
controller	O
port	O
serial-access	O
registers	B-Architecture
.	O
</s>
<s>
It	O
works	O
at	O
approximately	O
1.5	O
MIPS	O
,	O
and	O
has	O
a	O
theoretical	O
peak	O
performance	O
of	O
1.79	O
million	O
16-bit	B-Device
operations	O
per	O
second	O
.	O
</s>
