<s>
In	O
computing	O
,	O
the	O
reset	B-General_Concept
vector	I-General_Concept
is	O
the	O
default	O
location	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
will	O
go	O
to	O
find	O
the	O
first	O
instruction	O
it	O
will	O
execute	O
after	O
a	O
reset	B-General_Concept
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
is	O
a	O
pointer	O
or	O
address	B-General_Concept
,	O
where	O
the	O
CPU	O
should	O
always	O
begin	O
as	O
soon	O
as	O
it	O
is	O
able	O
to	O
execute	O
instructions	O
.	O
</s>
<s>
The	O
address	B-General_Concept
is	O
in	O
a	O
section	O
of	O
non-volatile	B-General_Concept
memory	I-General_Concept
initialized	O
to	O
contain	O
instructions	O
to	O
start	O
the	O
operation	O
of	O
the	O
CPU	O
,	O
as	O
the	O
first	O
step	O
in	O
the	O
process	O
of	O
booting	B-Operating_System
the	O
system	O
containing	O
the	O
CPU	O
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
the	O
8086	B-General_Concept
processor	O
is	O
at	O
physical	O
address	B-General_Concept
FFFF0h	O
(	O
16	O
bytes	O
below	O
1MB	O
)	O
.	O
</s>
<s>
The	O
value	O
of	O
the	O
CS	O
register	O
at	O
reset	B-General_Concept
is	O
FFFFh	O
and	O
the	O
value	O
of	O
the	O
IP	O
register	O
at	O
reset	B-General_Concept
is	O
0000h	O
to	O
form	O
the	O
segmented	B-Device
address	I-Device
FFFFh:0000h	O
,	O
which	O
maps	O
to	O
physical	O
address	B-General_Concept
FFFF0h	O
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
the	O
80286	B-General_Concept
processor	O
is	O
at	O
physical	O
address	B-General_Concept
FFFFF0h	O
(	O
16	O
bytes	O
below	O
16MB	O
)	O
.	O
</s>
<s>
The	O
value	O
of	O
the	O
CS	O
register	O
at	O
reset	B-General_Concept
is	O
F000h	O
with	O
the	O
descriptor	O
base	O
set	O
to	O
FF0000h	O
and	O
the	O
value	O
of	O
the	O
IP	O
register	O
at	O
reset	B-General_Concept
is	O
FFF0h	O
to	O
form	O
the	O
segmented	B-Device
address	I-Device
FF000h:FFF0h	O
,	O
which	O
maps	O
to	O
physical	O
address	B-General_Concept
FFFFF0h	O
in	O
real	B-Application
mode	I-Application
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
the	O
80386	B-General_Concept
and	O
later	O
x86	O
processors	O
is	O
physical	O
address	B-General_Concept
FFFFFFF0h	O
(	O
16	O
bytes	O
below	O
4GB	O
)	O
.	O
</s>
<s>
The	O
value	O
of	O
the	O
selector	O
portion	O
of	O
the	O
CS	O
register	O
at	O
reset	B-General_Concept
is	O
F000h	O
,	O
the	O
value	O
of	O
the	O
base	O
portion	O
of	O
the	O
CS	O
register	O
is	O
FFFF0000h	O
,	O
and	O
the	O
value	O
of	O
the	O
IP	O
register	O
at	O
reset	B-General_Concept
is	O
FFF0h	O
to	O
form	O
the	O
segmented	B-Device
address	I-Device
FFFF0000h:FFF0h	O
,	O
which	O
maps	O
to	O
the	O
physical	O
address	B-General_Concept
FFFFFFF0h	O
in	O
real	B-Application
mode	I-Application
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
PowerPC/Power	O
ISA	O
processors	O
is	O
at	O
an	O
effective	O
address	B-General_Concept
of	O
0x00000100	O
for	O
32-bit	O
processors	O
and	O
0x0000000000000100	O
for	O
64-bit	O
processors	O
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
m68k	B-Device
Architecture	I-Device
processors	O
is	O
0x0	O
for	O
Initial	O
Interrupt	O
Stack	O
Register	O
(	O
IISR	O
;	O
Not	O
really	O
a	O
reset	B-General_Concept
vector	I-General_Concept
and	O
is	O
used	O
to	O
initialize	O
the	O
stack	O
pointer	O
after	O
reset	B-General_Concept
.	O
)	O
</s>
<s>
and	O
0x4	O
for	O
initial	O
program	O
counter	O
(	O
reset	B-General_Concept
)	O
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
SPARC	B-Architecture
version	O
8	O
processors	O
is	O
at	O
an	O
address	B-General_Concept
of	O
0x00	O
;	O
the	O
reset	B-General_Concept
vector	I-General_Concept
for	O
SPARC	B-Architecture
version	O
9	O
processors	O
is	O
at	O
an	O
address	B-General_Concept
of	O
0x20	O
for	O
power-on	O
reset	B-General_Concept
,	O
0x40	O
for	O
watchdog	O
reset	B-General_Concept
,	O
0x60	O
for	O
externally	O
initiated	O
reset	B-General_Concept
,	O
and	O
0x80	O
for	O
software-initiated	O
reset	B-General_Concept
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
MIPS32	B-Device
processors	O
is	O
at	O
virtual	O
address	B-General_Concept
0xBFC00000	O
,	O
which	O
is	O
located	O
in	O
the	O
last	O
4	O
Mbytes	O
of	O
the	O
KSEG1	O
non-cacheable	O
region	O
of	O
memory	O
.	O
</s>
<s>
The	O
core	O
enters	O
kernel	O
mode	O
both	O
at	O
reset	B-General_Concept
and	O
when	O
an	O
exception	O
is	O
recognized	O
,	O
hence	O
able	O
to	O
map	O
the	O
virtual	O
address	B-General_Concept
to	O
physical	O
address	B-General_Concept
.	O
</s>
<s>
The	O
reset	B-General_Concept
vector	I-General_Concept
for	O
the	O
ARM	B-Architecture
family	I-Architecture
of	I-Architecture
processors	I-Architecture
is	O
address	B-General_Concept
0x0	O
or	O
0xFFFF0000	O
.	O
</s>
