<s>
In	O
computer	O
graphics	O
,	O
the	O
render	B-General_Concept
output	I-General_Concept
unit	I-General_Concept
(	O
ROP	O
)	O
or	O
raster	B-General_Concept
operations	I-General_Concept
pipeline	I-General_Concept
is	O
a	O
hardware	O
component	O
in	O
modern	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPUs	B-Architecture
)	O
and	O
one	O
of	O
the	O
final	O
steps	O
in	O
the	O
rendering	O
process	O
of	O
modern	O
graphics	B-Device
cards	I-Device
.	O
</s>
<s>
The	O
pixel	B-Algorithm
pipelines	O
take	O
pixel	B-Algorithm
(	O
each	O
pixel	B-Algorithm
is	O
a	O
dimensionless	O
point	O
)	O
and	O
texel	O
information	O
and	O
process	O
it	O
,	O
via	O
specific	O
matrix	O
and	O
vector	O
operations	O
,	O
into	O
a	O
final	O
pixel	B-Algorithm
or	O
depth	O
value	O
;	O
this	O
process	O
is	O
called	O
rasterization	O
.	O
</s>
<s>
Thus	O
,	O
ROPs	O
control	O
antialiasing	O
,	O
when	O
more	O
than	O
one	O
sample	O
is	O
merged	O
into	O
one	O
pixel	B-Algorithm
.	O
</s>
<s>
The	O
ROPs	O
perform	O
the	O
transactions	O
between	O
the	O
relevant	O
buffers	B-General_Concept
in	O
the	O
local	O
memory	O
–	O
this	O
includes	O
writing	O
or	O
reading	O
values	O
,	O
as	O
well	O
as	O
blending	O
them	O
together	O
.	O
</s>
<s>
Dedicated	O
antialiasing	O
hardware	O
used	O
to	O
perform	O
hardware-based	O
antialiasing	O
methods	O
like	O
MSAA	B-Algorithm
is	O
contained	O
in	O
ROPs	O
.	O
</s>
<s>
All	O
data	O
rendered	O
has	O
to	O
travel	O
through	O
the	O
ROP	O
in	O
order	O
to	O
be	O
written	O
to	O
the	O
framebuffer	B-Algorithm
,	O
from	O
there	O
it	O
can	O
be	O
transmitted	O
to	O
the	O
display	O
.	O
</s>
<s>
Therefore	O
,	O
the	O
ROP	O
is	O
where	O
the	O
GPU	B-Architecture
's	O
output	O
is	O
assembled	O
into	O
a	O
bitmapped	O
image	O
ready	O
for	O
display	O
.	O
</s>
<s>
Historically	O
the	O
number	O
of	O
ROPs	O
,	O
texture	B-General_Concept
mapping	I-General_Concept
units	I-General_Concept
(	O
TMUs	O
)	O
,	O
and	O
shader	O
processing	O
units/stream	O
processors	O
have	O
been	O
equal	O
.	O
</s>
<s>
However	O
,	O
from	O
2004	O
,	O
several	O
GPUs	B-Architecture
have	O
decoupled	O
these	O
areas	O
to	O
allow	O
optimum	O
transistor	O
allocation	O
for	O
application	O
workload	O
and	O
available	O
memory	O
performance	O
.	O
</s>
<s>
As	O
the	O
trend	O
continues	O
,	O
it	O
is	O
expected	O
that	O
graphics	B-Architecture
processors	I-Architecture
will	O
continue	O
to	O
decouple	O
the	O
various	O
parts	O
of	O
their	O
architectures	O
to	O
enhance	O
their	O
adaptability	O
to	O
future	O
graphics	O
applications	O
.	O
</s>
<s>
This	O
design	O
also	O
allows	O
chip	O
makers	O
to	O
build	O
a	O
modular	O
line-up	O
,	O
where	O
the	O
top-end	O
GPUs	B-Architecture
are	O
essentially	O
using	O
the	O
same	O
logic	O
as	O
the	O
low-end	O
products	O
.	O
</s>
