<s>
Registered	O
(	O
also	O
called	O
buffered	O
)	O
memory	B-General_Concept
modules	I-General_Concept
have	O
a	O
register	B-General_Concept
between	O
the	O
DRAM	O
modules	O
and	O
the	O
system	O
's	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
They	O
place	O
less	O
electrical	O
load	O
on	O
the	O
memory	B-General_Concept
controller	I-General_Concept
and	O
allow	O
single	O
systems	O
to	O
remain	O
stable	O
with	O
more	O
memory	B-General_Concept
modules	I-General_Concept
than	O
they	O
would	O
have	O
otherwise	O
.	O
</s>
<s>
When	O
compared	O
with	O
registered	B-General_Concept
memory	I-General_Concept
,	O
conventional	O
memory	O
is	O
usually	O
referred	O
to	O
as	O
unbuffered	B-General_Concept
memory	I-General_Concept
or	O
unregistered	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
When	O
manufactured	O
as	O
a	O
dual	B-General_Concept
in-line	I-General_Concept
memory	I-General_Concept
module	I-General_Concept
(	O
DIMM	B-General_Concept
)	O
,	O
a	O
registered	B-General_Concept
memory	I-General_Concept
module	O
is	O
called	O
an	O
RDIMM	B-General_Concept
,	O
while	O
unregistered	B-General_Concept
memory	I-General_Concept
is	O
called	O
UDIMM	B-General_Concept
or	O
simply	O
DIMM	B-General_Concept
.	O
</s>
<s>
Registered	B-General_Concept
memory	I-General_Concept
is	O
often	O
more	O
expensive	O
because	O
of	O
the	O
lower	O
number	O
of	O
units	O
sold	O
and	O
additional	O
circuitry	O
required	O
,	O
so	O
it	O
is	O
usually	O
found	O
only	O
in	O
applications	O
where	O
the	O
need	O
for	O
scalability	B-Architecture
and	O
robustness	B-Application
outweighs	O
the	O
need	O
for	O
a	O
low	O
price	O
for	O
example	O
,	O
registered	B-General_Concept
memory	I-General_Concept
is	O
usually	O
used	O
in	O
servers	O
.	O
</s>
<s>
Although	O
most	O
registered	B-General_Concept
memory	I-General_Concept
modules	O
also	O
feature	O
error-correcting	B-General_Concept
code	I-General_Concept
memory	I-General_Concept
(	O
ECC	O
)	O
,	O
it	O
is	O
also	O
possible	O
for	O
registered	B-General_Concept
memory	I-General_Concept
modules	O
to	O
not	O
be	O
error-correcting	O
or	O
vice	O
versa	O
.	O
</s>
<s>
Unregistered	O
ECC	B-General_Concept
memory	I-General_Concept
is	O
supported	O
and	O
used	O
in	O
workstation	O
or	O
entry-level	O
server	B-Application
motherboards	B-Device
that	O
do	O
not	O
support	O
very	O
large	O
amounts	O
of	O
memory	O
.	O
</s>
<s>
Normally	O
,	O
there	O
is	O
a	O
performance	O
penalty	O
for	O
using	O
registered	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Each	O
read	O
or	O
write	O
is	O
buffered	O
for	O
one	O
cycle	O
between	O
the	O
memory	O
bus	O
and	O
the	O
DRAM	O
,	O
so	O
the	O
registered	B-General_Concept
RAM	I-General_Concept
can	O
be	O
thought	O
of	O
as	O
running	O
one	O
clock	O
cycle	O
behind	O
the	O
equivalent	O
unregistered	O
DRAM	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
Intel	B-Device
Westmere	I-Device
5600	O
series	O
of	O
processors	O
access	O
memory	O
using	O
interleaving	B-General_Concept
,	O
wherein	O
memory	O
access	O
is	O
distributed	O
across	O
three	O
channels	O
.	O
</s>
<s>
If	O
two	O
memory	O
DIMMs	B-General_Concept
are	O
used	O
per	O
channel	O
,	O
this	O
"	O
results	O
in	O
a	O
reduction	O
of	O
maximum	O
memory	B-General_Concept
bandwidth	I-General_Concept
for	O
2DPC	O
(	O
DIMMs	B-General_Concept
per	O
channel	O
)	O
configurations	O
with	O
UDIMM	B-General_Concept
by	O
some	O
5%	O
in	O
comparison	O
to	O
RDIMM	B-General_Concept
"	O
.	O
</s>
<s>
This	O
occurs	O
because	O
"	O
when	O
you	O
go	O
to	O
two	O
DIMMs	B-General_Concept
per	O
memory	O
channel	O
,	O
due	O
to	O
the	O
high	O
electrical	O
loading	O
on	O
the	O
address	O
and	O
control	O
lines	O
,	O
the	O
memory	B-General_Concept
controller	I-General_Concept
uses	O
a	O
'	O
2T	O
 '	O
or	O
'	O
2N	O
 '	O
timing	O
for	O
UDIMMs	B-General_Concept
.	O
</s>
<s>
Usually	O
,	O
the	O
motherboard	B-Device
must	O
match	O
the	O
memory	O
type	O
;	O
as	O
a	O
result	O
,	O
registered	B-General_Concept
memory	I-General_Concept
will	O
not	O
work	O
in	O
a	O
motherboard	B-Device
not	O
designed	O
for	O
it	O
,	O
and	O
vice	O
versa	O
.	O
</s>
<s>
Some	O
PC	B-Device
motherboards	I-Device
accept	O
or	O
require	O
registered	B-General_Concept
memory	I-General_Concept
,	O
but	O
registered	O
and	O
unregistered	B-General_Concept
memory	I-General_Concept
modules	O
cannot	O
be	O
mixed	O
.	O
</s>
<s>
There	O
is	O
much	O
confusion	O
between	O
registered	O
and	O
ECC	B-General_Concept
memory	I-General_Concept
;	O
it	O
is	O
widely	O
thought	O
that	O
ECC	B-General_Concept
memory	I-General_Concept
(	O
which	O
may	O
or	O
may	O
not	O
be	O
registered	O
)	O
will	O
not	O
work	O
at	O
all	O
in	O
a	O
motherboard	B-Device
without	O
ECC	O
support	O
,	O
not	O
even	O
without	O
providing	O
the	O
ECC	O
functionality	O
,	O
although	O
the	O
compatibility	O
issues	O
actually	O
arise	O
when	O
trying	O
to	O
use	O
registered	B-General_Concept
memory	I-General_Concept
(	O
which	O
often	O
supports	O
ECC	O
and	O
is	O
described	O
as	O
ECC	B-General_Concept
RAM	I-General_Concept
)	O
in	O
a	O
PC	B-Device
motherboard	I-Device
that	O
does	O
not	O
support	O
it	O
.	O
</s>
<s>
Registered	O
(	O
Buffered	O
)	O
DIMM	B-General_Concept
(	O
R-DIMM	O
)	O
modules	O
insert	O
a	O
buffer	O
between	O
the	O
pins	O
of	O
the	O
command	O
and	O
address	O
buses	O
on	O
the	O
DIMM	B-General_Concept
and	O
the	O
memory	O
chips	O
.	O
</s>
<s>
A	O
high-capacity	O
DIMM	B-General_Concept
might	O
have	O
numerous	O
memory	O
chips	O
,	O
each	O
of	O
which	O
must	O
receive	O
the	O
memory	O
address	O
,	O
and	O
their	O
combined	O
input	O
capacitance	O
limits	O
the	O
speed	O
at	O
which	O
the	O
memory	O
bus	O
can	O
operate	O
.	O
</s>
<s>
By	O
redistributing	O
the	O
command	O
and	O
address	O
signals	O
within	O
the	O
R-DIMM	O
,	O
this	O
allows	O
more	O
chips	O
to	O
be	O
connected	O
to	O
the	O
memory	O
bus	O
.	O
</s>
<s>
The	O
cost	O
is	O
increased	O
memory	B-General_Concept
latency	I-General_Concept
,	O
as	O
a	O
result	O
of	O
one	O
additional	O
clock	O
cycle	O
required	O
for	O
the	O
address	O
to	O
traverse	O
the	O
additional	O
buffer	O
.	O
</s>
<s>
Early	O
registered	B-General_Concept
RAM	I-General_Concept
modules	O
were	O
physically	O
incompatible	O
with	O
unregistered	B-General_Concept
RAM	I-General_Concept
modules	O
,	O
but	O
the	O
two	O
variants	O
of	O
SDRAM	O
R-DIMMs	O
are	O
mechanically	O
interchangeable	O
,	O
and	O
some	O
motherboards	B-Device
may	O
support	O
both	O
types	O
.	O
</s>
<s>
Load	O
Reduced	O
DIMM	B-General_Concept
(	O
LR-DIMM	O
)	O
modules	O
are	O
similar	O
to	O
R-DIMMs	O
,	O
but	O
add	O
a	O
buffer	O
to	O
the	O
data	O
lines	O
as	O
well	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
LR-DIMMs	O
buffer	O
both	O
control	O
and	O
data	O
lines	O
while	O
keeping	O
the	O
parallel	O
nature	O
of	O
all	O
signals	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
LR-DIMMs	O
provide	O
large	O
overall	O
maximum	O
memory	O
capacities	O
,	O
while	O
avoiding	O
the	O
performance	O
and	O
power	O
consumption	O
problems	O
of	O
FB-DIMMs	B-General_Concept
,	O
induced	O
by	O
the	O
required	O
conversion	O
between	O
serial	O
and	O
parallel	O
signal	O
forms	O
.	O
</s>
<s>
Fully	B-General_Concept
Buffered	I-General_Concept
DIMM	I-General_Concept
(	O
FB-DIMM	B-General_Concept
)	O
modules	O
increase	O
maximum	O
memory	O
capacities	O
in	O
large	O
systems	O
even	O
more	O
,	O
using	O
a	O
more	O
complex	O
buffer	O
chip	O
to	O
translate	O
between	O
the	O
wide	O
bus	O
of	O
standard	O
SDRAM	O
chips	O
and	O
a	O
narrow	O
,	O
high-speed	O
serial	O
memory	O
bus	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
all	O
control	O
,	O
address	O
and	O
data	O
transfers	O
to	O
FB-DIMMs	B-General_Concept
are	O
performed	O
in	O
a	O
serial	O
fashion	O
,	O
while	O
the	O
additional	O
logic	O
present	O
on	O
each	O
FB-DIMM	B-General_Concept
transforms	O
serial	O
inputs	O
into	O
parallel	O
signals	O
required	O
to	O
drive	O
memory	O
chips	O
.	O
</s>
<s>
By	O
reducing	O
the	O
number	O
of	O
pins	O
required	O
per	O
memory	O
bus	O
,	O
CPUs	O
could	O
support	O
more	O
memory	O
buses	O
,	O
allowing	O
higher	O
total	O
memory	B-General_Concept
bandwidth	I-General_Concept
and	O
capacity	O
.	O
</s>
<s>
Unfortunately	O
,	O
the	O
translation	O
further	O
increased	O
memory	B-General_Concept
latency	I-General_Concept
,	O
and	O
the	O
complex	O
high-speed	O
buffer	O
chips	O
used	O
significant	O
power	O
and	O
generated	O
a	O
lot	O
of	O
heat	O
.	O
</s>
<s>
Both	O
FB-DIMMs	B-General_Concept
and	O
LR-DIMMs	O
are	O
designed	O
primarily	O
to	O
minimize	O
the	O
load	O
that	O
a	O
memory	B-General_Concept
module	I-General_Concept
presents	O
to	O
the	O
memory	O
bus	O
.	O
</s>
<s>
They	O
are	O
not	O
compatible	O
with	O
R-DIMMs	O
,	O
and	O
motherboards	B-Device
that	O
require	O
them	O
usually	O
will	O
not	O
accept	O
any	O
other	O
kind	O
of	O
memory	B-General_Concept
modules	I-General_Concept
.	O
</s>
