<s>
A	O
register	B-General_Concept
file	I-General_Concept
is	O
an	O
array	O
of	O
processor	B-General_Concept
registers	I-General_Concept
in	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
.	O
</s>
<s>
Modern	O
integrated	O
circuit-based	O
register	B-General_Concept
files	I-General_Concept
are	O
usually	O
implemented	O
by	O
way	O
of	O
fast	O
static	B-Architecture
RAMs	I-Architecture
with	O
multiple	O
ports	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
of	O
a	O
CPU	O
will	O
almost	O
always	O
define	O
a	O
set	O
of	O
registers	O
which	O
are	O
used	O
to	O
stage	O
data	O
between	O
memory	O
and	O
the	O
functional	O
units	O
on	O
the	O
chip	O
.	O
</s>
<s>
In	O
simpler	O
CPUs	O
,	O
these	O
architectural	O
registers	O
correspond	O
one-for-one	O
to	O
the	O
entries	O
in	O
a	O
physical	B-General_Concept
register	I-General_Concept
file	I-General_Concept
(	O
PRF	O
)	O
within	O
the	O
CPU	O
.	O
</s>
<s>
More	O
complicated	O
CPUs	O
use	O
register	B-Architecture
renaming	I-Architecture
,	O
so	O
that	O
the	O
mapping	O
of	O
which	O
physical	O
entry	O
stores	O
a	O
particular	O
architectural	O
register	O
changes	O
dynamically	O
during	O
execution	O
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
is	O
part	O
of	O
the	O
architecture	B-General_Concept
and	O
visible	O
to	O
the	O
programmer	O
,	O
as	O
opposed	O
to	O
the	O
concept	O
of	O
transparent	O
caches	B-General_Concept
.	O
</s>
<s>
Register	B-General_Concept
files	I-General_Concept
may	O
be	O
clubbed	O
together	O
as	O
register	B-General_Concept
banks	I-General_Concept
.	O
</s>
<s>
A	O
processor	O
may	O
have	O
more	O
than	O
one	O
register	B-General_Concept
bank	I-General_Concept
.	O
</s>
<s>
ARM	B-Architecture
processors	I-Architecture
have	O
both	O
banked	O
and	O
unbanked	O
registers	O
.	O
</s>
<s>
Notably	O
,	O
Fast	B-General_Concept
Interrupt	I-General_Concept
Request	I-General_Concept
(	O
FIQ	O
)	O
mode	O
has	O
its	O
own	O
bank	O
of	O
registers	O
for	O
R8	O
to	O
R12	O
,	O
with	O
the	O
architecture	B-General_Concept
also	O
providing	O
a	O
private	O
stack	O
pointer	O
(	O
R13	O
)	O
for	O
every	O
interrupt	O
mode	O
.	O
</s>
<s>
x86	B-Operating_System
processors	O
use	O
context	O
switching	O
and	O
fast	O
interrupt	O
for	O
switching	O
between	O
instruction	O
,	O
decoder	O
,	O
GPRs	B-General_Concept
and	O
register	B-General_Concept
files	I-General_Concept
,	O
if	O
there	O
is	O
more	O
than	O
one	O
,	O
before	O
the	O
instruction	O
is	O
issued	O
,	O
but	O
this	O
is	O
only	O
existing	O
on	O
processors	O
that	O
support	O
superscalar	O
.	O
</s>
<s>
However	O
,	O
context	O
switching	O
is	O
a	O
totally	O
different	O
mechanism	O
to	O
ARM	B-Architecture
's	O
register	B-General_Concept
bank	I-General_Concept
within	O
the	O
registers	O
.	O
</s>
<s>
The	O
MODCOMP	O
and	O
the	O
later	O
8051-compatible	O
processors	O
use	O
bits	O
in	O
the	O
program	O
status	O
word	O
to	O
select	O
the	O
currently	O
active	O
register	B-General_Concept
bank	I-General_Concept
.	O
</s>
<s>
That	O
is	O
,	O
a	O
single	O
word	O
line	O
,	O
which	O
runs	O
horizontally	O
,	O
causes	O
a	O
row	O
of	O
bit	B-General_Concept
cells	I-General_Concept
to	O
put	O
their	O
data	O
on	O
bit	O
lines	O
,	O
which	O
run	O
vertically	O
.	O
</s>
<s>
Larger	O
register	B-General_Concept
files	I-General_Concept
are	O
then	O
sometimes	O
constructed	O
by	O
tiling	O
mirrored	O
and	O
rotated	O
simple	O
arrays	O
.	O
</s>
<s>
Register	B-General_Concept
files	I-General_Concept
have	O
one	O
word	O
line	O
per	O
entry	O
per	O
port	O
,	O
one	O
bit	O
line	O
per	O
bit	O
of	O
width	O
per	O
read	O
port	O
,	O
and	O
two	O
bit	O
lines	O
per	O
bit	O
of	O
width	O
per	O
write	O
port	O
.	O
</s>
<s>
Each	O
bit	B-General_Concept
cell	I-General_Concept
also	O
has	O
a	O
Vdd	O
and	O
Vss	O
.	O
</s>
<s>
At	O
some	O
point	O
,	O
it	O
may	O
be	O
smaller	O
and/or	O
faster	O
to	O
have	O
multiple	O
redundant	O
register	B-General_Concept
files	I-General_Concept
,	O
with	O
smaller	O
numbers	O
of	O
read	O
ports	O
,	O
rather	O
than	O
a	O
single	O
register	B-General_Concept
file	I-General_Concept
with	O
all	O
the	O
read	O
ports	O
.	O
</s>
<s>
The	O
MIPS	B-Device
R8000	B-General_Concept
's	O
integer	O
unit	O
,	O
for	O
example	O
,	O
had	O
a	O
9	O
read	O
4	O
write	O
port	O
32	O
entry	O
64-bit	O
register	B-General_Concept
file	I-General_Concept
implemented	O
in	O
a	O
0.7µm	O
process	O
,	O
which	O
could	O
be	O
seen	O
when	O
looking	O
at	O
the	O
chip	O
from	O
arm	B-Architecture
's	O
length	O
.	O
</s>
<s>
Two	O
popular	O
approaches	O
to	O
dividing	O
registers	O
into	O
multiple	O
register	B-General_Concept
files	I-General_Concept
are	O
the	O
distributed	O
register	B-General_Concept
file	I-General_Concept
configuration	O
and	O
the	O
partitioned	O
register	B-General_Concept
file	I-General_Concept
configuration	O
.	O
</s>
<s>
In	O
principle	O
,	O
any	O
operation	O
that	O
could	O
be	O
done	O
with	O
a	O
64-bit-wide	O
register	B-General_Concept
file	I-General_Concept
with	O
many	O
read	O
and	O
write	O
ports	O
could	O
be	O
done	O
with	O
a	O
single	O
8-bit-wide	O
register	B-General_Concept
file	I-General_Concept
with	O
a	O
single	O
read	O
port	O
and	O
a	O
single	O
write	O
port	O
.	O
</s>
<s>
However	O
,	O
the	O
bit-level	B-Operating_System
parallelism	I-Operating_System
of	O
wide	O
register	B-General_Concept
files	I-General_Concept
with	O
many	O
ports	O
allows	O
them	O
to	O
run	O
much	O
faster	O
and	O
thus	O
,	O
they	O
can	O
do	O
operations	O
in	O
a	O
single	O
cycle	O
that	O
would	O
take	O
many	O
cycles	O
with	O
fewer	O
ports	O
or	O
a	O
narrower	O
bit	O
width	O
or	O
both	O
.	O
</s>
<s>
The	O
width	O
in	O
bits	O
of	O
the	O
register	B-General_Concept
file	I-General_Concept
is	O
usually	O
the	O
number	O
of	O
bits	O
in	O
the	O
processor	O
word	O
size	O
.	O
</s>
<s>
If	O
the	O
width	O
of	O
the	O
data	O
word	O
is	O
different	O
than	O
the	O
width	O
of	O
an	O
address	O
—	O
or	O
in	O
some	O
cases	O
,	O
such	O
as	O
the	O
68000	B-Device
,	O
even	O
when	O
they	O
are	O
the	O
same	O
width	O
—	O
the	O
address	B-General_Concept
registers	I-General_Concept
are	O
in	O
a	O
separate	O
register	B-General_Concept
file	I-General_Concept
than	O
the	O
data	O
registers	O
.	O
</s>
<s>
If	O
the	O
array	O
has	O
four	O
read	O
and	O
two	O
write	O
ports	O
,	O
for	O
example	O
,	O
it	O
has	O
6	O
word	O
lines	O
per	O
bit	B-General_Concept
cell	I-General_Concept
in	O
the	O
array	O
,	O
and	O
six	O
AND	O
gates	O
per	O
row	O
in	O
the	O
decoder	O
.	O
</s>
<s>
The	O
basic	O
scheme	O
for	O
a	O
bit	B-General_Concept
cell	I-General_Concept
:	O
</s>
<s>
So	O
:	O
read	O
ports	O
take	O
one	O
transistor	O
per	O
bit	B-General_Concept
cell	I-General_Concept
,	O
write	O
ports	O
take	O
four	O
.	O
</s>
<s>
Most	O
register	B-General_Concept
files	I-General_Concept
make	O
no	O
special	O
provisions	O
to	O
prevent	O
multiple	O
write	O
ports	O
from	O
writing	O
to	O
the	O
same	O
entry	O
simultaneously	O
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
is	O
usually	O
pitch-matched	O
to	O
the	O
datapath	B-General_Concept
that	O
it	O
serves	O
.	O
</s>
<s>
Pitch	O
matching	O
avoids	O
having	O
many	O
busses	O
passing	O
over	O
the	O
datapath	B-General_Concept
turn	O
corners	O
,	O
which	O
would	O
use	O
a	O
lot	O
of	O
area	O
.	O
</s>
<s>
But	O
since	O
every	O
unit	O
must	O
have	O
the	O
same	O
bit	O
pitch	O
,	O
every	O
unit	O
in	O
the	O
datapath	B-General_Concept
ends	O
up	O
with	O
the	O
bit	O
pitch	O
forced	O
by	O
the	O
widest	O
unit	O
,	O
which	O
can	O
waste	O
area	O
in	O
the	O
other	O
units	O
.	O
</s>
<s>
Register	B-General_Concept
files	I-General_Concept
,	O
because	O
they	O
have	O
two	O
wires	O
per	O
bit	O
per	O
write	O
port	O
,	O
and	O
because	O
all	O
the	O
bit	O
lines	O
must	O
contact	O
the	O
silicon	O
at	O
every	O
bit	B-General_Concept
cell	I-General_Concept
,	O
can	O
often	O
set	O
the	O
pitch	O
of	O
a	O
datapath	B-General_Concept
.	O
</s>
<s>
Area	O
can	O
sometimes	O
be	O
saved	O
on	O
machines	O
with	O
multiple	O
units	O
in	O
a	O
datapath	B-General_Concept
by	O
having	O
two	O
datapaths	B-General_Concept
side-by-side	O
,	O
each	O
of	O
which	O
has	O
smaller	O
bit	O
pitch	O
than	O
a	O
single	O
datapath	B-General_Concept
would	O
have	O
.	O
</s>
<s>
This	O
case	O
usually	O
forces	O
multiple	O
copies	O
of	O
a	O
register	B-General_Concept
file	I-General_Concept
,	O
one	O
for	O
each	O
datapath	B-General_Concept
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
(	O
EV6	O
)	O
,	O
for	O
instance	O
,	O
was	O
the	O
first	O
large	O
micro-architecture	O
to	O
implement	O
a	O
"	O
Shadow	O
Register	B-General_Concept
File	I-General_Concept
Architecture	B-General_Concept
"	O
.	O
</s>
<s>
It	O
had	O
two	O
copies	O
of	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
and	O
two	O
copies	O
of	O
the	O
floating	O
point	O
register	O
located	O
in	O
its	O
front	O
end	O
(	O
future	O
and	O
scaled	O
file	O
,	O
each	O
containing	O
2	O
read	O
and	O
2	O
write	O
ports	O
)	O
,	O
and	O
took	O
an	O
extra	O
cycle	O
to	O
propagate	O
data	O
between	O
the	O
two	O
during	O
a	O
context	O
switch	O
.	O
</s>
<s>
This	O
design	O
was	O
later	O
adapted	O
by	O
SPARC	B-Architecture
,	O
MIPS	B-Device
and	O
some	O
of	O
the	O
later	O
x86	B-Operating_System
implementations	O
.	O
</s>
<s>
The	O
MIPS	B-Device
uses	O
multiple	O
register	B-General_Concept
files	I-General_Concept
as	O
well	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
floating-point	O
unit	O
had	O
two	O
copies	O
of	O
the	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
,	O
each	O
with	O
four	O
write	O
and	O
four	O
read	O
ports	O
,	O
and	O
wrote	O
both	O
copies	O
at	O
the	O
same	O
time	O
with	O
a	O
context	O
switch	O
.	O
</s>
<s>
However	O
,	O
it	O
did	O
not	O
support	O
integer	O
operations	O
,	O
and	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
still	O
remained	O
as	O
such	O
.	O
</s>
<s>
Later	O
,	O
shadow	O
register	B-General_Concept
files	I-General_Concept
were	O
abandoned	O
in	O
newer	O
designs	O
in	O
favor	O
of	O
the	O
embedded	O
market	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
uses	O
a	O
"	O
Shadow	O
Register	B-General_Concept
File	I-General_Concept
Architecture	B-General_Concept
"	O
as	O
well	O
for	O
its	O
high-end	O
line	O
.	O
</s>
<s>
It	O
has	O
up	O
to	O
4	O
copies	O
of	O
integer	O
register	B-General_Concept
files	I-General_Concept
(	O
future	O
,	O
retired	O
,	O
scaled	O
,	O
and	O
scratched	O
,	O
each	O
containing	O
7	O
read	O
4	O
write	O
port	O
)	O
and	O
2	O
copies	O
of	O
the	O
floating	O
point	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
However	O
,	O
unlike	O
Alpha	B-General_Concept
and	O
x86	B-Operating_System
,	O
they	O
are	O
located	O
in	O
the	O
backend	O
as	O
a	O
retire	O
unit	O
right	O
after	O
its	O
out-of-order	O
unit	O
and	O
renaming	O
register	B-General_Concept
files	I-General_Concept
.	O
</s>
<s>
IBM	O
uses	O
the	O
same	O
mechanism	O
as	O
many	O
major	O
microprocessors	O
,	O
deeply	O
merging	O
the	O
register	B-General_Concept
file	I-General_Concept
with	O
the	O
decoder	O
,	O
but	O
its	O
register	B-General_Concept
files	I-General_Concept
work	O
independently	O
of	O
the	O
decoder	O
side	O
and	O
do	O
not	O
involve	O
context	O
switching	O
,	O
which	O
is	O
different	O
from	O
Alpha	B-General_Concept
and	O
x86	B-Operating_System
.	O
</s>
<s>
Most	O
of	O
its	O
register	B-General_Concept
files	I-General_Concept
do	O
not	O
only	O
serve	O
its	O
dedicated	O
decoder	O
,	O
but	O
up	O
to	O
the	O
thread	O
level	O
.	O
</s>
<s>
For	O
example	O
,	O
POWER8	B-Device
has	O
up	O
to	O
8	O
instruction	O
decoders	O
,	O
but	O
up	O
to	O
32	O
register	B-General_Concept
files	I-General_Concept
of	O
32	O
general	O
purpose	O
registers	O
each	O
(	O
4	O
read	O
and	O
4	O
write	O
ports	O
)	O
to	O
facilitate	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
as	O
its	O
parallel	O
instructions	O
cannot	O
be	O
used	O
across	O
any	O
other	O
register	B-General_Concept
file	I-General_Concept
due	O
to	O
the	O
lack	O
of	O
a	O
context	O
switch	O
.	O
</s>
<s>
In	O
the	O
x86	B-Operating_System
processor	O
line	O
,	O
a	O
typical	O
pre-486	O
CPU	O
did	O
not	O
have	O
an	O
individual	O
register	B-General_Concept
file	I-General_Concept
,	O
as	O
all	O
general	O
purpose	O
registers	O
worked	O
directly	O
with	O
the	O
decoder	O
,	O
and	O
the	O
x87	O
push	O
stack	O
was	O
located	O
within	O
the	O
floating-point	O
unit	O
itself	O
.	O
</s>
<s>
Starting	O
with	O
the	O
Pentium	B-General_Concept
,	O
a	O
typical	O
Pentium-compatible	O
x86	B-Operating_System
processor	O
is	O
integrated	O
with	O
one	O
copy	O
of	O
a	O
single-port	O
architectural	O
register	B-General_Concept
file	I-General_Concept
containing	O
6	O
general-purpose	O
registers	O
,	O
4	O
control	O
registers	O
,	O
8	O
debug	O
registers	O
(	O
two	O
reserved	O
)	O
,	O
1	O
stack	O
pointer	B-General_Concept
register	I-General_Concept
,	O
1	O
stack	O
base	O
register	O
,	O
1	O
instruction	O
pointer	O
,	O
1	O
flags	O
register	O
,	O
and	O
6	O
segment	O
registers	O
.	O
</s>
<s>
One	O
copy	O
of	O
8	O
x87	O
FP	O
push	O
down	O
stack	O
by	O
default	O
,	O
MMX	B-Architecture
register	O
were	O
virtually	O
simulated	O
from	O
x87	O
stack	O
and	O
require	O
x86	B-Operating_System
register	O
to	O
supplying	O
MMX	B-Architecture
instruction	O
and	O
aliases	O
to	O
exist	O
stack	O
.	O
</s>
<s>
On	O
P6	B-Device
,	O
the	O
instruction	O
independently	O
can	O
be	O
stored	O
and	O
executed	O
in	O
parallel	O
in	O
early	O
pipeline	O
stages	O
before	O
decoding	O
into	O
micro-operations	B-General_Concept
and	O
renaming	O
in	O
out-of-order	O
execution	O
.	O
</s>
<s>
Beginning	O
with	O
P6	B-Device
,	O
all	O
register	B-General_Concept
files	I-General_Concept
do	O
not	O
require	O
additional	O
cycle	O
to	O
propagate	O
the	O
data	O
,	O
register	B-General_Concept
files	I-General_Concept
like	O
architectural	O
and	O
floating	O
point	O
are	O
located	O
between	O
code	O
buffer	O
and	O
decoders	O
,	O
called	O
"	O
retire	O
buffer	O
"	O
,	O
Reorder	O
buffer	O
and	O
OoOE	O
and	O
connected	O
within	O
the	O
ring	O
bus	O
(	O
16bytes	O
)	O
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
itself	O
still	O
remains	O
one	O
x86	B-Operating_System
register	B-General_Concept
file	I-General_Concept
and	O
one	O
x87	O
stack	O
and	O
both	O
serve	O
as	O
retirement	O
storing	O
.	O
</s>
<s>
Its	O
x86	B-Operating_System
register	B-General_Concept
file	I-General_Concept
was	O
enlarged	O
to	O
dual-ported	O
to	O
increase	O
bandwidth	O
for	O
result	O
storage	O
.	O
</s>
<s>
Registers	O
like	O
debug/condition	O
code/control/unnamed/flag	O
were	O
stripped	O
from	O
the	O
main	O
register	B-General_Concept
file	I-General_Concept
and	O
placed	O
into	O
individual	O
files	O
between	O
the	O
micro-op	B-General_Concept
ROM	O
and	O
instruction	O
sequencer	O
.	O
</s>
<s>
Only	O
inaccessible	O
registers	O
like	O
the	O
segment	O
register	O
are	O
now	O
separated	O
from	O
the	O
general-purpose	O
register	B-General_Concept
file	I-General_Concept
(	O
except	O
the	O
instruction	O
pointer	O
)	O
;	O
they	O
are	O
now	O
located	O
between	O
the	O
scheduler	O
and	O
instruction	O
allocator	O
,	O
in	O
order	O
to	O
facilitate	O
register	B-Architecture
renaming	I-Architecture
and	O
out-of-order	O
execution	O
.	O
</s>
<s>
The	O
x87	O
stack	O
was	O
later	O
merged	O
with	O
the	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
after	O
a	O
128-bit	O
XMM	O
register	O
debuted	O
in	O
Pentium	B-General_Concept
III	O
,	O
but	O
the	O
XMM	O
register	B-General_Concept
file	I-General_Concept
is	O
still	O
located	O
separately	O
from	O
x86	B-Operating_System
integer	O
register	B-General_Concept
files	I-General_Concept
.	O
</s>
<s>
Later	O
P6	B-Device
implementations	O
(	O
Pentium	B-General_Concept
M	O
,	O
Yonah	O
)	O
introduced	O
a	O
"	O
Shadow	O
Register	B-General_Concept
File	I-General_Concept
Architecture	B-General_Concept
"	O
that	O
expanded	O
to	O
2	O
copies	O
of	O
dual-ported	O
integer	O
architectural	O
register	B-General_Concept
files	I-General_Concept
and	O
consist	O
with	O
context	O
switch	O
(	O
between	O
future	O
and	O
retired	O
file	O
and	O
scaled	O
file	O
using	O
the	O
same	O
trick	O
used	O
between	O
integer	O
and	O
floating-point	O
)	O
.	O
</s>
<s>
This	O
was	O
done	O
in	O
order	O
to	O
solve	O
the	O
register	O
bottleneck	O
that	O
existed	O
in	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
after	O
micro-operation	B-General_Concept
fusion	O
is	O
introduced	O
,	O
but	O
it	O
is	O
still	O
have	O
8	O
entries	O
32bit	O
architectural	O
registers	O
for	O
total	O
32	O
bytes	O
in	O
capacity	O
per	O
file	O
(	O
segment	O
register	O
and	O
instruction	O
pointer	O
remain	O
within	O
the	O
file	O
,	O
though	O
they	O
are	O
inaccessible	O
by	O
program	O
)	O
as	O
speculative	O
file	O
.	O
</s>
<s>
The	O
second	O
file	O
is	O
served	O
as	O
a	O
scaled	O
shadow	O
register	B-General_Concept
file	I-General_Concept
,	O
which	O
without	O
context	O
switch	O
the	O
scaled	O
file	O
cannot	O
store	O
some	O
instruction	O
independently	O
.	O
</s>
<s>
Some	O
instruction	O
from	O
SSE2/SSE3/SSSE3	O
require	O
this	O
feature	O
for	O
integer	O
operation	O
,	O
for	O
example	O
instruction	O
like	O
PSHUFB	O
,	O
PMADDUBSW	O
,	O
PHSUBW	O
,	O
PHSUBD	O
,	O
PHSUBSW	O
,	O
PHADDW	O
,	O
PHADDD	O
,	O
PHADDSW	O
would	O
require	O
loading	O
EAX/EBX/ECX/EDX	O
from	O
both	O
register	B-General_Concept
files	I-General_Concept
,	O
though	O
it	O
was	O
uncommon	O
for	O
an	O
x86	B-Operating_System
processor	O
to	O
make	O
use	O
of	O
another	O
register	B-General_Concept
file	I-General_Concept
with	O
the	O
same	O
instruction	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
M	O
architecture	B-General_Concept
still	O
has	O
one	O
dual-ported	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
(	O
8	O
entries	O
MM/XMM	O
)	O
shared	O
with	O
three	O
decoders	O
,	O
and	O
the	O
FP	O
register	B-General_Concept
file	I-General_Concept
does	O
not	O
have	O
a	O
shadow	O
register	B-General_Concept
file	I-General_Concept
along	O
with	O
it	O
,	O
as	O
its	O
shadow-register-file	O
architecture	B-General_Concept
did	O
not	O
including	O
floating-point	O
functions	O
.	O
</s>
<s>
In	O
processors	O
after	O
P6	B-Device
,	O
the	O
architectural	O
register	B-General_Concept
files	I-General_Concept
are	O
external	O
and	O
located	O
in	O
the	O
processor	O
's	O
backend	O
after	O
the	O
retired	O
file	O
,	O
as	O
opposed	O
to	O
the	O
internal	O
register	B-General_Concept
file	I-General_Concept
located	O
in	O
the	O
inner	O
core	O
for	O
register	O
renaming/reorder	O
buffer	O
.	O
</s>
<s>
However	O
,	O
in	O
Core	B-Device
2	I-Device
it	O
is	O
now	O
housed	O
within	O
a	O
unit	O
called	O
the	O
"	O
register	O
alias	O
table	O
"	O
(	O
RAT	O
)	O
,	O
located	O
with	O
instruction	O
allocator	O
but	O
have	O
same	O
size	O
of	O
register	O
size	O
as	O
retirement	O
.	O
</s>
<s>
Core	B-Device
2	I-Device
increased	O
the	O
inner	O
ring	O
bus	O
to	O
24bytes	O
(	O
allow	O
more	O
than	O
3	O
instructions	O
to	O
be	O
decoded	O
)	O
and	O
extended	O
its	O
register	B-General_Concept
file	I-General_Concept
from	O
dual-ported	O
(	O
one	O
read/one	O
write	O
)	O
to	O
quad-ported	O
(	O
two	O
read/two	O
write	O
)	O
,	O
register	O
still	O
remain	O
8	O
entries	O
in	O
32bit	O
and	O
32bytes	O
(	O
not	O
including	O
6	O
segment	O
register	O
and	O
one	O
instruction	O
pointer	O
as	O
they	O
are	O
unable	O
to	O
be	O
access	O
in	O
the	O
file	O
by	O
any	O
code/instruction	O
)	O
in	O
total	O
file	O
size	O
and	O
expanded	O
to	O
16	O
entries	O
in	O
x64	O
for	O
total	O
128bytes	O
size	O
per	O
file	O
.	O
</s>
<s>
From	O
Pentium	B-General_Concept
M	O
as	O
its	O
pipeline	O
port	O
and	O
decoder	O
increased	O
,	O
but	O
they	O
're	O
located	O
with	O
allocator	O
table	O
instead	O
of	O
code	O
buffer	O
.	O
</s>
<s>
Its	O
FP	O
XMM	O
register	B-General_Concept
file	I-General_Concept
are	O
also	O
increase	O
to	O
quad-ported	O
(	O
2	O
read/2	O
write	O
)	O
,	O
register	O
still	O
remain	O
8	O
entries	O
in	O
32bit	O
and	O
extended	O
to	O
16	O
entries	O
in	O
x64	O
mode	O
and	O
number	O
still	O
remain	O
1	O
as	O
its	O
shadow-register-file	O
architecture	B-General_Concept
is	O
not	O
including	O
floating	O
point/SSE	O
functions	O
.	O
</s>
<s>
In	O
later	O
x86	B-Operating_System
implementations	O
,	O
like	O
Nehalem	B-Device
and	O
later	O
processors	O
,	O
both	O
integer	O
and	O
floating	O
point	O
registers	O
are	O
now	O
incorporated	O
into	O
a	O
unified	O
octa-ported	O
(	O
six	O
read	O
and	O
two	O
write	O
)	O
general-purpose	O
register	B-General_Concept
file	I-General_Concept
(	O
8	O
+	O
8	O
in	O
32-bit	O
and	O
16	O
+	O
16	O
in	O
x64	O
per	O
file	O
)	O
,	O
while	O
the	O
register	B-General_Concept
file	I-General_Concept
extended	O
to	O
2	O
with	O
enhanced	O
"	O
Shadow	O
Register	B-General_Concept
File	I-General_Concept
Architecture	B-General_Concept
"	O
in	O
favorite	O
of	O
executing	O
hyper	B-Operating_System
threading	I-Operating_System
and	O
each	O
thread	O
uses	O
independent	O
register	B-General_Concept
files	I-General_Concept
for	O
its	O
decoder	O
.	O
</s>
<s>
Later	O
Sandy	B-Device
bridge	I-Device
and	O
onward	O
replaced	O
shadow	O
register	O
table	O
and	O
architectural	O
registers	O
with	O
much	O
large	O
and	O
yet	O
more	O
advance	O
physical	B-General_Concept
register	I-General_Concept
file	I-General_Concept
before	O
decoding	O
to	O
the	O
reorder	O
buffer	O
.	O
</s>
<s>
Randered	O
that	O
Sandy	B-Device
Bridge	I-Device
and	O
onward	O
no	O
longer	O
carry	O
an	O
architectural	O
register	O
.	O
</s>
<s>
On	O
the	O
Atom	B-Device
line	O
was	O
the	O
modern	O
simplified	O
revision	O
of	O
P5	B-General_Concept
.	O
</s>
<s>
It	O
includes	O
single	O
copies	O
of	O
register	B-General_Concept
file	I-General_Concept
share	O
with	O
thread	O
and	O
decoder	O
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
is	O
a	O
dual-port	O
design	O
,	O
8/16	O
entries	O
GPRS	B-General_Concept
,	O
8/16	O
entries	O
debug	O
register	O
and	O
8/16	O
entries	O
condition	O
code	O
are	O
integrated	O
in	O
the	O
same	O
file	O
.	O
</s>
<s>
However	O
it	O
has	O
an	O
eight-entries	O
64bit	O
shadow	O
based	O
register	O
and	O
an	O
eight-entries	O
64bit	O
unnamed	O
register	O
that	O
are	O
now	O
separated	O
from	O
main	O
GPRs	B-General_Concept
unlike	O
the	O
original	O
P5	B-General_Concept
design	O
and	O
located	O
after	O
the	O
execution	O
unit	O
,	O
and	O
the	O
file	O
of	O
these	O
registers	O
is	O
single-ported	O
and	O
not	O
expose	O
to	O
instruction	O
like	O
scaled	O
shadow	O
register	B-General_Concept
file	I-General_Concept
found	O
on	O
Core/Core2	O
(	O
shadow	O
register	B-General_Concept
file	I-General_Concept
are	O
made	O
of	O
architectural	O
registers	O
and	O
Bonnell	B-Device
did	O
not	O
due	O
to	O
not	O
have	O
"	O
Shadow	O
Register	B-General_Concept
File	I-General_Concept
Architecture	B-General_Concept
"	O
)	O
,	O
however	O
the	O
file	O
can	O
be	O
use	O
for	O
renaming	O
purpose	O
due	O
to	O
lack	O
of	O
out	O
of	O
order	O
execution	O
found	O
on	O
Bonnell	B-Device
architecture	B-General_Concept
.	O
</s>
<s>
It	O
also	O
had	O
one	O
copy	O
of	O
XMM	O
floating	O
point	O
register	B-General_Concept
file	I-General_Concept
per	O
thread	O
.	O
</s>
<s>
The	O
difference	O
from	O
Nehalem	B-Device
is	O
Bonnell	B-Device
do	O
not	O
have	O
a	O
unified	O
register	B-General_Concept
file	I-General_Concept
and	O
has	O
no	O
dedicated	O
register	B-General_Concept
file	I-General_Concept
for	O
its	O
hyper	B-Operating_System
threading	I-Operating_System
.	O
</s>
<s>
Instead	O
,	O
Bonnell	B-Device
uses	O
a	O
separate	O
rename	O
register	O
for	O
its	O
thread	O
despite	O
it	O
is	O
not	O
out	O
of	O
order	O
.	O
</s>
<s>
Similar	O
to	O
Bonnell	B-Device
,	O
Larrabee	B-Architecture
and	O
Xeon	B-General_Concept
Phi	I-General_Concept
also	O
each	O
have	O
only	O
one	O
general-purpose	O
integer	O
register	B-General_Concept
file	I-General_Concept
,	O
but	O
the	O
Larrabee	B-Architecture
has	O
up	O
to	O
16	O
XMM	O
register	B-General_Concept
files	I-General_Concept
(	O
8	O
entries	O
per	O
file	O
)	O
,	O
and	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
has	O
up	O
to	O
128	O
AVX-512	O
register	B-General_Concept
files	I-General_Concept
,	O
each	O
containing	O
32	O
512-bit	O
ZMM	O
registers	O
for	O
vector	O
instruction	O
storage	O
,	O
which	O
can	O
be	O
as	O
big	O
as	O
L2	O
cache	O
.	O
</s>
<s>
There	O
are	O
some	O
other	O
of	O
Intel	O
's	O
x86	B-Operating_System
lines	O
that	O
do	O
n't	O
have	O
a	O
register	B-General_Concept
file	I-General_Concept
in	O
their	O
internal	O
design	O
,	O
Geode	B-Device
GX	I-Device
and	O
Vortex86	B-Device
and	O
many	O
embedded	O
processors	O
that	O
are	O
n't	O
Pentium-compatible	O
or	O
reverse-engineered	O
early	O
80x86	B-Operating_System
processors	O
.	O
</s>
<s>
Therefore	O
,	O
most	O
of	O
them	O
do	O
n't	O
have	O
a	O
register	B-General_Concept
file	I-General_Concept
for	O
their	O
decoders	O
,	O
but	O
their	O
GPRs	B-General_Concept
are	O
used	O
individually	O
.	O
</s>
<s>
Pentium	B-General_Concept
4	I-General_Concept
(	O
based	O
on	O
the	O
NetBurst	B-Device
microarchitecture	O
)	O
,	O
on	O
the	O
other	O
hand	O
,	O
does	O
not	O
have	O
a	O
register	B-General_Concept
file	I-General_Concept
for	O
its	O
decoder	O
,	O
as	O
its	O
x86	B-Operating_System
GPRs	B-General_Concept
did	O
n't	O
exist	O
within	O
its	O
structure	O
,	O
due	O
to	O
the	O
introduction	O
of	O
a	O
physical	O
unified	O
renaming	O
register	B-General_Concept
file	I-General_Concept
(	O
similar	O
to	O
Sandy	B-Device
Bridge	I-Device
,	O
but	O
slightly	O
different	O
due	O
to	O
the	O
inability	O
of	O
Pentium	B-General_Concept
4	I-General_Concept
to	O
use	O
the	O
register	O
before	O
naming	O
)	O
for	O
attempting	O
to	O
replace	O
the	O
architectural	O
register	B-General_Concept
file	I-General_Concept
and	O
skip	O
the	O
x86	B-Operating_System
decoding	O
scheme	O
.	O
</s>
<s>
AMD	O
's	O
early	O
design	O
like	O
K6	B-Architecture
do	O
not	O
have	O
a	O
register	B-General_Concept
file	I-General_Concept
like	O
Intel	O
and	O
do	O
not	O
support	O
"	O
Shadow	O
Register	B-General_Concept
File	I-General_Concept
Architecture	B-General_Concept
"	O
as	O
its	O
lack	O
of	O
context	O
switch	O
and	O
bypass	O
inverter	O
that	O
are	O
necessary	O
require	O
for	O
a	O
register	B-General_Concept
file	I-General_Concept
to	O
function	O
appropriately	O
.	O
</s>
<s>
Instead	O
they	O
use	O
a	O
separate	O
GPRs	B-General_Concept
that	O
directly	O
link	O
to	O
a	O
rename	O
register	O
table	O
for	O
its	O
OoOE	O
CPU	O
with	O
a	O
dedicated	O
integer	O
decoder	O
and	O
floating	O
decoder	O
.	O
</s>
<s>
The	O
mechanism	O
is	O
similar	O
to	O
Intel	O
's	O
pre-Pentium	O
processor	O
line	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
K6	B-Architecture
processor	O
has	O
four	O
int	O
(	O
one	O
eight-entries	O
temporary	O
scratched	O
register	B-General_Concept
file	I-General_Concept
+	O
one	O
eight-entries	O
future	O
register	B-General_Concept
file	I-General_Concept
+	O
one	O
eight-entries	O
fetched	O
register	B-General_Concept
file	I-General_Concept
+	O
an	O
eight-entries	O
unnamed	O
register	B-General_Concept
file	I-General_Concept
)	O
and	O
two	O
FP	O
rename	O
register	B-General_Concept
files	I-General_Concept
(	O
two	O
eight-entries	O
x87	O
ST	O
file	O
one	O
goes	O
fadd	O
and	O
one	O
goes	O
fmov	O
)	O
that	O
directly	O
link	O
with	O
its	O
x86	B-Operating_System
EAX	O
for	O
integer	O
renaming	O
and	O
XMM0	O
register	O
for	O
floating	O
point	O
renaming	O
,	O
but	O
later	O
Athlon	B-Architecture
included	O
"	O
shadow	O
register	O
"	O
in	O
its	O
front	O
end	O
,	O
it	O
's	O
scaled	O
up	O
to	O
40	O
entries	O
unified	O
register	B-General_Concept
file	I-General_Concept
for	O
in	O
order	O
integer	O
operation	O
before	O
decoded	O
,	O
the	O
register	B-General_Concept
file	I-General_Concept
contain	O
8	O
entries	O
scratch	B-General_Concept
register	I-General_Concept
+	O
16	O
future	O
GPRs	B-General_Concept
register	B-General_Concept
file	I-General_Concept
+	O
16	O
unnamed	O
GPRs	B-General_Concept
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
In	O
later	O
AMD	O
designs	O
it	O
abandons	O
the	O
shadow	O
register	O
design	O
and	O
favored	O
to	O
K6	B-Architecture
architecture	B-General_Concept
with	O
individual	O
GPRs	B-General_Concept
direct	O
link	O
design	O
.	O
</s>
<s>
Like	O
Phenom	O
,	O
it	O
has	O
three	O
int	O
register	B-General_Concept
files	I-General_Concept
and	O
two	O
SSE	O
register	B-General_Concept
files	I-General_Concept
that	O
are	O
located	O
in	O
the	O
physical	B-General_Concept
register	I-General_Concept
file	I-General_Concept
directly	O
linked	O
with	O
GPRs	B-General_Concept
.	O
</s>
<s>
Like	O
early	O
AMD	O
designs	O
,	O
most	O
of	O
the	O
x86	B-Operating_System
manufacturers	O
like	O
Cyrix	O
,	O
VIA	O
,	O
DM&P	O
,	O
and	O
SIS	O
used	O
the	O
same	O
mechanism	O
as	O
well	O
,	O
resulting	O
in	O
a	O
lack	O
of	O
integer	O
performance	O
without	O
register	B-Architecture
renaming	I-Architecture
for	O
their	O
in-order	O
CPU	O
.	O
</s>
<s>
AMD	O
's	O
SSE	O
integer	O
operation	O
work	O
in	O
a	O
different	O
way	O
than	O
Core	B-Device
2	I-Device
and	O
Pentium	B-General_Concept
4	I-General_Concept
;	O
it	O
uses	O
its	O
separate	O
renaming	O
integer	O
register	O
to	O
load	O
the	O
value	O
directly	O
before	O
the	O
decode	O
stage	O
.	O
</s>
<s>
Though	O
theoretically	O
it	O
will	O
only	O
need	O
a	O
shorter	O
pipeline	O
than	O
Intel	O
's	O
SSE	O
implementation	O
,	O
but	O
generally	O
the	O
cost	O
of	O
branch	O
prediction	O
are	O
much	O
greater	O
and	O
higher	O
missing	O
rate	O
than	O
Intel	O
,	O
and	O
it	O
would	O
have	O
to	O
take	O
at	O
least	O
two	O
cycles	O
for	O
its	O
SSE	O
instruction	O
to	O
be	O
executed	O
regardless	O
of	O
instruction	O
wide	O
,	O
as	O
early	O
AMDs	O
implementations	O
could	O
not	O
execute	O
both	O
FP	O
and	O
Int	O
in	O
an	O
SSE	O
instruction	B-General_Concept
set	I-General_Concept
like	O
Intel	O
's	O
implementation	O
did	O
.	O
</s>
<s>
Unlike	O
Alpha	B-General_Concept
,	O
SPARC	B-Architecture
,	O
and	O
MIPS	B-Device
that	O
only	O
allows	O
one	O
register	B-General_Concept
file	I-General_Concept
to	O
load/fetch	O
one	O
operand	O
at	O
the	O
time	O
;	O
it	O
would	O
require	O
multiple	O
register	B-General_Concept
files	I-General_Concept
to	O
achieve	O
superscale	O
.	O
</s>
<s>
The	O
ARM	B-Architecture
processor	I-Architecture
on	O
the	O
other	O
hand	O
does	O
not	O
integrate	O
multiple	O
register	B-General_Concept
files	I-General_Concept
to	O
load/fetch	O
instructions	O
.	O
</s>
<s>
ARM	B-Architecture
GPRs	B-General_Concept
have	O
no	O
special	O
purpose	O
to	O
the	O
instruction	B-General_Concept
set	I-General_Concept
(	O
the	O
ARM	B-Architecture
ISA	O
does	O
not	O
require	O
accumulator	O
,	O
index	O
,	O
and	O
stack/base	O
points	O
.	O
</s>
<s>
Any	O
GPRs	B-General_Concept
can	O
propagate	O
and	O
store	O
multiple	O
instructions	O
independently	O
in	O
smaller	O
code	O
size	O
that	O
is	O
small	O
enough	O
to	O
be	O
able	O
to	O
fit	O
in	O
one	O
register	O
and	O
its	O
architectural	O
register	O
act	O
as	O
a	O
table	O
and	O
shared	O
with	O
all	O
decoder/instructions	O
with	O
simple	O
bank	O
switching	O
between	O
decoders	O
.	O
</s>
<s>
The	O
major	O
difference	O
between	O
ARM	B-Architecture
and	O
other	O
designs	O
is	O
that	O
ARM	B-Architecture
allows	O
to	O
run	O
on	O
the	O
same	O
general-purpose	O
register	O
with	O
quick	O
bank	O
switching	O
without	O
requiring	O
additional	O
register	B-General_Concept
file	I-General_Concept
in	O
superscalar	O
.	O
</s>
<s>
Despite	O
x86	B-Operating_System
sharing	O
the	O
same	O
mechanism	O
with	O
ARM	B-Architecture
that	O
its	O
GPRs	B-General_Concept
can	O
store	O
any	O
data	O
individually	O
,	O
x86	B-Operating_System
will	O
confront	O
data	O
dependency	O
if	O
more	O
than	O
three	O
non-related	O
instructions	O
are	O
stored	O
,	O
as	O
its	O
GPRs	B-General_Concept
per	O
file	O
are	O
too	O
small	O
(	O
eight	O
in	O
32bit	O
mode	O
and	O
16	O
in	O
64bit	O
,	O
compared	O
to	O
ARM	B-Architecture
's	O
13	O
in	O
32bit	O
and	O
31	O
in	O
64bit	O
)	O
for	O
data	O
,	O
and	O
it	O
is	O
impossible	O
to	O
have	O
superscalar	O
without	O
multiple	O
register	B-General_Concept
files	I-General_Concept
to	O
feed	O
to	O
its	O
decoder	O
(	O
x86	B-Operating_System
code	O
is	O
big	O
and	O
complex	O
compared	O
to	O
ARM	B-Architecture
)	O
.	O
</s>
<s>
Because	O
most	O
x86	B-Operating_System
's	O
front-ends	O
have	O
become	O
much	O
larger	O
and	O
much	O
more	O
power	O
hungry	O
than	O
the	O
ARM	B-Architecture
processor	I-Architecture
in	O
order	O
to	O
be	O
competitive	O
(	O
example	O
:	O
Pentium	B-General_Concept
M	O
&	O
Core	B-Device
2	I-Device
Duo	O
,	O
Bay	O
Trail	O
)	O
.	O
</s>
<s>
Some	O
third-party	O
x86	B-Operating_System
equivalent	O
processors	O
even	O
became	O
noncompetitive	O
with	O
ARM	B-Architecture
due	O
to	O
having	O
no	O
dedicated	O
register-file	O
architecture	B-General_Concept
.	O
</s>
<s>
Particularly	O
for	O
AMD	O
,	O
Cyrix	O
and	O
VIA	O
that	O
cannot	O
bring	O
any	O
reasonable	O
performance	O
without	O
register	B-Architecture
renaming	I-Architecture
and	O
out	O
of	O
order	O
execution	O
,	O
which	O
leave	O
only	O
Intel	O
Atom	B-Device
to	O
be	O
the	O
only	O
in-order	O
x86	B-Operating_System
processor	O
core	O
in	O
the	O
mobile	O
competition	O
.	O
</s>
<s>
This	O
was	O
until	O
the	O
x86	B-Operating_System
Nehalem	B-Device
processor	O
merged	O
both	O
of	O
its	O
integer	O
and	O
floating	O
point	O
register	O
into	O
one	O
single	O
file	O
,	O
and	O
the	O
introduction	O
of	O
a	O
large	O
physical	O
register	O
table	O
and	O
enhanced	O
allocator	O
table	O
in	O
its	O
front-end	O
before	O
renaming	O
in	O
its	O
out-of-order	O
internal	O
core	O
.	O
</s>
<s>
Processors	O
that	O
perform	O
register	B-Architecture
renaming	I-Architecture
can	O
arrange	O
for	O
each	O
functional	O
unit	O
to	O
write	O
to	O
a	O
subset	O
of	O
the	O
physical	B-General_Concept
register	I-General_Concept
file	I-General_Concept
.	O
</s>
<s>
This	O
arrangement	O
can	O
eliminate	O
the	O
need	O
for	O
multiple	O
write	O
ports	O
per	O
bit	B-General_Concept
cell	I-General_Concept
,	O
for	O
large	O
savings	O
in	O
area	O
.	O
</s>
<s>
The	O
resulting	O
register	B-General_Concept
file	I-General_Concept
,	O
effectively	O
a	O
stack	O
of	O
register	B-General_Concept
files	I-General_Concept
with	O
single	O
write	O
ports	O
,	O
then	O
benefits	O
from	O
replication	O
and	O
subsetting	O
the	O
read	O
ports	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
ISA	O
defines	O
register	B-General_Concept
windows	I-General_Concept
,	O
in	O
which	O
the	O
5-bit	O
architectural	O
names	O
of	O
the	O
registers	O
actually	O
point	O
into	O
a	O
window	O
on	O
a	O
much	O
larger	O
register	B-General_Concept
file	I-General_Concept
,	O
with	O
hundreds	O
of	O
entries	O
.	O
</s>
<s>
Implementing	O
multiported	O
register	B-General_Concept
files	I-General_Concept
with	O
hundreds	O
of	O
entries	O
requires	O
a	O
large	O
area	O
.	O
</s>
<s>
The	O
register	B-General_Concept
window	I-General_Concept
slides	O
by	O
16	O
registers	O
when	O
moved	O
,	O
so	O
that	O
each	O
architectural	O
register	O
name	O
can	O
refer	O
to	O
only	O
a	O
small	O
number	O
of	O
registers	O
in	O
the	O
larger	O
array	O
,	O
e.g.	O
</s>
<s>
To	O
save	O
area	O
,	O
some	O
SPARC	B-Architecture
implementations	O
implement	O
a	O
32-entry	O
register	B-General_Concept
file	I-General_Concept
,	O
in	O
which	O
each	O
cell	O
has	O
seven	O
"	O
bits	O
"	O
.	O
</s>
<s>
A	O
rotation	O
accomplishes	O
in	O
a	O
single	O
cycle	O
a	O
movement	O
of	O
the	O
register	B-General_Concept
window	I-General_Concept
.	O
</s>
<s>
This	O
same	O
technique	O
is	O
used	O
in	O
the	O
R10000	B-General_Concept
register	B-Architecture
renaming	I-Architecture
mapping	O
file	O
,	O
which	O
stores	O
a	O
6-bit	O
virtual	O
register	O
number	O
for	O
each	O
of	O
the	O
physical	O
registers	O
.	O
</s>
<s>
(	O
See	O
Register	B-Architecture
renaming	I-Architecture
.	O
)	O
</s>
