<s>
In	O
computer	O
engineering	O
,	O
a	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
is	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
designed	O
to	O
simplify	O
the	O
individual	O
instructions	O
given	O
to	O
the	O
computer	O
to	O
accomplish	O
tasks	O
.	O
</s>
<s>
Compared	O
to	O
the	O
instructions	O
given	O
to	O
a	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	B-Architecture
)	O
,	O
a	O
RISC	B-Architecture
computer	O
might	O
require	O
more	O
instructions	O
(	O
more	O
code	O
)	O
in	O
order	O
to	O
accomplish	O
a	O
task	O
because	O
the	O
individual	O
instructions	O
are	O
written	O
in	O
simpler	O
code	O
.	O
</s>
<s>
The	O
goal	O
is	O
to	O
offset	O
the	O
need	O
to	O
process	O
more	O
instructions	O
by	O
increasing	O
the	O
speed	O
of	O
each	O
instruction	O
,	O
in	O
particular	O
by	O
implementing	O
an	O
instruction	B-General_Concept
pipeline	I-General_Concept
,	O
which	O
may	O
be	O
simpler	O
given	O
simpler	O
instructions	O
.	O
</s>
<s>
The	O
key	O
operational	O
concept	O
of	O
the	O
RISC	B-Architecture
computer	O
is	O
that	O
each	O
instruction	O
performs	O
only	O
one	O
function	O
(	O
e.g.	O
</s>
<s>
The	O
RISC	B-Architecture
computer	O
usually	O
has	O
many	O
(	O
16	O
or	O
32	O
)	O
high-speed	O
,	O
general-purpose	O
registers	O
with	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
in	O
which	O
the	O
code	O
for	O
the	O
register-register	O
instructions	O
(	O
for	O
performing	O
arithmetic	O
and	O
tests	O
)	O
are	O
separate	O
from	O
the	O
instructions	O
that	O
grant	O
access	O
to	O
the	O
main	O
memory	O
of	O
the	O
computer	O
.	O
</s>
<s>
The	O
design	O
of	O
the	O
CPU	O
allows	O
RISC	B-Architecture
computers	O
few	O
simple	O
addressing	B-Language
modes	I-Language
and	O
predictable	O
instruction	O
times	O
that	O
simplify	O
design	O
of	O
the	O
system	O
as	O
a	O
whole	O
.	O
</s>
<s>
The	O
conceptual	O
developments	O
of	O
the	O
RISC	B-Architecture
computer	B-General_Concept
architecture	I-General_Concept
began	O
with	O
the	O
IBM	B-Device
801	I-Device
project	O
in	O
the	O
late	O
1970s	O
,	O
but	O
these	O
were	O
not	O
immediately	O
put	O
into	O
use	O
.	O
</s>
<s>
Designers	O
in	O
California	O
picked	O
up	O
the	O
801	O
concepts	O
in	O
two	O
seminal	O
projects	O
,	O
Stanford	B-General_Concept
MIPS	I-General_Concept
and	O
Berkeley	B-General_Concept
RISC	I-General_Concept
.	O
</s>
<s>
These	O
were	O
commercialized	O
in	O
the	O
1980s	O
as	O
the	O
MIPS	B-Device
and	O
SPARC	B-Architecture
systems	O
.	O
</s>
<s>
IBM	O
eventually	O
produced	O
RISC	B-Architecture
designs	O
based	O
on	O
further	O
work	O
on	O
the	O
801	O
concept	O
,	O
the	O
IBM	B-Architecture
POWER	I-Architecture
architecture	I-Architecture
,	O
PowerPC	B-Architecture
,	O
and	O
Power	B-Architecture
ISA	I-Architecture
.	O
</s>
<s>
As	O
the	O
projects	O
matured	O
,	O
many	O
similar	O
designs	O
,	O
produced	O
in	O
the	O
late	O
1980s	O
and	O
early	O
1990s	O
,	O
created	O
the	O
central	O
processing	O
units	O
that	O
increased	O
the	O
commercial	O
utility	O
of	O
the	O
Unix	B-Device
workstation	I-Device
and	O
of	O
embedded	B-Architecture
processors	I-Architecture
in	O
the	O
laser	O
printer	O
,	O
the	O
router	B-Protocol
,	O
and	O
similar	O
products	O
.	O
</s>
<s>
The	O
varieties	O
of	O
RISC	B-Architecture
processor	I-Architecture
design	O
include	O
the	O
ARC	B-Application
processor	I-Application
,	O
DEC	B-Device
Alpha	I-Device
,	O
the	O
AMD	B-General_Concept
Am29000	I-General_Concept
,	O
the	O
ARM	B-Architecture
architecture	I-Architecture
,	O
the	O
Atmel	B-Architecture
AVR	I-Architecture
,	O
Blackfin	B-General_Concept
,	O
Intel	B-General_Concept
i860	I-General_Concept
,	O
Intel	B-General_Concept
i960	I-General_Concept
,	O
LoongArch	O
,	O
Motorola	B-Architecture
88000	I-Architecture
,	O
the	O
MIPS	B-Device
architecture	I-Device
,	O
PA-RISC	B-Device
,	O
Power	B-Architecture
ISA	I-Architecture
,	O
RISC-V	B-Device
,	O
SuperH	O
,	O
and	O
SPARC	B-Architecture
.	O
</s>
<s>
RISC	B-Architecture
processors	I-Architecture
are	O
used	O
in	O
supercomputers	B-Architecture
,	O
such	O
as	O
the	O
Fugaku	B-Device
.	O
</s>
<s>
A	O
number	O
of	O
systems	O
,	O
going	O
back	O
to	O
the	O
1960s	O
,	O
have	O
been	O
credited	O
as	O
the	O
first	O
RISC	B-Architecture
architecture	O
,	O
partly	O
based	O
on	O
their	O
use	O
of	O
the	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
approach	O
.	O
</s>
<s>
The	O
term	O
RISC	B-Architecture
was	O
coined	O
by	O
David	O
Patterson	O
of	O
the	O
Berkeley	B-General_Concept
RISC	I-General_Concept
project	O
,	O
although	O
somewhat	O
similar	O
concepts	O
had	O
appeared	O
before	O
.	O
</s>
<s>
The	O
CDC	B-Device
6600	I-Device
designed	O
by	O
Seymour	O
Cray	O
in	O
1964	O
used	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
with	O
only	O
two	O
addressing	B-Language
modes	I-Language
(	O
register+register	O
,	O
and	O
register+immediate	O
constant	O
)	O
and	O
74	O
operation	B-Language
codes	I-Language
,	O
with	O
the	O
basic	O
clock	O
cycle	O
being	O
10	O
times	O
faster	O
than	O
the	O
memory	O
access	O
time	O
.	O
</s>
<s>
Partly	O
due	O
to	O
the	O
optimized	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
of	O
the	O
CDC	B-Device
6600	I-Device
,	O
Jack	O
Dongarra	O
says	O
that	O
it	O
can	O
be	O
considered	O
a	O
forerunner	O
of	O
modern	O
RISC	B-Architecture
systems	O
,	O
although	O
a	O
number	O
of	O
other	O
technical	O
barriers	O
needed	O
to	O
be	O
overcome	O
for	O
the	O
development	O
of	O
a	O
modern	O
RISC	B-Architecture
system	O
.	O
</s>
<s>
Michael	O
J	O
.	O
Flynn	O
views	O
the	O
first	O
RISC	B-Architecture
system	O
as	O
the	O
IBM	B-Device
801	I-Device
design	O
,	O
begun	O
in	O
1975	O
by	O
John	O
Cocke	O
and	O
completed	O
in	O
1980	O
.	O
</s>
<s>
The	O
801	O
developed	O
out	O
of	O
an	O
effort	O
to	O
build	O
a	O
24-bit	O
high-speed	O
processor	O
to	O
use	O
as	O
the	O
basis	O
for	O
a	O
digital	O
telephone	O
switch	B-Application
.	O
</s>
<s>
To	O
reach	O
their	O
goal	O
of	O
switching	O
1	O
million	O
calls	O
per	O
hour	O
(	O
300	O
per	O
second	O
)	O
they	O
calculated	O
that	O
the	O
CPU	O
required	O
performance	O
on	O
the	O
order	O
of	O
12	O
million	O
instructions	O
per	O
second	O
(	O
MIPS	B-Device
)	O
,	O
compared	O
to	O
their	O
fastest	O
mainframe	O
machine	O
of	O
the	O
time	O
,	O
the	O
370/168	B-Device
,	O
which	O
performed	O
at	O
3.5	O
MIPS	B-Device
.	O
</s>
<s>
This	O
demonstrated	O
that	O
code	O
in	O
high-performance	O
settings	O
made	O
extensive	O
use	O
of	O
processor	B-General_Concept
registers	I-General_Concept
,	O
and	O
that	O
they	O
often	O
ran	O
out	O
of	O
them	O
.	O
</s>
<s>
Additionally	O
,	O
they	O
noticed	O
that	O
compilers	B-Language
generally	O
ignored	O
the	O
vast	O
majority	O
of	O
the	O
available	O
instructions	O
,	O
especially	O
orthogonal	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
These	O
two	O
conclusions	O
worked	O
in	O
concert	O
;	O
removing	O
instructions	O
would	O
allow	O
the	O
instruction	B-Language
opcodes	I-Language
to	O
be	O
shorter	O
,	O
freeing	O
up	O
bits	O
in	O
the	O
instruction	B-Language
word	I-Language
which	O
could	O
then	O
be	O
used	O
to	O
select	O
among	O
a	O
larger	O
set	O
of	O
registers	O
.	O
</s>
<s>
The	O
telephone	O
switch	B-Application
program	O
was	O
canceled	O
in	O
1975	O
,	O
but	O
by	O
then	O
the	O
team	O
had	O
demonstrated	O
that	O
the	O
same	O
design	O
would	O
offer	O
significant	O
performance	O
gains	O
running	O
just	O
about	O
any	O
code	O
.	O
</s>
<s>
In	O
simulations	O
,	O
they	O
showed	O
that	O
a	O
compiler	B-Language
tuned	O
to	O
use	O
registers	O
wherever	O
possible	O
would	O
run	O
code	O
about	O
three	O
times	O
as	O
fast	O
as	O
traditional	O
designs	O
.	O
</s>
<s>
In	O
practice	O
,	O
their	O
experimental	O
PL/8	O
compiler	B-Language
,	O
a	O
slightly	O
cut-down	O
version	O
of	O
PL/I	B-Language
,	O
consistently	O
produced	O
code	O
that	O
ran	O
much	O
faster	O
on	O
their	O
existing	O
mainframes	O
.	O
</s>
<s>
A	O
32-bit	O
version	O
of	O
the	O
801	O
was	O
eventually	O
produced	O
in	O
a	O
single-chip	O
form	O
as	O
the	O
IBM	B-Device
ROMP	I-Device
in	O
1981	O
,	O
which	O
stood	O
for	O
'	O
Research	O
OPD	O
[	O
Office	O
Products	O
Division ]	O
Micro	B-Architecture
Processor	I-Architecture
 '	O
.	O
</s>
<s>
This	O
CPU	O
was	O
designed	O
for	O
"	O
mini	O
"	O
tasks	O
,	O
and	O
found	O
use	O
in	O
peripheral	O
interfaces	O
and	O
channel	B-Device
controllers	I-Device
on	O
later	O
IBM	O
computers	O
.	O
</s>
<s>
It	O
was	O
also	O
used	O
as	O
the	O
CPU	O
in	O
the	O
IBM	B-Device
RT	I-Device
PC	I-Device
in	O
1986	O
,	O
which	O
turned	O
out	O
to	O
be	O
a	O
commercial	O
failure	O
.	O
</s>
<s>
Although	O
the	O
801	O
did	O
not	O
see	O
widespread	O
use	O
in	O
its	O
original	O
form	O
,	O
it	O
inspired	O
many	O
research	O
projects	O
,	O
including	O
ones	O
at	O
IBM	O
that	O
would	O
eventually	O
lead	O
to	O
the	O
IBM	B-Architecture
POWER	I-Architecture
architecture	I-Architecture
.	O
</s>
<s>
The	O
Zilog	B-General_Concept
Z80	I-General_Concept
of	O
1976	O
had	O
8,000	O
transistors	B-Application
,	O
whereas	O
the	O
1979	O
Motorola	B-Device
68000	I-Device
(	O
68k	B-Device
)	O
had	O
68,000	O
.	O
</s>
<s>
These	O
newer	O
designs	O
generally	O
used	O
their	O
newfound	O
complexity	O
to	O
expand	O
the	O
instruction	B-General_Concept
set	I-General_Concept
to	O
make	O
it	O
more	O
orthogonal	O
.	O
</s>
<s>
Most	O
,	O
like	O
the	O
68k	B-Device
,	O
used	O
microcode	B-Device
to	O
do	O
this	O
,	O
reading	O
instructions	O
and	O
re-implementing	O
them	O
as	O
a	O
sequence	O
of	O
simpler	O
internal	O
instructions	O
.	O
</s>
<s>
In	O
the	O
68k	B-Device
,	O
a	O
full	O
of	O
the	O
transistors	B-Application
were	O
used	O
for	O
this	O
microcoding	B-Device
.	O
</s>
<s>
In	O
1979	O
,	O
David	O
Patterson	O
was	O
sent	O
on	O
a	O
sabbatical	O
from	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
to	O
help	O
DEC	O
's	O
west-coast	O
team	O
improve	O
the	O
VAX	B-Device
microcode	B-Device
.	O
</s>
<s>
He	O
first	O
wrote	O
a	O
paper	O
on	O
ways	O
to	O
improve	O
microcoding	B-Device
,	O
but	O
later	O
changed	O
his	O
mind	O
and	O
decided	O
microcode	B-Device
itself	O
was	O
the	O
problem	O
.	O
</s>
<s>
With	O
funding	O
from	O
the	O
DARPA	O
VLSI	O
Program	O
,	O
Patterson	O
started	O
the	O
Berkeley	B-General_Concept
RISC	I-General_Concept
effort	O
.	O
</s>
<s>
Considering	O
a	O
variety	O
of	O
programs	O
from	O
their	O
BSD	B-Operating_System
Unix	I-Operating_System
variant	O
,	O
the	O
Berkeley	O
team	O
found	O
,	O
as	O
had	O
IBM	O
,	O
that	O
most	O
programs	O
made	O
no	O
use	O
of	O
the	O
large	O
variety	O
of	O
instructions	O
in	O
the	O
68k	B-Device
.	O
</s>
<s>
Patterson	O
's	O
early	O
work	O
pointed	O
out	O
an	O
important	O
problem	O
with	O
the	O
traditional	O
"	O
more	O
is	O
better	O
"	O
approach	O
;	O
even	O
those	O
instructions	O
that	O
were	O
critical	O
to	O
overall	O
performance	O
were	O
being	O
delayed	O
by	O
their	O
trip	O
through	O
the	O
microcode	B-Device
.	O
</s>
<s>
If	O
the	O
microcode	B-Device
was	O
removed	O
,	O
the	O
programs	O
would	O
run	O
faster	O
.	O
</s>
<s>
And	O
since	O
the	O
microcode	B-Device
ultimately	O
took	O
a	O
complex	O
instruction	O
and	O
broke	O
it	O
into	O
steps	O
,	O
there	O
was	O
no	O
reason	O
the	O
compiler	B-Language
could	O
n't	O
do	O
this	O
instead	O
.	O
</s>
<s>
These	O
studies	O
suggested	O
that	O
,	O
even	O
with	O
no	O
other	O
changes	O
,	O
one	O
could	O
make	O
a	O
chip	O
with	O
fewer	O
transistors	B-Application
that	O
would	O
run	O
faster	O
.	O
</s>
<s>
In	O
the	O
original	O
RISC-I	O
paper	O
they	O
noted	O
:	O
</s>
<s>
It	O
was	O
also	O
discovered	O
that	O
,	O
on	O
microcoded	B-Device
implementations	O
of	O
certain	O
architectures	O
,	O
complex	O
operations	O
tended	O
to	O
be	O
slower	O
than	O
a	O
sequence	O
of	O
simpler	O
operations	O
doing	O
the	O
same	O
thing	O
.	O
</s>
<s>
One	O
infamous	O
example	O
was	O
the	O
VAX	B-Device
's	O
INDEX	O
instruction	O
.	O
</s>
<s>
This	O
led	O
the	O
Berkeley	O
design	O
to	O
select	O
a	O
method	O
known	O
as	O
register	B-General_Concept
windows	I-General_Concept
which	O
can	O
significantly	O
improve	O
subroutine	O
performance	O
although	O
at	O
the	O
cost	O
of	O
some	O
complexity	O
.	O
</s>
<s>
This	O
led	O
to	O
far	O
more	O
emphasis	O
on	O
the	O
underlying	O
arithmetic	O
data	O
unit	O
,	O
as	O
opposed	O
to	O
previous	O
designs	O
where	O
the	O
majority	O
of	O
the	O
chip	O
was	O
dedicated	O
to	O
control	O
and	O
microcode	B-Device
.	O
</s>
<s>
The	O
resulting	O
Berkeley	B-General_Concept
RISC	I-General_Concept
was	O
based	O
on	O
gaining	O
performance	O
through	O
the	O
use	O
of	O
pipelining	B-General_Concept
and	O
aggressive	O
use	O
of	O
register	B-General_Concept
windowing	I-General_Concept
.	O
</s>
<s>
In	O
a	O
CPU	O
with	O
register	B-General_Concept
windows	I-General_Concept
,	O
there	O
are	O
a	O
huge	O
number	O
of	O
registers	O
,	O
e.g.	O
,	O
128	O
,	O
but	O
programs	O
can	O
only	O
use	O
a	O
small	O
number	O
of	O
them	O
,	O
e.g.	O
,	O
eight	O
,	O
at	O
any	O
one	O
time	O
.	O
</s>
<s>
The	O
Berkeley	B-General_Concept
RISC	I-General_Concept
project	O
delivered	O
the	O
RISC-I	O
processor	O
in	O
1982	O
.	O
</s>
<s>
Consisting	O
of	O
only	O
44,420	O
transistors	B-Application
(	O
compared	O
with	O
averages	O
of	O
about	O
100,000	O
in	O
newer	O
CISC	B-Architecture
designs	O
of	O
the	O
era	O
)	O
,	O
RISC-I	O
had	O
only	O
32	O
instructions	O
,	O
and	O
yet	O
completely	O
outperformed	O
any	O
other	O
single-chip	O
design	O
,	O
with	O
estimated	O
performance	O
being	O
higher	O
than	O
the	O
VAX	B-Device
.	O
</s>
<s>
They	O
followed	O
this	O
up	O
with	O
the	O
40,760	O
-transistor	O
,	O
39-instruction	O
RISC-II	O
in	O
1983	O
,	O
which	O
ran	O
over	O
three	O
times	O
as	O
fast	O
as	O
RISC-I	O
.	O
</s>
<s>
As	O
the	O
RISC	B-Architecture
project	O
began	O
to	O
become	O
known	O
in	O
Silicon	O
Valley	O
,	O
a	O
similar	O
project	O
began	O
at	O
Stanford	O
University	O
in	O
1981	O
.	O
</s>
<s>
This	O
MIPS	B-Device
project	O
grew	O
out	O
of	O
a	O
graduate	O
course	O
by	O
John	O
L	O
.	O
Hennessy	O
,	O
produced	O
a	O
functioning	O
system	O
in	O
1983	O
,	O
and	O
could	O
run	O
simple	O
programs	O
by	O
1984	O
.	O
</s>
<s>
The	O
MIPS	B-Device
approach	O
emphasized	O
an	O
aggressive	O
clock	O
cycle	O
and	O
the	O
use	O
of	O
the	O
pipeline	O
,	O
making	O
sure	O
it	O
could	O
be	O
run	O
as	O
"	O
full	O
"	O
as	O
possible	O
.	O
</s>
<s>
The	O
MIPS	B-Device
system	O
was	O
followed	O
by	O
the	O
MIPS-X	B-General_Concept
and	O
in	O
1984	O
Hennessy	O
and	O
his	O
colleagues	O
formed	O
MIPS	B-Device
Computer	O
Systems	O
to	O
produce	O
the	O
design	O
commercially	O
.	O
</s>
<s>
The	O
venture	O
resulted	O
in	O
a	O
new	O
architecture	O
that	O
was	O
also	O
called	O
MIPS	B-Device
and	O
the	O
R2000	B-Device
microprocessor	I-Device
in	O
1985	O
.	O
</s>
<s>
The	O
overall	O
philosophy	O
of	O
the	O
RISC	B-Architecture
concept	O
was	O
widely	O
understood	O
by	O
the	O
second	O
half	O
of	O
the	O
1980s	O
,	O
and	O
led	O
the	O
designers	O
of	O
the	O
MIPS-X	B-General_Concept
to	O
put	O
it	O
this	O
way	O
in	O
1987	O
:	O
</s>
<s>
In	O
the	O
early	O
1980s	O
,	O
significant	O
uncertainties	O
surrounded	O
the	O
RISC	B-Architecture
concept	O
.	O
</s>
<s>
One	O
concern	O
involved	O
the	O
use	O
of	O
memory	O
;	O
a	O
single	O
instruction	O
from	O
a	O
traditional	O
processor	O
like	O
the	O
Motorola	B-Device
68k	I-Device
may	O
be	O
written	O
out	O
as	O
perhaps	O
a	O
half	O
dozen	O
of	O
the	O
simpler	O
RISC	B-Architecture
instructions	O
.	O
</s>
<s>
Commercial	O
RISC	B-Architecture
designs	O
began	O
to	O
emerge	O
in	O
the	O
mid-1980s	O
.	O
</s>
<s>
The	O
first	O
MIPS	B-Device
R2000	I-Device
appeared	O
in	O
January	O
1986	O
,	O
followed	O
shortly	O
thereafter	O
by	O
Hewlett-Packard	O
'	O
s	O
PA-RISC	B-Device
in	O
some	O
of	O
their	O
computers	O
.	O
</s>
<s>
In	O
1987	O
Sun	O
Microsystems	O
began	O
shipping	O
systems	O
with	O
the	O
SPARC	B-Architecture
processor	O
,	O
directly	O
based	O
on	O
the	O
Berkeley	O
RISC-II	O
system	O
.	O
</s>
<s>
The	O
US	O
government	O
Committee	O
on	O
Innovations	O
in	O
Computing	O
and	O
Communications	O
credits	O
the	O
acceptance	O
of	O
the	O
viability	O
of	O
the	O
RISC	B-Architecture
concept	O
to	O
the	O
success	O
of	O
the	O
SPARC	B-Architecture
system	O
.	O
</s>
<s>
The	O
success	O
of	O
SPARC	B-Architecture
renewed	O
interest	O
within	O
IBM	O
,	O
which	O
released	O
new	O
RISC	B-Architecture
systems	O
by	O
1990	O
and	O
by	O
1995	O
RISC	B-Architecture
processors	I-Architecture
were	O
the	O
foundation	O
of	O
a	O
$15billion	O
server	O
industry	O
.	O
</s>
<s>
By	O
the	O
later	O
1980s	O
,	O
the	O
new	O
RISC	B-Architecture
designs	O
were	O
easily	O
outperforming	O
all	O
traditional	O
designs	O
by	O
a	O
wide	O
margin	O
.	O
</s>
<s>
At	O
that	O
point	O
,	O
all	O
of	O
the	O
other	O
vendors	O
began	O
RISC	B-Architecture
efforts	O
of	O
their	O
own	O
.	O
</s>
<s>
Among	O
these	O
were	O
the	O
DEC	B-Device
Alpha	I-Device
,	O
AMD	B-General_Concept
Am29000	I-General_Concept
,	O
Intel	B-General_Concept
i860	I-General_Concept
and	O
i960	B-General_Concept
,	O
Motorola	B-Architecture
88000	I-Architecture
,	O
IBM	B-Device
POWER	I-Device
,	O
and	O
,	O
slightly	O
later	O
,	O
the	O
IBM/Apple/Motorola	O
PowerPC	B-Architecture
.	O
</s>
<s>
Those	O
that	O
remain	O
are	O
often	O
used	O
only	O
in	O
niche	O
markets	O
or	O
as	O
parts	O
of	O
other	O
systems	O
;	O
of	O
the	O
designs	O
from	O
these	O
traditional	O
vendors	O
,	O
only	O
SPARC	B-Architecture
and	O
POWER	O
have	O
any	O
significant	O
remaining	O
market	O
.	O
</s>
<s>
The	O
ARM	B-Architecture
architecture	I-Architecture
is	O
illustrative	O
of	O
the	O
adaptations	O
made	O
by	O
RISC	B-Architecture
vendors	O
to	O
respond	O
to	O
changing	O
competitive	O
circumstances	O
,	O
being	O
first	O
introduced	O
to	O
deliver	O
higher	O
performance	O
in	O
desktop	O
computers	O
such	O
as	O
the	O
Acorn	B-Device
Archimedes	I-Device
,	O
but	O
also	O
being	O
introduced	O
in	O
embedded	O
applications	O
such	O
as	O
laser	O
printer	O
raster	O
image	O
processing	O
.	O
</s>
<s>
ARM	B-Architecture
,	O
in	O
partnership	O
with	O
Apple	O
,	O
developed	O
a	O
low-power	O
design	O
and	O
then	O
specialized	O
in	O
that	O
market	O
,	O
which	O
at	O
the	O
time	O
was	O
a	O
niche	O
.	O
</s>
<s>
With	O
the	O
rise	O
in	O
mobile	O
computing	O
,	O
especially	O
after	O
the	O
introduction	O
of	O
the	O
iPhone	B-Device
,	O
ARM	B-Architecture
became	O
the	O
most	O
widely	O
used	O
high-end	O
CPU	O
design	O
in	O
the	O
market	O
.	O
</s>
<s>
Competition	O
between	O
RISC	B-Architecture
and	O
conventional	O
CISC	B-Architecture
approaches	O
was	O
also	O
the	O
subject	O
of	O
theoretical	O
analysis	O
in	O
the	O
early	O
1980s	O
,	O
leading	O
,	O
for	O
example	O
,	O
to	O
the	O
iron	O
law	O
of	O
processor	O
performance	O
.	O
</s>
<s>
Since	O
2010	O
,	O
a	O
new	O
open	B-License
source	I-License
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
,	O
RISC-V	B-Device
,	O
has	O
been	O
under	O
development	O
at	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
,	O
for	O
research	O
purposes	O
and	O
as	O
a	O
free	O
alternative	O
to	O
proprietary	O
ISAs	O
.	O
</s>
<s>
As	O
of	O
2014	O
,	O
version	O
2	O
of	O
the	O
user	B-Operating_System
space	I-Operating_System
ISA	O
is	O
fixed	O
.	O
</s>
<s>
The	O
ISA	O
is	O
designed	O
to	O
be	O
extensible	O
from	O
a	O
barebones	O
core	O
sufficient	O
for	O
a	O
small	O
embedded	B-Architecture
processor	I-Architecture
to	O
supercomputer	B-Architecture
and	O
cloud	O
computing	O
use	O
with	O
standard	O
and	O
chip	O
designer	O
–	O
defined	O
extensions	O
and	O
coprocessors	O
.	O
</s>
<s>
It	O
has	O
been	O
tested	O
in	O
silicon	O
design	O
with	O
the	O
ROCKET	O
SoC	B-Architecture
,	O
which	O
is	O
also	O
available	O
as	O
an	O
open-source	B-License
processor	O
generator	O
in	O
the	O
CHISEL	O
language	O
.	O
</s>
<s>
Confusion	O
around	O
the	O
definition	O
of	O
RISC	B-Architecture
deriving	O
from	O
the	O
formulation	O
of	O
the	O
term	O
,	O
along	O
with	O
the	O
tendency	O
to	O
opportunistically	O
categorise	O
processor	O
architectures	O
with	O
relatively	O
few	O
instructions	O
(	O
or	O
groups	O
of	O
instructions	O
)	O
as	O
RISC	B-Architecture
architectures	I-Architecture
,	O
led	O
to	O
attempts	O
to	O
define	O
RISC	B-Architecture
as	O
a	O
design	O
philosophy	O
.	O
</s>
<s>
A	O
common	O
misunderstanding	O
of	O
the	O
phrase	O
"	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
"	O
is	O
that	O
instructions	O
are	O
simply	O
eliminated	O
,	O
resulting	O
in	O
a	O
smaller	O
set	O
of	O
instructions	O
.	O
</s>
<s>
In	O
fact	O
,	O
over	O
the	O
years	O
,	O
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
have	O
grown	O
in	O
size	O
,	O
and	O
today	O
many	O
of	O
them	O
have	O
a	O
larger	O
set	O
of	O
instructions	O
than	O
many	O
CISC	B-Architecture
CPUs	O
.	O
</s>
<s>
Some	O
RISC	B-Architecture
processors	I-Architecture
such	O
as	O
the	O
PowerPC	B-Architecture
have	O
instruction	B-General_Concept
sets	I-General_Concept
as	O
large	O
as	O
the	O
CISC	B-Architecture
IBM	B-Device
System/370	I-Device
,	O
for	O
example	O
;	O
conversely	O
,	O
the	O
DEC	B-Device
PDP-8	I-Device
—	O
clearly	O
a	O
CISC	B-Architecture
CPU	O
because	O
many	O
of	O
its	O
instructions	O
involve	O
multiple	O
memory	O
accesses	O
—	O
has	O
only	O
8	O
basic	O
instructions	O
and	O
a	O
few	O
extended	O
instructions	O
.	O
</s>
<s>
The	O
term	O
"	O
reduced	O
"	O
in	O
that	O
phrase	O
was	O
intended	O
to	O
describe	O
the	O
fact	O
that	O
the	O
amount	O
of	O
work	O
any	O
single	O
instruction	O
accomplishes	O
is	O
reduced	O
—	O
at	O
most	O
a	O
single	O
data	O
memory	O
cycle	O
—	O
compared	O
to	O
the	O
"	O
complex	O
instructions	O
"	O
of	O
CISC	B-Architecture
CPUs	O
that	O
may	O
require	O
dozens	O
of	O
data	O
memory	O
cycles	O
in	O
order	O
to	O
execute	O
a	O
single	O
instruction	O
.	O
</s>
<s>
The	O
term	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
is	O
sometimes	O
preferred	O
.	O
</s>
<s>
Another	O
way	O
of	O
looking	O
at	O
the	O
RISC/CISC	O
debate	O
is	O
to	O
consider	O
what	O
is	O
exposed	O
to	O
the	O
compiler	B-Language
.	O
</s>
<s>
In	O
a	O
CISC	B-Architecture
processor	I-Architecture
,	O
the	O
hardware	O
may	O
internally	O
use	O
registers	O
and	O
flag	O
bit	O
in	O
order	O
to	O
implement	O
a	O
single	O
complex	O
instruction	O
such	O
as	O
,	O
but	O
hide	O
those	O
details	O
from	O
the	O
compiler	B-Language
.	O
</s>
<s>
The	O
internal	O
operations	O
of	O
a	O
RISC	B-Architecture
processor	I-Architecture
are	O
"	O
exposed	O
to	O
the	O
compiler	B-Language
"	O
,	O
leading	O
to	O
the	O
backronym	O
'	O
Relegate	O
Interesting	O
Stuff	O
to	O
the	O
Compiler	B-Language
 '	O
.	O
</s>
<s>
Most	O
RISC	B-Architecture
architectures	I-Architecture
have	O
fixed-length	O
instructions	O
and	O
a	O
simple	O
encoding	O
,	O
which	O
simplifies	O
fetch	O
,	O
decode	O
,	O
and	O
issue	O
logic	O
considerably	O
.	O
</s>
<s>
This	O
is	O
among	O
the	O
main	O
goals	O
of	O
the	O
RISC	B-Architecture
approach	O
.	O
</s>
<s>
For	O
instance	O
,	O
in	O
a	O
typical	O
program	O
,	O
over	O
30%	O
of	O
all	O
the	O
numeric	B-Algorithm
constants	O
are	O
either	O
0	O
or	O
1	O
,	O
95%	O
will	O
fit	O
in	O
one	O
byte	B-Application
,	O
and	O
99%	O
in	O
a	O
16-bit	O
value	O
.	O
</s>
<s>
When	O
computers	O
were	O
based	O
on	O
8	O
-	O
or	O
16-bit	O
words	O
,	O
it	O
would	O
be	O
difficult	O
to	O
have	O
an	O
immediate	O
combined	O
with	O
the	O
opcode	B-Language
in	O
a	O
single	O
memory	O
word	O
,	O
although	O
certain	O
instructions	O
like	O
increment	O
and	O
decrement	O
did	O
this	O
implicitly	O
by	O
using	O
a	O
different	O
opcode	B-Language
.	O
</s>
<s>
This	O
is	O
why	O
many	O
RISC	B-Architecture
processors	I-Architecture
allow	O
a	O
12	O
-	O
or	O
13-bit	O
constant	O
to	O
be	O
encoded	O
directly	O
into	O
the	O
instruction	B-Language
word	I-Language
.	O
</s>
<s>
Assuming	O
a	O
13-bit	O
constant	O
area	O
,	O
as	O
is	O
the	O
case	O
in	O
the	O
MIPS	B-Device
and	O
RISC	B-Architecture
designs	O
,	O
another	O
19	O
bits	O
are	O
available	O
for	O
the	O
instruction	O
encoding	O
.	O
</s>
<s>
This	O
leaves	O
ample	O
room	O
to	O
indicate	O
both	O
the	O
opcode	B-Language
and	O
one	O
or	O
two	O
registers	O
.	O
</s>
<s>
If	O
one	O
of	O
these	O
registers	O
is	O
replaced	O
by	O
an	O
immediate	O
,	O
there	O
is	O
still	O
lots	O
of	O
room	O
to	O
encode	O
the	O
two	O
remaining	O
registers	O
and	O
the	O
opcode	B-Language
.	O
</s>
<s>
Common	O
instructions	O
found	O
in	O
multi-word	O
systems	O
,	O
like	O
and	O
,	O
which	O
reduce	O
the	O
number	O
of	O
words	O
that	O
have	O
to	O
be	O
read	O
before	O
performing	O
the	O
instruction	O
,	O
are	O
unnecessary	O
in	O
RISC	B-Architecture
as	O
they	O
can	O
be	O
accomplished	O
with	O
a	O
single	O
register	O
and	O
the	O
immediate	O
value	O
1	O
.	O
</s>
<s>
The	O
original	O
RISC-I	O
format	O
remains	O
a	O
canonical	O
example	O
of	O
the	O
concept	O
.	O
</s>
<s>
It	O
uses	O
7	O
bits	O
for	O
the	O
opcode	B-Language
and	O
a	O
1-bit	O
flag	O
for	O
conditional	O
codes	O
,	O
the	O
following	O
5	O
bits	O
for	O
the	O
destination	O
register	O
,	O
and	O
the	O
next	O
five	O
for	O
the	O
first	O
operand	O
.	O
</s>
<s>
A	O
more	O
complex	O
example	O
is	O
the	O
MIPS	B-Device
encoding	O
,	O
which	O
used	O
only	O
6	O
bits	O
for	O
the	O
opcode	B-Language
,	O
followed	O
by	O
two	O
5-bit	O
registers	O
.	O
</s>
<s>
The	O
remaining	O
16	O
bits	O
could	O
be	O
used	O
in	O
two	O
ways	O
,	O
one	O
as	O
a	O
16-bit	O
immediate	O
value	O
,	O
or	O
as	O
a	O
5-bit	O
shift	O
value	O
(	O
used	O
only	O
in	O
shift	O
operations	O
,	O
otherwise	O
zero	O
)	O
and	O
the	O
remaining	O
6	O
bits	O
as	O
an	O
extension	O
on	O
the	O
opcode	B-Language
.	O
</s>
<s>
In	O
the	O
case	O
of	O
register-to-register	O
arithmetic	O
operations	O
,	O
the	O
opcode	B-Language
was	O
0	O
and	O
the	O
last	O
6	O
bits	O
contained	O
the	O
actual	O
code	O
;	O
those	O
that	O
used	O
an	O
immediate	O
value	O
used	O
the	O
normal	O
opcode	B-Language
field	O
at	O
the	O
front	O
.	O
</s>
<s>
One	O
drawback	O
of	O
32-bit	O
instructions	O
is	O
reduced	O
code	O
density	O
,	O
which	O
is	O
more	O
adverse	O
a	O
characteristic	O
in	O
embedded	B-Architecture
computing	I-Architecture
than	O
it	O
is	O
in	O
the	O
workstation	B-Device
and	O
server	O
markets	O
RISC	B-Architecture
architectures	I-Architecture
were	O
originally	O
designed	O
to	O
serve	O
.	O
</s>
<s>
To	O
address	O
this	O
problem	O
,	O
several	O
architectures	O
,	O
such	O
as	O
ARM	B-Architecture
,	O
Power	B-Architecture
ISA	I-Architecture
,	O
MIPS	B-Device
,	O
RISC-V	B-Device
,	O
and	O
the	O
Adapteva	B-Application
Epiphany	I-Application
,	O
have	O
an	O
optional	O
short	O
,	O
feature-reduced	O
compressed	B-Architecture
instruction	I-Architecture
set	I-Architecture
.	O
</s>
<s>
A	O
two-operand	O
format	O
in	O
a	O
system	O
with	O
16	O
registers	O
requires	O
8	O
bits	O
for	O
register	O
numbers	O
,	O
leaving	O
another	O
8	O
for	O
an	O
opcode	B-Language
or	O
other	O
uses	O
.	O
</s>
<s>
For	O
any	O
given	O
level	O
of	O
general	O
performance	O
,	O
a	O
RISC	B-Architecture
chip	O
will	O
typically	O
have	O
far	O
fewer	O
transistors	B-Application
dedicated	O
to	O
the	O
core	O
logic	O
which	O
originally	O
allowed	O
designers	O
to	O
increase	O
the	O
size	O
of	O
the	O
register	O
set	O
and	O
increase	O
internal	O
parallelism	O
.	O
</s>
<s>
Other	O
features	O
of	O
RISC	B-Architecture
architectures	I-Architecture
include	O
:	O
</s>
<s>
RISC	B-Architecture
designs	O
are	O
also	O
more	O
likely	O
to	O
feature	O
a	O
Harvard	B-Architecture
memory	I-Architecture
model	I-Architecture
,	O
where	O
the	O
instruction	O
stream	O
and	O
the	O
data	O
stream	O
are	O
conceptually	O
separated	O
;	O
this	O
means	O
that	O
modifying	O
the	O
memory	O
where	O
code	O
is	O
held	O
might	O
not	O
have	O
any	O
effect	O
on	O
the	O
instructions	O
executed	O
by	O
the	O
processor	O
(	O
because	O
the	O
CPU	O
has	O
a	O
separate	O
instruction	O
and	O
data	B-General_Concept
cache	I-General_Concept
)	O
,	O
at	O
least	O
until	O
a	O
special	O
synchronization	O
instruction	O
is	O
issued	O
;	O
CISC	B-Architecture
processors	I-Architecture
that	O
have	O
separate	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
generally	O
keep	O
them	O
synchronized	O
automatically	O
,	O
for	O
backwards	O
compatibility	O
with	O
older	O
processors	O
.	O
</s>
<s>
Many	O
early	O
RISC	B-Architecture
designs	O
also	O
shared	O
the	O
characteristic	O
of	O
having	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
,	O
an	O
instruction	O
space	O
immediately	O
following	O
a	O
jump	O
or	O
branch	O
.	O
</s>
<s>
This	O
instruction	O
keeps	O
the	O
ALU	B-General_Concept
of	O
the	O
CPU	O
busy	O
for	O
the	O
extra	O
time	O
normally	O
needed	O
to	O
perform	O
a	O
branch	O
.	O
</s>
<s>
Nowadays	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
is	O
considered	O
an	O
unfortunate	O
side	O
effect	O
of	O
a	O
particular	O
strategy	O
for	O
implementing	O
some	O
RISC	B-Architecture
designs	O
,	O
and	O
modern	O
RISC	B-Architecture
designs	O
generally	O
do	O
away	O
with	O
it	O
(	O
such	O
as	O
PowerPC	B-Architecture
and	O
more	O
recent	O
versions	O
of	O
SPARC	B-Architecture
and	O
MIPS	B-Device
)	O
.	O
</s>
<s>
Some	O
aspects	O
attributed	O
to	O
the	O
first	O
RISC-labeled	O
designs	O
around	O
1975	O
include	O
the	O
observations	O
that	O
the	O
memory-restricted	O
compilers	B-Language
of	O
the	O
time	O
were	O
often	O
unable	O
to	O
take	O
advantage	O
of	O
features	O
intended	O
to	O
facilitate	O
manual	O
assembly	O
coding	O
,	O
and	O
that	O
complex	O
addressing	B-Language
modes	I-Language
take	O
many	O
cycles	O
to	O
perform	O
due	O
to	O
the	O
required	O
additional	O
memory	O
accesses	O
.	O
</s>
<s>
In	O
these	O
simple	O
designs	O
,	O
most	O
instructions	O
are	O
of	O
uniform	O
length	O
and	O
similar	O
structure	O
,	O
arithmetic	O
operations	O
are	O
restricted	O
to	O
CPU	B-General_Concept
registers	I-General_Concept
and	O
only	O
separate	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
access	O
memory	O
.	O
</s>
<s>
These	O
properties	O
enable	O
a	O
better	O
balancing	O
of	O
pipeline	B-General_Concept
stages	I-General_Concept
than	O
before	O
,	O
making	O
RISC	B-General_Concept
pipelines	I-General_Concept
significantly	O
more	O
efficient	O
and	O
allowing	O
higher	O
clock	O
frequencies	O
.	O
</s>
<s>
Yet	O
another	O
impetus	O
of	O
both	O
RISC	B-Architecture
and	O
other	O
designs	O
came	O
from	O
practical	O
measurements	O
on	O
real-world	O
programs	O
.	O
</s>
<s>
This	O
suggests	O
that	O
,	O
to	O
reduce	O
the	O
number	O
of	O
memory	O
accesses	O
,	O
a	O
fixed	O
length	O
machine	O
could	O
store	O
constants	O
in	O
unused	O
bits	O
of	O
the	O
instruction	B-Language
word	I-Language
itself	O
,	O
so	O
that	O
they	O
would	O
be	O
immediately	O
ready	O
when	O
the	O
CPU	O
needs	O
them	O
(	O
much	O
like	O
immediate	O
addressing	O
in	O
a	O
conventional	O
design	O
)	O
.	O
</s>
<s>
This	O
required	O
small	O
opcodes	B-Language
in	O
order	O
to	O
leave	O
room	O
for	O
a	O
reasonably	O
sized	O
constant	O
in	O
a	O
32-bit	O
instruction	B-Language
word	I-Language
.	O
</s>
<s>
The	O
focus	O
on	O
"	O
reduced	O
instructions	O
"	O
led	O
to	O
the	O
resulting	O
machine	O
being	O
called	O
a	O
"	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
"	O
(	O
RISC	B-Architecture
)	O
.	O
</s>
<s>
The	O
goal	O
was	O
to	O
make	O
instructions	O
so	O
simple	O
that	O
they	O
could	O
easily	O
be	O
pipelined	B-General_Concept
,	O
in	O
order	O
to	O
achieve	O
a	O
single	O
clock	O
throughput	O
at	O
high	O
frequencies	O
.	O
</s>
<s>
Later	O
,	O
it	O
was	O
noted	O
that	O
one	O
of	O
the	O
most	O
significant	O
characteristics	O
of	O
RISC	B-Architecture
processors	I-Architecture
was	O
that	O
external	O
memory	O
was	O
only	O
accessible	O
by	O
a	O
load	O
or	O
store	O
instruction	O
.	O
</s>
<s>
This	O
simplified	O
many	O
aspects	O
of	O
processor	O
design	O
:	O
allowing	O
instructions	O
to	O
be	O
fixed-length	O
,	O
simplifying	O
pipelines	O
,	O
and	O
isolating	O
the	O
logic	O
for	O
dealing	O
with	O
the	O
delay	O
in	O
completing	O
a	O
memory	O
access	O
(	O
cache	B-General_Concept
miss	O
,	O
etc	O
.	O
)	O
</s>
<s>
This	O
led	O
to	O
RISC	B-Architecture
designs	O
being	O
referred	O
to	O
as	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architectures	I-Architecture
.	O
</s>
<s>
Some	O
CPUs	O
have	O
been	O
specifically	O
designed	O
to	O
have	O
a	O
very	O
small	O
set	O
of	O
instructionsbut	O
these	O
designs	O
are	O
very	O
different	O
from	O
classic	O
RISC	B-Architecture
designs	O
,	O
so	O
they	O
have	O
been	O
given	O
other	O
names	O
such	O
as	O
minimal	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
computer	I-General_Concept
(	O
MISC	O
)	O
or	O
transport	B-General_Concept
triggered	I-General_Concept
architecture	I-General_Concept
(	O
TTA	O
)	O
.	O
</s>
<s>
RISC	B-Architecture
architectures	I-Architecture
have	O
traditionally	O
had	O
few	O
successes	O
in	O
the	O
desktop	O
PC	O
and	O
commodity	O
server	O
markets	O
,	O
where	O
the	O
x86-based	O
platforms	O
remain	O
the	O
dominant	O
processor	O
architecture	O
.	O
</s>
<s>
However	O
,	O
this	O
may	O
change	O
,	O
as	O
ARM-based	O
processors	O
are	O
being	O
developed	O
for	O
higher	O
performance	O
systems	O
.	O
</s>
<s>
Manufacturers	O
including	O
Cavium	O
,	O
AMD	O
,	O
and	O
Qualcomm	O
have	O
released	O
server	O
processors	O
based	O
on	O
the	O
ARM	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
ARM	B-Architecture
further	O
partnered	O
with	O
Cray	O
in	O
2017	O
to	O
produce	O
an	O
ARM-based	O
supercomputer	B-Architecture
.	O
</s>
<s>
On	O
the	O
desktop	O
,	O
Microsoft	O
announced	O
that	O
it	O
planned	O
to	O
support	O
the	O
PC	O
version	O
of	O
Windows	B-Operating_System
10	I-Operating_System
on	O
Qualcomm	O
Snapdragon-based	O
devices	O
in	O
2017	O
as	O
part	O
of	O
its	O
partnership	O
with	O
Qualcomm	O
.	O
</s>
<s>
These	O
devices	O
will	O
support	O
Windows	O
applications	O
compiled	B-Language
for	O
32-bit	O
x86	B-Operating_System
via	O
an	O
x86	B-Operating_System
processor	O
emulator	B-Application
that	O
translates	O
32-bit	O
x86	B-Operating_System
code	O
to	O
ARM64	O
code	O
.	O
</s>
<s>
Apple	O
announced	O
they	O
will	O
transition	B-Device
their	O
Mac	B-Device
desktop	O
and	O
laptop	O
computers	O
from	O
Intel	O
processors	O
to	O
internally	O
developed	O
ARM64-based	O
SoCs	B-Architecture
called	O
Apple	B-Device
silicon	I-Device
;	O
the	O
first	O
such	O
computers	O
,	O
using	O
the	O
Apple	B-Device
M1	I-Device
processor	O
,	O
were	O
released	O
in	O
November	O
2020	O
.	O
</s>
<s>
Macs	B-Device
with	O
Apple	B-Device
silicon	I-Device
can	O
run	O
x86-64	O
binaries	O
with	O
Rosetta	O
2	O
,	O
an	O
x86-64	O
to	O
ARM64	O
translator	O
.	O
</s>
<s>
Outside	O
of	O
the	O
desktop	O
arena	O
,	O
however	O
,	O
the	O
ARM	B-Architecture
RISC	B-Architecture
architecture	O
is	O
in	O
widespread	O
use	O
in	O
smartphones	O
,	O
tablets	B-Device
and	O
many	O
forms	O
of	O
embedded	B-Architecture
devices	I-Architecture
.	O
</s>
<s>
While	O
early	O
RISC	B-Architecture
designs	O
differed	O
significantly	O
from	O
contemporary	O
CISC	B-Architecture
designs	O
,	O
by	O
2000	O
the	O
highest-performing	O
CPUs	O
in	O
the	O
RISC	B-Architecture
line	O
were	O
almost	O
indistinguishable	O
from	O
the	O
highest-performing	O
CPUs	O
in	O
the	O
CISC	B-Architecture
line	O
.	O
</s>
<s>
RISC	B-Architecture
architectures	I-Architecture
are	O
now	O
used	O
across	O
a	O
range	O
of	O
platforms	O
,	O
from	O
smartphones	O
and	O
tablet	B-Device
computers	I-Device
to	O
some	O
of	O
the	O
world	O
's	O
fastest	B-Operating_System
supercomputers	I-Operating_System
such	O
as	O
Fugaku	B-Device
,	O
the	O
fastest	O
on	O
the	O
TOP500	B-Operating_System
list	O
,	O
and	O
Summit	B-Device
,	O
Sierra	B-Device
,	O
and	O
Sunway	B-Device
TaihuLight	I-Device
,	O
the	O
next	O
three	O
on	O
that	O
list	O
.	O
</s>
<s>
By	O
the	O
beginning	O
of	O
the	O
21st	O
century	O
,	O
the	O
majority	O
of	O
low-end	O
and	O
mobile	O
systems	O
relied	O
on	O
RISC	B-Architecture
architectures	I-Architecture
.	O
</s>
<s>
The	O
ARM	B-Architecture
architecture	I-Architecture
dominates	O
the	O
market	O
for	O
low-power	O
and	O
low-cost	O
embedded	B-Architecture
systems	I-Architecture
(	O
typically	O
200	O
–	O
1800MHz	O
in	O
2014	O
)	O
.	O
</s>
<s>
It	O
is	O
used	O
in	O
a	O
number	O
of	O
systems	O
such	O
as	O
most	O
Android-based	O
systems	O
,	O
the	O
Apple	O
iPhone	B-Device
and	O
iPad	B-Device
,	O
Microsoft	B-Protocol
Windows	I-Protocol
Phone	I-Protocol
(	O
former	O
Windows	B-Operating_System
Mobile	I-Operating_System
)	O
,	O
RIM	O
devices	O
,	O
Nintendo	B-Device
Game	I-Device
Boy	I-Device
Advance	I-Device
,	O
DS	B-Device
,	O
3DS	B-Operating_System
and	O
Switch	B-Application
,	O
Raspberry	B-Operating_System
Pi	I-Operating_System
,	O
etc	O
.	O
</s>
<s>
IBM	O
's	O
PowerPC	B-Architecture
was	O
used	O
in	O
the	O
GameCube	B-Application
,	O
Wii	B-Operating_System
,	O
PlayStation	B-Operating_System
3	I-Operating_System
,	O
Xbox	B-Operating_System
360	I-Operating_System
and	O
Wii	B-Device
U	I-Device
gaming	O
consoles	O
.	O
</s>
<s>
The	O
MIPS	B-Device
line	O
(	O
at	O
one	O
point	O
used	O
in	O
many	O
SGI	O
computers	O
)	O
was	O
used	O
in	O
the	O
PlayStation	B-Device
,	O
PlayStation	B-Device
2	I-Device
,	O
Nintendo	B-Operating_System
64	I-Operating_System
,	O
PlayStation	B-Operating_System
Portable	I-Operating_System
game	O
consoles	O
,	O
and	O
residential	B-Application
gateways	I-Application
like	O
Linksys	B-Application
WRT54G	I-Application
series	I-Application
.	O
</s>
<s>
Hitachi	O
's	O
SuperH	O
,	O
originally	O
in	O
wide	O
use	O
in	O
the	O
Sega	B-Device
Super	I-Device
32X	I-Device
,	O
Saturn	B-Device
and	O
Dreamcast	B-Operating_System
,	O
now	O
developed	O
and	O
sold	O
by	O
Renesas	O
as	O
the	O
SH4	O
.	O
</s>
<s>
Atmel	B-Architecture
AVR	I-Architecture
,	O
used	O
in	O
a	O
variety	O
of	O
products	O
ranging	O
from	O
Xbox	B-Application
handheld	O
controllers	O
and	O
the	O
Arduino	O
open-source	B-License
microcontroller	O
platform	O
to	O
BMW	O
cars	O
.	O
</s>
<s>
RISC-V	B-Device
,	O
the	O
open-source	B-License
fifth	O
Berkeley	B-General_Concept
RISC	I-General_Concept
ISA	O
,	O
with	O
32	O
-	O
or	O
64-bit	O
address	B-General_Concept
spaces	I-General_Concept
,	O
a	O
small	O
core	O
integer	O
instruction	B-General_Concept
set	I-General_Concept
,	O
and	O
an	O
experimental	O
"	O
Compressed	O
"	O
ISA	O
for	O
code	O
density	O
and	O
designed	O
for	O
standard	O
and	O
special-purpose	O
extensions	O
.	O
</s>
<s>
IBM	O
's	O
PowerPC	B-Architecture
architecture	O
was	O
used	O
in	O
Apple	B-Device
's	I-Device
Macintosh	I-Device
computers	O
from	O
1994	O
,	O
when	O
they	O
began	O
a	O
switch	B-Application
from	O
Motorola	B-Device
68000	I-Device
family	I-Device
processors	O
,	O
to	O
2005	O
,	O
when	O
they	O
transitioned	B-Device
to	I-Device
Intel	I-Device
x86	I-Device
processors	I-Device
.	O
</s>
<s>
Some	O
chromebooks	B-Operating_System
use	O
ARM-based	O
platforms	O
since	O
2012	O
.	O
</s>
<s>
Apple	O
uses	O
inhouse-designed	B-Device
processors	I-Device
based	O
on	O
the	O
ARM	B-Architecture
architecture	I-Architecture
for	O
its	O
lineup	O
of	O
desktop	O
and	O
laptop	O
computers	O
since	O
its	O
transition	B-Device
from	O
Intel	O
processors	O
,	O
and	O
the	O
first	O
such	O
computers	O
were	O
released	O
in	O
November	O
2020	O
.	O
</s>
<s>
Microsoft	O
uses	O
Qualcomm	O
ARM-based	O
processors	O
for	O
its	O
Surface	B-Device
line	O
.	O
</s>
<s>
HP	O
Inc	O
and	O
Lenovo	O
have	O
released	O
Windows	O
PCs	O
with	O
an	O
ARM-based	O
Qualcomm	B-Architecture
Snapdragon	I-Architecture
.	O
</s>
<s>
MIPS	B-Device
,	O
by	O
Silicon	O
Graphics	O
(	O
ceased	O
making	O
MIPS-based	O
systems	O
in	O
2006	O
)	O
.	O
</s>
<s>
SPARC	B-Architecture
,	O
by	O
Oracle	B-Application
(	O
previously	O
Sun	O
Microsystems	O
)	O
,	O
and	O
Fujitsu	O
.	O
</s>
<s>
IBM	O
's	O
IBM	B-Architecture
POWER	I-Architecture
architecture	I-Architecture
,	O
PowerPC	B-Architecture
,	O
and	O
Power	B-Architecture
ISA	I-Architecture
were	O
and	O
are	O
used	O
in	O
many	O
of	O
IBM	O
's	O
supercomputers	B-Architecture
,	O
mid-range	O
servers	O
and	O
workstations	B-Device
.	O
</s>
<s>
Hewlett-Packard	O
'	O
s	O
PA-RISC	B-Device
,	O
also	O
known	O
as	O
HP-PA	B-Device
(	O
discontinued	O
at	O
the	O
end	O
of	O
2008	O
)	O
.	O
</s>
<s>
Alpha	B-Device
,	O
used	O
in	O
single-board	B-Device
computers	I-Device
,	O
workstations	B-Device
,	O
servers	O
and	O
supercomputers	B-Architecture
from	O
Digital	O
Equipment	O
Corporation	O
,	O
then	O
Compaq	O
and	O
finally	O
Hewlett-Packard	O
(	O
HP	O
)	O
(	O
discontinued	O
as	O
of	O
2007	O
)	O
.	O
</s>
<s>
RISC-V	B-Device
,	O
the	O
open	B-License
source	I-License
fifth	O
Berkeley	B-General_Concept
RISC	I-General_Concept
ISA	O
,	O
with	O
64	O
-	O
or	O
128-bit	O
address	B-General_Concept
spaces	I-General_Concept
,	O
and	O
the	O
integer	O
core	O
extended	O
with	O
floating	B-Algorithm
point	I-Algorithm
,	O
atomics	B-General_Concept
and	O
vector	B-Operating_System
processing	I-Operating_System
,	O
and	O
designed	O
to	O
be	O
extended	O
with	O
instructions	O
for	O
networking	O
,	O
I/O	O
,	O
and	O
data	O
processing	O
.	O
</s>
<s>
It	O
is	O
implemented	O
in	O
the	O
European	B-General_Concept
Processor	I-General_Concept
Initiative	I-General_Concept
processor	O
.	O
</s>
<s>
The	O
ARM	B-Architecture
architecture	I-Architecture
was	O
used	O
in	O
the	O
Fujitsu	B-Device
A64FX	I-Device
chip	O
to	O
create	O
Fugaku	B-Device
,	O
the	O
world	O
's	O
fastest	B-Operating_System
supercomputer	I-Operating_System
in	O
2020	O
.	O
</s>
<s>
RISC	B-Architecture
architectures	I-Architecture
have	O
become	O
popular	O
in	O
open	B-License
source	I-License
processors	O
and	O
soft	B-Device
microprocessors	I-Device
since	O
they	O
are	O
relatively	O
simple	O
to	O
implement	O
,	O
which	O
makes	O
them	O
suitable	O
for	O
FPGA	B-Architecture
implementations	O
and	O
prototyping	O
,	O
for	O
instance	O
.	O
</s>
<s>
OpenRISC	B-Device
,	O
an	O
open	O
instruction	B-General_Concept
set	I-General_Concept
and	O
micro-architecture	O
first	O
introduced	O
in	O
2000	O
.	O
</s>
<s>
LEON	B-General_Concept
,	O
an	O
open	B-License
source	I-License
,	O
radiation-tolerant	O
implementation	O
of	O
the	O
SPARC	B-Architecture
V8	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
(	O
targeting	O
space	O
applications	O
)	O
.	O
</s>
<s>
Libre-SOC	B-General_Concept
,	O
an	O
open	B-License
source	I-License
SoC	B-Architecture
based	O
on	O
the	O
Power	B-Architecture
ISA	I-Architecture
with	O
extensions	O
for	O
video	O
and	O
3D	O
graphics	O
.	O
</s>
<s>
There	O
are	O
also	O
several	O
open	B-License
source	I-License
RISC-V	B-Device
implementations	O
.	O
</s>
<s>
In	O
2022	O
Steve	O
Furber	O
,	O
John	O
L	O
.	O
Hennessy	O
,	O
David	O
A	O
.	O
Patterson	O
and	O
Sophie	O
M	O
.	O
Wilson	O
were	O
awarded	O
the	O
Charles	O
Stark	O
Draper	O
Prize	O
by	O
the	O
United	O
States	O
National	O
Academy	O
of	O
Engineering	O
for	O
their	O
contributions	O
to	O
the	O
invention	O
,	O
development	O
,	O
and	O
implementation	O
of	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
chips	O
.	O
</s>
