<s>
Reconfigurable	B-Architecture
computing	I-Architecture
is	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
combining	O
some	O
of	O
the	O
flexibility	O
of	O
software	O
with	O
the	O
high	O
performance	O
of	O
hardware	O
by	O
processing	O
with	O
very	O
flexible	O
high	O
speed	O
computing	O
fabrics	O
like	O
field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGAs	B-Architecture
)	O
.	O
</s>
<s>
The	O
principal	O
difference	O
when	O
compared	O
to	O
using	O
ordinary	O
microprocessors	B-Architecture
is	O
the	O
ability	O
to	O
make	O
substantial	O
changes	O
to	O
the	O
datapath	B-General_Concept
itself	O
in	O
addition	O
to	O
the	O
control	O
flow	O
.	O
</s>
<s>
The	O
concept	O
of	O
reconfigurable	B-Architecture
computing	I-Architecture
has	O
existed	O
since	O
the	O
1960s	O
,	O
when	O
Gerald	O
Estrin	O
's	O
paper	O
proposed	O
the	O
concept	O
of	O
a	O
computer	O
made	O
of	O
a	O
standard	O
processor	O
and	O
an	O
array	O
of	O
"	O
reconfigurable	O
"	O
hardware	O
.	O
</s>
<s>
The	O
latter	O
would	O
then	O
be	O
tailored	O
to	O
perform	O
a	O
specific	O
task	O
,	O
such	O
as	O
image	B-Algorithm
processing	I-Algorithm
or	O
pattern	B-Language
matching	I-Language
,	O
as	O
quickly	O
as	O
a	O
dedicated	O
piece	O
of	O
hardware	O
.	O
</s>
<s>
Some	O
of	O
these	O
massively	O
parallel	O
reconfigurable	O
computers	O
were	O
built	O
primarily	O
for	O
special	O
subdomains	O
such	O
as	O
molecular	O
evolution	O
,	O
neural	O
or	O
image	B-Algorithm
processing	I-Algorithm
.	O
</s>
<s>
It	O
was	O
not	O
a	O
commercial	O
success	O
,	O
but	O
was	O
promising	O
enough	O
that	O
Xilinx	O
(	O
the	O
inventor	O
of	O
the	O
Field-Programmable	B-Architecture
Gate	I-Architecture
Array	I-Architecture
,	O
FPGA	B-Architecture
)	O
bought	O
the	O
technology	O
and	O
hired	O
the	O
Algotronix	O
staff	O
.	O
</s>
<s>
The	O
fundamental	O
model	O
of	O
the	O
reconfigurable	B-Architecture
computing	I-Architecture
machine	O
paradigm	O
,	O
the	O
data-stream-based	O
anti	B-General_Concept
machine	I-General_Concept
is	O
well	O
illustrated	O
by	O
the	O
differences	O
to	O
other	O
machine	O
paradigms	O
that	O
were	O
introduced	O
earlier	O
,	O
as	O
shown	O
by	O
Nick	O
Tredennick	O
's	O
following	O
classification	O
scheme	O
of	O
computing	O
paradigms	O
(	O
see	O
"	O
Table	O
1	O
:	O
Nick	O
Tredennick	O
’s	O
Paradigm	O
Classification	O
Scheme	O
"	O
)	O
.	O
</s>
<s>
Computer	O
scientist	O
Reiner	O
Hartenstein	O
describes	O
reconfigurable	B-Architecture
computing	I-Architecture
in	O
terms	O
of	O
an	O
anti-machine	B-General_Concept
that	O
,	O
according	O
to	O
him	O
,	O
represents	O
a	O
fundamental	O
paradigm	O
shift	O
away	O
from	O
the	O
more	O
conventional	O
von	B-Architecture
Neumann	I-Architecture
machine	I-Architecture
.	O
</s>
<s>
Hartenstein	O
calls	O
it	O
Reconfigurable	B-Architecture
Computing	I-Architecture
Paradox	I-Architecture
,	O
that	O
software-to-configware	O
(	O
software-to-FPGA	O
)	O
migration	O
results	O
in	O
reported	O
speed-up	O
factors	O
of	O
up	O
to	O
more	O
than	O
four	O
orders	O
of	O
magnitude	O
,	O
as	O
well	O
as	O
a	O
reduction	O
in	O
electricity	O
consumption	O
by	O
up	O
to	O
almost	O
four	O
orders	O
of	O
magnitude	O
—	O
although	O
the	O
technological	O
parameters	O
of	O
FPGAs	B-Architecture
are	O
behind	O
the	O
Gordon	O
Moore	O
curve	O
by	O
about	O
four	O
orders	O
of	O
magnitude	O
,	O
and	O
the	O
clock	O
frequency	O
is	O
substantially	O
lower	O
than	O
that	O
of	O
microprocessors	B-Architecture
.	O
</s>
<s>
High-Performance	O
Reconfigurable	B-Architecture
Computing	I-Architecture
(	O
HPRC	O
)	O
is	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
combining	O
reconfigurable	O
computing-based	O
accelerators	O
like	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
with	O
CPUs	O
or	O
multi-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
The	O
increase	O
of	O
logic	O
in	O
an	O
FPGA	B-Architecture
has	O
enabled	O
larger	O
and	O
more	O
complex	O
algorithms	O
to	O
be	O
programmed	O
into	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
The	O
attachment	O
of	O
such	O
an	O
FPGA	B-Architecture
to	O
a	O
modern	O
CPU	O
over	O
a	O
high	O
speed	O
bus	O
,	O
like	O
PCI	O
express	O
,	O
has	O
enabled	O
the	O
configurable	O
logic	O
to	O
act	O
more	O
like	O
a	O
coprocessor	B-General_Concept
rather	O
than	O
a	O
peripheral	O
.	O
</s>
<s>
This	O
has	O
brought	O
reconfigurable	B-Architecture
computing	I-Architecture
into	O
the	O
high-performance	B-Architecture
computing	I-Architecture
sphere	O
.	O
</s>
<s>
Furthermore	O
,	O
by	O
replicating	O
an	O
algorithm	O
on	O
an	O
FPGA	B-Architecture
or	O
the	O
use	O
of	O
a	O
multiplicity	O
of	O
FPGAs	B-Architecture
has	O
enabled	O
reconfigurable	O
SIMD	B-Device
systems	O
to	O
be	O
produced	O
where	O
several	O
computational	O
devices	O
can	O
concurrently	O
operate	O
on	O
different	O
data	O
,	O
which	O
is	O
highly	O
parallel	B-Operating_System
computing	I-Operating_System
.	O
</s>
<s>
This	O
heterogeneous	O
systems	O
technique	O
is	O
used	O
in	O
computing	O
research	O
and	O
especially	O
in	O
supercomputing	B-Architecture
.	O
</s>
<s>
Some	O
supercomputer	B-Architecture
firms	O
offer	O
heterogeneous	O
processing	O
blocks	O
including	O
FPGAs	B-Architecture
as	O
accelerators	O
.	O
</s>
<s>
The	O
US	O
National	O
Science	O
Foundation	O
has	O
a	O
center	O
for	O
high-performance	O
reconfigurable	B-Architecture
computing	I-Architecture
(	O
CHREC	O
)	O
.	O
</s>
<s>
In	O
April	O
2011	O
the	O
fourth	O
Many-core	O
and	O
Reconfigurable	O
Supercomputing	B-Architecture
Conference	O
was	O
held	O
in	O
Europe	O
.	O
</s>
<s>
Commercial	O
high-performance	O
reconfigurable	B-Architecture
computing	I-Architecture
systems	O
are	O
beginning	O
to	O
emerge	O
with	O
the	O
announcement	O
of	O
IBM	O
integrating	O
FPGAs	B-Architecture
with	O
its	O
IBM	B-Device
Power	I-Device
microprocessors	I-Device
.	O
</s>
<s>
Field	B-Architecture
programmable	I-Architecture
gate	I-Architecture
arrays	I-Architecture
are	O
often	O
used	O
as	O
a	O
support	O
to	O
partial	O
reconfiguration	O
.	O
</s>
<s>
In	O
many	O
cases	O
it	O
is	O
useful	O
to	O
be	O
able	O
to	O
swap	O
out	O
one	O
or	O
several	O
of	O
these	O
subcomponents	O
while	O
the	O
FPGA	B-Architecture
is	O
still	O
operating	O
.	O
</s>
<s>
Normally	O
,	O
reconfiguring	O
an	O
FPGA	B-Architecture
requires	O
it	O
to	O
be	O
held	O
in	O
reset	O
while	O
an	O
external	O
controller	O
reloads	O
a	O
design	O
onto	O
it	O
.	O
</s>
<s>
Partial	O
reconfiguration	O
allows	O
for	O
critical	O
parts	O
of	O
the	O
design	O
to	O
continue	O
operating	O
while	O
a	O
controller	O
either	O
on	O
the	O
FPGA	B-Architecture
or	O
off	O
of	O
it	O
loads	O
a	O
partial	O
design	O
into	O
a	O
reconfigurable	O
module	O
.	O
</s>
<s>
Partial	O
reconfiguration	O
is	O
not	O
supported	O
on	O
all	O
FPGAs	B-Architecture
.	O
</s>
<s>
Typically	O
the	O
design	O
modules	O
are	O
built	O
along	O
well	O
defined	O
boundaries	O
inside	O
the	O
FPGA	B-Architecture
that	O
require	O
the	O
design	O
to	O
be	O
specially	O
mapped	O
to	O
the	O
internal	O
hardware	O
.	O
</s>
<s>
dynamic	O
partial	O
reconfiguration	O
,	O
also	O
known	O
as	O
an	O
active	O
partial	O
reconfiguration	O
-	O
permits	O
to	O
change	O
the	O
part	O
of	O
the	O
device	O
while	O
the	O
rest	O
of	O
an	O
FPGA	B-Architecture
is	O
still	O
running	O
;	O
</s>
<s>
While	O
the	O
partial	O
data	O
is	O
sent	O
into	O
the	O
FPGA	B-Architecture
,	O
the	O
rest	O
of	O
the	O
device	O
is	O
stopped	O
(	O
in	O
the	O
shutdown	O
mode	O
)	O
and	O
brought	O
up	O
after	O
the	O
configuration	O
is	O
completed	O
.	O
</s>
<s>
With	O
the	O
advent	O
of	O
affordable	O
FPGA	B-Architecture
boards	I-Architecture
,	O
students	O
 '	O
and	O
hobbyists	O
 '	O
projects	O
seek	O
to	O
recreate	O
vintage	O
computers	O
or	O
implement	O
more	O
novel	O
architectures	O
.	O
</s>
<s>
Such	O
projects	O
are	O
built	O
with	O
reconfigurable	O
hardware	O
(	O
FPGAs	B-Architecture
)	O
,	O
and	O
some	O
devices	O
support	O
emulation	O
of	O
multiple	O
vintage	O
computers	O
using	O
a	O
single	O
reconfigurable	O
hardware	O
(	O
C-One	B-Device
)	O
.	O
</s>
<s>
A	O
fully	O
FPGA-based	O
computer	O
is	O
the	O
COPACOBANA	O
,	O
the	O
Cost	O
Optimized	O
Codebreaker	O
and	O
Analyzer	O
and	O
its	O
successor	O
RIVYERA	O
.	O
</s>
<s>
A	O
spin-off	O
company	O
SciEngines	B-Device
GmbH	I-Device
of	O
the	O
COPACOBANA-Project	O
of	O
the	O
Universities	O
of	O
Bochum	O
and	O
Kiel	O
in	O
Germany	O
continues	O
the	O
development	O
of	O
fully	O
FPGA-based	O
computers	O
.	O
</s>
<s>
Mitrionics	B-General_Concept
has	O
developed	O
a	O
SDK	O
that	O
enables	O
software	O
written	O
using	O
a	O
single	O
assignment	O
language	O
to	O
be	O
compiled	O
and	O
executed	O
on	O
FPGA-based	O
computers	O
.	O
</s>
<s>
The	O
Mitrion-C	O
software	O
language	O
and	O
Mitrion	B-General_Concept
processor	O
enable	O
software	O
developers	O
to	O
write	O
and	O
execute	O
applications	O
on	O
FPGA-based	O
computers	O
in	O
the	O
same	O
manner	O
as	O
with	O
other	O
computing	O
technologies	O
,	O
such	O
as	O
graphical	O
processing	O
units	O
(	O
“	O
GPUs	O
”	O
)	O
,	O
cell-based	O
processors	B-Architecture
,	O
parallel	B-Operating_System
processing	I-Operating_System
units	O
(	O
“	O
PPUs	O
”	O
)	O
,	O
multi-core	B-Architecture
CPUs	I-Architecture
,	O
and	O
traditional	O
single-core	O
CPU	O
clusters	O
.	O
</s>
<s>
National	O
Instruments	O
have	O
developed	O
a	O
hybrid	O
embedded	O
computing	O
system	O
called	O
CompactRIO	B-General_Concept
.	O
</s>
<s>
It	O
consists	O
of	O
reconfigurable	O
chassis	O
housing	O
the	O
user-programmable	O
FPGA	B-Architecture
,	O
hot	O
swappable	O
I/O	O
modules	O
,	O
real-time	O
controller	O
for	O
deterministic	O
communication	O
and	O
processing	O
,	O
and	O
graphical	O
LabVIEW	O
software	O
for	O
rapid	O
RT	O
and	O
FPGA	B-Architecture
programming	O
.	O
</s>
<s>
Xilinx	O
has	O
developed	O
two	O
styles	O
of	O
partial	O
reconfiguration	O
of	O
FPGA	B-Architecture
devices	O
:	O
module-based	O
and	O
difference-based	O
.	O
</s>
<s>
Intel	O
supports	O
partial	O
reconfiguration	O
of	O
their	O
FPGA	B-Architecture
devices	O
on	O
28nm	O
devices	O
such	O
as	O
Stratix	O
V	O
,	O
and	O
on	O
the	O
20nm	O
Arria	O
10	O
devices	O
.	O
</s>
<s>
The	O
Intel	O
FPGA	B-Architecture
partial	O
reconfiguration	O
flow	O
for	O
Arria	O
10	O
is	O
based	O
on	O
the	O
hierarchical	O
design	O
methodology	O
in	O
the	O
Quartus	O
Prime	O
Pro	O
software	O
where	O
users	O
create	O
physical	O
partitions	O
of	O
the	O
FPGA	B-Architecture
that	O
can	O
be	O
reconfigured	O
at	O
runtime	O
while	O
the	O
remainder	O
of	O
the	O
design	O
continues	O
to	O
operate	O
.	O
</s>
<s>
The	O
granularity	O
of	O
the	O
reconfigurable	B-Architecture
logic	I-Architecture
is	O
defined	O
as	O
the	O
size	O
of	O
the	O
smallest	O
functional	O
unit	O
(	O
configurable	O
logic	O
block	O
,	O
CLB	O
)	O
that	O
is	O
addressed	O
by	O
the	O
mapping	O
tools	O
.	O
</s>
<s>
Fine-grained	O
architectures	O
work	O
at	O
the	O
bit-level	O
manipulation	O
level	O
;	O
whilst	O
coarse	O
grained	O
processing	O
elements	O
(	O
reconfigurable	O
datapath	B-General_Concept
unit	O
,	O
rDPU	B-Architecture
)	O
are	O
better	O
optimised	O
for	O
standard	O
data	O
path	O
applications	O
.	O
</s>
<s>
This	O
problem	O
can	O
be	O
solved	O
by	O
having	O
a	O
coarse	O
grain	O
array	O
(	O
reconfigurable	O
datapath	B-General_Concept
array	O
,	O
rDPA	O
)	O
and	O
a	O
FPGA	B-Architecture
on	O
the	O
same	O
chip	O
.	O
</s>
<s>
Coarse-grained	O
architectures	O
(	O
rDPA	O
)	O
are	O
intended	O
for	O
the	O
implementation	O
for	O
algorithms	O
needing	O
word-width	O
data	O
paths	O
(	O
rDPU	B-Architecture
)	O
.	O
</s>
<s>
As	O
their	O
functional	O
blocks	O
are	O
optimized	O
for	O
large	O
computations	O
and	O
typically	O
comprise	O
word	O
wide	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALU	O
)	O
,	O
they	O
will	O
perform	O
these	O
computations	O
more	O
quickly	O
and	O
with	O
more	O
power	O
efficiency	O
than	O
a	O
set	O
of	O
interconnected	O
smaller	O
functional	O
units	O
;	O
this	O
is	O
due	O
to	O
the	O
connecting	O
wires	O
being	O
shorter	O
,	O
resulting	O
in	O
less	O
wire	O
capacitance	O
and	O
hence	O
faster	O
and	O
lower	O
power	O
designs	O
.	O
</s>
<s>
Examples	O
of	O
this	O
are	O
domain	O
specific	O
arrays	O
aimed	O
at	O
gaining	O
better	O
performance	O
in	O
terms	O
of	O
power	O
,	O
area	O
,	O
throughput	O
than	O
their	O
more	O
generic	O
finer	O
grained	O
FPGA	B-Architecture
cousins	O
by	O
reducing	O
their	O
flexibility	O
.	O
</s>
<s>
Configuration	O
of	O
these	O
reconfigurable	B-Architecture
systems	I-Architecture
can	O
happen	O
at	O
deployment	O
time	O
,	O
between	O
execution	O
phases	O
or	O
during	O
execution	O
.	O
</s>
<s>
In	O
a	O
typical	O
reconfigurable	B-Architecture
system	I-Architecture
,	O
a	O
bit	O
stream	O
is	O
used	O
to	O
program	O
the	O
device	O
at	O
deployment	O
time	O
.	O
</s>
<s>
The	O
level	O
of	O
coupling	O
determines	O
the	O
type	O
of	O
data	O
transfers	O
,	O
latency	O
,	O
power	O
,	O
throughput	O
and	O
overheads	O
involved	O
when	O
utilising	O
the	O
reconfigurable	B-Architecture
logic	I-Architecture
.	O
</s>
<s>
Some	O
of	O
the	O
most	O
intuitive	O
designs	O
use	O
a	O
peripheral	O
bus	O
to	O
provide	O
a	O
coprocessor	B-General_Concept
like	O
arrangement	O
for	O
the	O
reconfigurable	O
array	O
.	O
</s>
<s>
One	O
style	O
of	O
interconnect	O
made	O
popular	O
by	O
FPGAs	B-Architecture
vendors	O
,	O
Xilinx	O
and	O
Altera	O
are	O
the	O
island	O
style	O
layout	O
,	O
where	O
blocks	O
are	O
arranged	O
in	O
an	O
array	O
with	O
vertical	O
and	O
horizontal	O
routing	O
.	O
</s>
<s>
One	O
of	O
the	O
key	O
challenges	O
for	O
reconfigurable	B-Architecture
computing	I-Architecture
is	O
to	O
enable	O
higher	O
design	O
productivity	O
and	O
provide	O
an	O
easier	O
way	O
to	O
use	O
reconfigurable	B-Architecture
computing	I-Architecture
systems	O
for	O
users	O
that	O
are	O
unfamiliar	O
with	O
the	O
underlying	O
concepts	O
.	O
</s>
<s>
This	O
can	O
be	O
relaxed	O
by	O
the	O
concept	O
of	O
threads	O
,	O
allowing	O
different	O
tasks	O
to	O
run	O
concurrently	O
on	O
this	O
virtual	O
hardware	O
to	O
exploit	O
task	O
level	O
parallelism	B-Operating_System
.	O
</s>
<s>
In	O
addition	O
to	O
abstraction	O
,	O
resource	O
management	O
of	O
the	O
underlying	O
hardware	O
components	O
is	O
necessary	O
because	O
the	O
virtual	O
computers	O
provided	O
to	O
the	O
processes	O
and	O
threads	O
by	O
the	O
operating	O
system	O
need	O
to	O
share	O
available	O
physical	O
resources	O
(	O
processors	B-Architecture
,	O
memory	O
,	O
and	O
devices	O
)	O
spatially	O
and	O
temporarily	O
.	O
</s>
